319 lines
7.1 KiB
ArmAsm
319 lines
7.1 KiB
ArmAsm
# Copyright 2018 Canaan Inc.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#include "encoding.h"
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# define LREG ld
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# define SREG sd
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# define LFREG flw
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# define SFREG fsw
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# define REGBYTES 8
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# define STKSHIFT 15
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.section .text.start, "ax", @progbits
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.globl _start
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_start:
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j 1f
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.word 0xdeadbeef
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.align 3
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.global g_wake_up
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g_wake_up:
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.dword 1
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.dword 0
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1:
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csrw mideleg, 0
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csrw medeleg, 0
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csrw mie, 0
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csrw mip, 0
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la t0, trap_entry
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csrw mtvec, t0
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li x1, 0
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li x2, 0
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li x3, 0
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li x4, 0
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li x5, 0
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li x6, 0
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li x7, 0
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li x8, 0
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li x9, 0
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li x10,0
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li x11,0
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li x12,0
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li x13,0
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li x14,0
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li x15,0
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li x16,0
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li x17,0
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li x18,0
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li x19,0
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li x20,0
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li x21,0
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li x22,0
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li x23,0
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li x24,0
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li x25,0
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li x26,0
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li x27,0
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li x28,0
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li x29,0
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li x30,0
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li x31,0
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li t0, MSTATUS_FS
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csrs mstatus, t0
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fssr x0
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fmv.w.x f0, x0
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fmv.w.x f1, x0
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fmv.w.x f2, x0
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fmv.w.x f3, x0
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fmv.w.x f4, x0
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fmv.w.x f5, x0
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fmv.w.x f6, x0
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fmv.w.x f7, x0
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fmv.w.x f8, x0
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fmv.w.x f9, x0
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fmv.w.x f10,x0
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fmv.w.x f11,x0
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fmv.w.x f12,x0
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fmv.w.x f13,x0
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fmv.w.x f14,x0
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fmv.w.x f15,x0
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fmv.w.x f16,x0
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fmv.w.x f17,x0
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fmv.w.x f18,x0
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fmv.w.x f19,x0
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fmv.w.x f20,x0
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fmv.w.x f21,x0
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fmv.w.x f22,x0
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fmv.w.x f23,x0
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fmv.w.x f24,x0
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fmv.w.x f25,x0
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fmv.w.x f26,x0
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fmv.w.x f27,x0
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fmv.w.x f28,x0
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fmv.w.x f29,x0
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fmv.w.x f30,x0
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fmv.w.x f31,x0
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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la tp, _end + 63
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and tp, tp, -64
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csrr a0, mhartid
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add sp, a0, 1
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sll sp, sp, STKSHIFT
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add sp, sp, tp
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j _init_bsp
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.globl trap_entry
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.type trap_entry, @function
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.align 2
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trap_entry:
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addi sp, sp, -REGBYTES
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sd t0, 0x0(sp)
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csrr t0, mcause
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bgez t0, .handle_other
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# Test soft interrupt
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slli t0, t0, 1
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addi t0, t0, -(IRQ_M_SOFT << 1)
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bnez t0, .handle_other
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# Interupt is soft interrupt
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# Get event
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addi sp, sp, -REGBYTES
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sd t1, 0x0(sp)
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la t0, g_core_pending_switch
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csrr t1, mhartid
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slli t1, t1, 3
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add t0, t0, t1
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ld t1, 0x0(sp)
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addi sp, sp, REGBYTES
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# Test ContextSwitch event
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ld t0, 0x0(t0)
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beqz t0, .handle_other
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ld t0, 0x0(sp)
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addi sp, sp, REGBYTES
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# Do not use jal here
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j xPortSysTickInt
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mret
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.handle_other:
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ld t0, 0x0(sp)
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addi sp, sp, REGBYTES
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addi sp, sp, -64*REGBYTES
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SREG x1, 1*REGBYTES(sp)
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SREG x2, 2*REGBYTES(sp)
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SREG x3, 3*REGBYTES(sp)
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SREG x4, 4*REGBYTES(sp)
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SREG x5, 5*REGBYTES(sp)
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SREG x6, 6*REGBYTES(sp)
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SREG x7, 7*REGBYTES(sp)
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SREG x8, 8*REGBYTES(sp)
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SREG x9, 9*REGBYTES(sp)
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SREG x10, 10*REGBYTES(sp)
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SREG x11, 11*REGBYTES(sp)
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SREG x12, 12*REGBYTES(sp)
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SREG x13, 13*REGBYTES(sp)
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SREG x14, 14*REGBYTES(sp)
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SREG x15, 15*REGBYTES(sp)
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SREG x16, 16*REGBYTES(sp)
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SREG x17, 17*REGBYTES(sp)
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SREG x18, 18*REGBYTES(sp)
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SREG x19, 19*REGBYTES(sp)
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SREG x20, 20*REGBYTES(sp)
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SREG x21, 21*REGBYTES(sp)
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SREG x22, 22*REGBYTES(sp)
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SREG x23, 23*REGBYTES(sp)
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SREG x24, 24*REGBYTES(sp)
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SREG x25, 25*REGBYTES(sp)
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SREG x26, 26*REGBYTES(sp)
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SREG x27, 27*REGBYTES(sp)
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SREG x28, 28*REGBYTES(sp)
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SREG x29, 29*REGBYTES(sp)
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SREG x30, 30*REGBYTES(sp)
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SREG x31, 31*REGBYTES(sp)
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SFREG f0, ( 0 + 32)*REGBYTES(sp)
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SFREG f1, ( 1 + 32)*REGBYTES(sp)
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SFREG f2, ( 2 + 32)*REGBYTES(sp)
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SFREG f3, ( 3 + 32)*REGBYTES(sp)
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SFREG f4, ( 4 + 32)*REGBYTES(sp)
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SFREG f5, ( 5 + 32)*REGBYTES(sp)
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SFREG f6, ( 6 + 32)*REGBYTES(sp)
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SFREG f7, ( 7 + 32)*REGBYTES(sp)
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SFREG f8, ( 8 + 32)*REGBYTES(sp)
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SFREG f9, ( 9 + 32)*REGBYTES(sp)
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SFREG f10,( 10 + 32)*REGBYTES(sp)
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SFREG f11,( 11 + 32)*REGBYTES(sp)
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SFREG f12,( 12 + 32)*REGBYTES(sp)
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SFREG f13,( 13 + 32)*REGBYTES(sp)
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SFREG f14,( 14 + 32)*REGBYTES(sp)
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SFREG f15,( 15 + 32)*REGBYTES(sp)
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SFREG f16,( 16 + 32)*REGBYTES(sp)
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SFREG f17,( 17 + 32)*REGBYTES(sp)
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SFREG f18,( 18 + 32)*REGBYTES(sp)
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SFREG f19,( 19 + 32)*REGBYTES(sp)
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SFREG f20,( 20 + 32)*REGBYTES(sp)
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SFREG f21,( 21 + 32)*REGBYTES(sp)
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SFREG f22,( 22 + 32)*REGBYTES(sp)
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SFREG f23,( 23 + 32)*REGBYTES(sp)
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SFREG f24,( 24 + 32)*REGBYTES(sp)
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SFREG f25,( 25 + 32)*REGBYTES(sp)
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SFREG f26,( 26 + 32)*REGBYTES(sp)
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SFREG f27,( 27 + 32)*REGBYTES(sp)
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SFREG f28,( 28 + 32)*REGBYTES(sp)
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SFREG f29,( 29 + 32)*REGBYTES(sp)
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SFREG f30,( 30 + 32)*REGBYTES(sp)
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SFREG f31,( 31 + 32)*REGBYTES(sp)
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csrr a0, mcause
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csrr a1, mepc
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mv a2, sp
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add a3, sp, 32*REGBYTES
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bgez a0, .handle_syscall
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.handle_irq:
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jal handle_irq
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j .restore
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.handle_syscall:
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jal handle_syscall
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.restore:
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csrw mepc, a0
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LREG x1, 1*REGBYTES(sp)
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LREG x2, 2*REGBYTES(sp)
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LREG x3, 3*REGBYTES(sp)
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LREG x4, 4*REGBYTES(sp)
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LREG x5, 5*REGBYTES(sp)
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LREG x6, 6*REGBYTES(sp)
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LREG x7, 7*REGBYTES(sp)
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LREG x8, 8*REGBYTES(sp)
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LREG x9, 9*REGBYTES(sp)
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LREG x10, 10*REGBYTES(sp)
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LREG x11, 11*REGBYTES(sp)
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LREG x12, 12*REGBYTES(sp)
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LREG x13, 13*REGBYTES(sp)
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LREG x14, 14*REGBYTES(sp)
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LREG x15, 15*REGBYTES(sp)
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LREG x16, 16*REGBYTES(sp)
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LREG x17, 17*REGBYTES(sp)
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LREG x18, 18*REGBYTES(sp)
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LREG x19, 19*REGBYTES(sp)
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LREG x20, 20*REGBYTES(sp)
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LREG x21, 21*REGBYTES(sp)
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LREG x22, 22*REGBYTES(sp)
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LREG x23, 23*REGBYTES(sp)
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LREG x24, 24*REGBYTES(sp)
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LREG x25, 25*REGBYTES(sp)
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LREG x26, 26*REGBYTES(sp)
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LREG x27, 27*REGBYTES(sp)
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LREG x28, 28*REGBYTES(sp)
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LREG x29, 29*REGBYTES(sp)
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LREG x30, 30*REGBYTES(sp)
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LREG x31, 31*REGBYTES(sp)
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LFREG f0, ( 0 + 32)*REGBYTES(sp)
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LFREG f1, ( 1 + 32)*REGBYTES(sp)
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LFREG f2, ( 2 + 32)*REGBYTES(sp)
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LFREG f3, ( 3 + 32)*REGBYTES(sp)
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LFREG f4, ( 4 + 32)*REGBYTES(sp)
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LFREG f5, ( 5 + 32)*REGBYTES(sp)
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LFREG f6, ( 6 + 32)*REGBYTES(sp)
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LFREG f7, ( 7 + 32)*REGBYTES(sp)
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LFREG f8, ( 8 + 32)*REGBYTES(sp)
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LFREG f9, ( 9 + 32)*REGBYTES(sp)
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LFREG f10,( 10 + 32)*REGBYTES(sp)
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LFREG f11,( 11 + 32)*REGBYTES(sp)
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LFREG f12,( 12 + 32)*REGBYTES(sp)
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LFREG f13,( 13 + 32)*REGBYTES(sp)
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LFREG f14,( 14 + 32)*REGBYTES(sp)
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LFREG f15,( 15 + 32)*REGBYTES(sp)
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LFREG f16,( 16 + 32)*REGBYTES(sp)
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LFREG f17,( 17 + 32)*REGBYTES(sp)
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LFREG f18,( 18 + 32)*REGBYTES(sp)
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LFREG f19,( 19 + 32)*REGBYTES(sp)
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LFREG f20,( 20 + 32)*REGBYTES(sp)
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LFREG f21,( 21 + 32)*REGBYTES(sp)
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LFREG f22,( 22 + 32)*REGBYTES(sp)
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LFREG f23,( 23 + 32)*REGBYTES(sp)
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LFREG f24,( 24 + 32)*REGBYTES(sp)
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LFREG f25,( 25 + 32)*REGBYTES(sp)
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LFREG f26,( 26 + 32)*REGBYTES(sp)
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LFREG f27,( 27 + 32)*REGBYTES(sp)
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LFREG f28,( 28 + 32)*REGBYTES(sp)
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LFREG f29,( 29 + 32)*REGBYTES(sp)
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LFREG f30,( 30 + 32)*REGBYTES(sp)
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LFREG f31,( 31 + 32)*REGBYTES(sp)
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addi sp, sp, 64*REGBYTES
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mret
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.section ".tdata.begin"
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.globl _tdata_begin
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_tdata_begin:
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.section ".tdata.end"
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.globl _tdata_end
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_tdata_end:
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.section ".tbss.end"
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.globl _tbss_end
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_tbss_end:
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