modify spi slave driver
This commit is contained in:
jiangxiangbing
parent
a8f5ea747e
commit
a454a6e4d2
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@ -157,18 +157,47 @@ typedef enum _spi_chip_select
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SPI_CHIP_SELECT_MAX,
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} spi_chip_select_t;
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typedef enum _spi_slave_event
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{
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SPI_EV_TRANS,
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SPI_EV_RECV,
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} spi_slave_event_t;
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typedef enum {
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WRITE_CONFIG,
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READ_CONFIG,
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WRITE_DATA_BYTE,
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READ_DATA_BYTE,
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WRITE_DATA_BLOCK,
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READ_DATA_BLOCK,
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} spi_slave_command_e;
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typedef struct _spi_slave_handler
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typedef struct
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{
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void (*on_receive)(uint32_t data);
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uint32_t (*on_transmit)(uint32_t data);
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spi_slave_event_t (*on_event)(uint32_t data);
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} spi_slave_handler_t;
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uint8_t cmd;
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uint8_t err;
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uint32_t addr;
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uint32_t len;
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} spi_slave_command_t;
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typedef enum
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{
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IDLE,
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COMMAND,
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TRANSFER,
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} spi_slave_status_e;
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typedef int (*spi_slave_receive_callback_t)(void *ctx);
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typedef struct _spi_slave_instance
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{
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uint8_t int_pin;
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uint8_t ready_pin;
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dmac_channel_number_t dmac_channel;
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uint8_t dfs;
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uint8_t slv_oe;
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uint8_t work_mode;
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size_t data_bit_length;
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volatile spi_slave_status_e status;
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volatile spi_slave_command_t command;
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volatile uint8_t *config_ptr;
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uint32_t config_len;
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spi_slave_receive_callback_t callback;
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} spi_slave_instance_t;
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extern volatile spi_t *const spi[4];
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@ -186,16 +215,6 @@ extern volatile spi_t *const spi[4];
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void spi_init(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_format_t frame_format,
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size_t data_bit_length, uint32_t endian);
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/**
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* @brief Set spi slave configuration
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*
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* @param[in] data_bit_length Spi data bit length
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* @param[in] handler Handle of spi slave interrupt function.
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*
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* @return Void
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*/
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void spi_slave_config(size_t data_bit_length, const spi_slave_handler_t *handler);
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/**
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* @brief Set multiline configuration
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*
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@ -419,6 +438,21 @@ void spi_dup_send_receive_data_dma(dmac_channel_number_t dma_send_channel_num,
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spi_device_num_t spi_num, spi_chip_select_t chip_select,
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const uint8_t *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len);
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/**
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* @brief Set spi slave configuration
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*
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* @param[in] int_pin SPI master starts sending data interrupt.
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* @param[in] ready_pin SPI slave ready.
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* @param[in] dmac_channel Dmac channel number for block.
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* @param[in] data_bit_length Spi data bit length
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* @param[in] data SPI slave device data buffer.
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* @param[in] len The length of SPI slave device data buffer.
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* @param[in] callback Callback of spi slave.
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*
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* @return Void
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*/
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void spi_slave_config(uint8_t int_pin, uint8_t ready_pin, dmac_channel_number_t dmac_channel, size_t data_bit_length, uint8_t *data, uint32_t len, spi_slave_receive_callback_t callback);
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#ifdef __cplusplus
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}
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#endif
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@ -16,16 +16,10 @@
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#include "spi.h"
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#include "fpioa.h"
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#include "utils.h"
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#include "gpiohs.h"
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#include "sysctl.h"
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#include <stddef.h>
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#include <stdlib.h>
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typedef struct _spi_slave_context
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{
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size_t data_bit_length;
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const spi_slave_handler_t *handler;
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} spi_slave_context_t;
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static spi_slave_context_t spi_slave_context;
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volatile spi_t *const spi[4] =
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{
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@ -35,6 +29,8 @@ volatile spi_t *const spi[4] =
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(volatile spi_t *)SPI3_BASE_ADDR
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};
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static spi_slave_instance_t g_instance;
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static spi_frame_format_t spi_get_frame_format(spi_device_num_t spi_num)
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{
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uint8_t frf_offset;
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@ -150,66 +146,6 @@ void spi_init(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_for
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spi_adapter->endian = endian;
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}
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int spi_slave_irq(void *userdata)
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{
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spi_slave_context_t *context = (spi_slave_context_t *)userdata;
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volatile spi_t *spi_adapter = spi[2];
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uint8_t isr = spi_adapter->isr;
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uint32_t data;
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uint32_t transmit_data;
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uint8_t dfs_offset = 16, slv_oe = 10, work_mode_offset = 6;
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if (isr & 0x10)
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{
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data = spi_adapter->dr[0];
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if(context->handler->on_event(data) == SPI_EV_RECV)
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{
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context->handler->on_receive(data);
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}
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if(context->handler->on_event(data) == SPI_EV_TRANS)
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{
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transmit_data = context->handler->on_transmit(data);
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spi_adapter->ssienr = 0x00;
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spi_adapter->ctrlr0 = (0x0 << work_mode_offset) | (0x0 << slv_oe) | ((context->data_bit_length - 1) << dfs_offset);
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spi_set_tmod(2, SPI_TMOD_TRANS);
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spi_adapter->ssienr = 0x01;
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spi_adapter->dr[0] = transmit_data;
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spi_adapter->dr[0] = transmit_data;
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spi_adapter->imr = 0x00000001;
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}
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}
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if (isr & 0x01)
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{
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spi_adapter->ssienr = 0x00;
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spi_adapter->ctrlr0 = (0x0 << work_mode_offset) | (0x1 << slv_oe) | ((context->data_bit_length - 1) << dfs_offset);
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spi_set_tmod(2, SPI_TMOD_RECV);
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spi_adapter->imr = 0x00000010;
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spi_adapter->ssienr = 0x01;
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}
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return 0;
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}
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void spi_slave_config(size_t data_bit_length, const spi_slave_handler_t *handler)
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{
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sysctl_reset(SYSCTL_RESET_SPI2);
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sysctl_clock_enable(SYSCTL_CLOCK_SPI2);
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sysctl_clock_set_threshold(SYSCTL_THRESHOLD_SPI2, 0);
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spi_slave_context.data_bit_length = data_bit_length;
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spi_slave_context.handler = handler;
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uint8_t dfs_offset = 16, slv_oe = 10, work_mode_offset = 6;
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volatile spi_t *spi_adapter = spi[2];
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spi_adapter->ssienr = 0x00;
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spi_adapter->ctrlr0 = (0x0 << work_mode_offset) | (0x1 << slv_oe) | ((data_bit_length - 1) << dfs_offset);
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spi_adapter->txftlr = 0x00000000;
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spi_adapter->rxftlr = 0x00000000;
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spi_adapter->imr = 0x00000010;
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spi_adapter->ssienr = 0x01;
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plic_set_priority(IRQN_SPI_SLAVE_INTERRUPT, 1);
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plic_irq_enable(IRQN_SPI_SLAVE_INTERRUPT);
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plic_irq_register(IRQN_SPI_SLAVE_INTERRUPT, spi_slave_irq, &spi_slave_context);
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}
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void spi_init_non_standard(spi_device_num_t spi_num, uint32_t instruction_length, uint32_t address_length,
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uint32_t wait_cycles, spi_instruction_address_trans_mode_t instruction_address_trans_mode)
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{
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@ -1036,3 +972,327 @@ void spi_fill_data_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_n
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spi_handle->ssienr = 0x00;
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}
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static int spi_slave_irq(void *ctx)
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{
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volatile spi_t *spi_handle = spi[2];
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spi_handle->imr = 0x00;
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*(volatile uint32_t *)(spi_handle->icr);
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if (g_instance.status == IDLE)
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g_instance.status = COMMAND;
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return 0;
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}
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static void spi_slave_idle_mode(void)
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{
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volatile spi_t *spi_handle = spi[2];
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uint32_t data_width = g_instance.data_bit_length / 8;
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g_instance.status = IDLE;
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spi_handle->ssienr = 0x00;
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spi_handle->ctrlr0 = (0x0 << g_instance.work_mode) | (0x1 << g_instance.slv_oe) | ((g_instance.data_bit_length - 1) << g_instance.dfs);
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spi_handle->rxftlr = 0x08 / data_width - 1;
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spi_handle->dmacr = 0x00;
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spi_handle->imr = 0x10;
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spi_handle->ssienr = 0x01;
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gpiohs_set_pin(g_instance.ready_pin, GPIO_PV_HIGH);
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}
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static void spi_slave_command_mode(void)
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{
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volatile spi_t *spi_handle = spi[2];
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uint8_t cmd_data[8], sum = 0;
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spi_transfer_width_t frame_width = spi_get_frame_size(g_instance.data_bit_length - 1);
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uint32_t data_width = g_instance.data_bit_length / 8;
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spi_device_num_t spi_num = SPI_DEVICE_2;
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switch(frame_width)
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{
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case SPI_TRANS_INT:
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for (uint32_t i = 0; i < 8 / 4; i++)
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((uint32_t *)cmd_data)[i] = spi_handle->dr[0];
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break;
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case SPI_TRANS_SHORT:
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for (uint32_t i = 0; i < 8 / 2; i++)
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((uint16_t *)cmd_data)[i] = spi_handle->dr[0];
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break;
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default:
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for (uint32_t i = 0; i < 8; i++)
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cmd_data[i] = spi_handle->dr[0];
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break;
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}
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for (uint32_t i = 0; i < 7; i++)
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{
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sum += cmd_data[i];
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}
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if (cmd_data[7] != sum)
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{
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spi_slave_idle_mode();
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return;
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}
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g_instance.command.cmd = cmd_data[0];
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g_instance.command.addr = cmd_data[1] | (cmd_data[2] << 8) | (cmd_data[3] << 16) | (cmd_data[4] << 24);
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g_instance.command.len = cmd_data[5] | (cmd_data[6] << 8);
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if (g_instance.command.len == 0)
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g_instance.command.len = 65536;
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if ((g_instance.command.cmd < WRITE_DATA_BLOCK) && (g_instance.command.len > 8))
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{
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spi_slave_idle_mode();
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return;
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}
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g_instance.status = TRANSFER;
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spi_handle->ssienr = 0x00;
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if (g_instance.command.cmd == WRITE_CONFIG)
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{
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spi_handle->ctrlr0 = (0x0 << g_instance.work_mode) | (0x1 << g_instance.slv_oe) | ((g_instance.data_bit_length - 1) << g_instance.dfs);
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spi[2]->rxftlr = g_instance.command.len / data_width - 1;
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spi_handle->imr = 0x00;
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spi_handle->ssienr = 0x01;
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}
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else if (g_instance.command.cmd == READ_CONFIG)
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{
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spi_handle->ctrlr0 = (0x0 << g_instance.work_mode) | (0x0 << g_instance.slv_oe) | ((g_instance.data_bit_length - 1) << g_instance.dfs);
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spi_set_tmod(2, SPI_TMOD_TRANS);
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spi_handle->txftlr = 0x00;
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spi_handle->imr = 0x00;
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spi_handle->ssienr = 0x01;
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switch(frame_width)
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{
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case SPI_TRANS_INT:
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for (uint32_t i = 0; i < g_instance.command.len / 4; i++)
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{
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spi_handle->dr[0] = ((uint32_t *)&g_instance.config_ptr[g_instance.command.addr])[i];
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}
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break;
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case SPI_TRANS_SHORT:
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for (uint32_t i = 0; i < g_instance.command.len / 2; i++)
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{
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spi_handle->dr[0] = ((uint16_t *)&g_instance.config_ptr[g_instance.command.addr])[i];
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}
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break;
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default:
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for (uint32_t i = 0; i < g_instance.command.len; i++)
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{
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spi_handle->dr[0] = ((uint8_t *)&g_instance.config_ptr[g_instance.command.addr])[i];
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}
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break;
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}
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}
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else if (g_instance.command.cmd == WRITE_DATA_BYTE)
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{
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spi_handle->ctrlr0 = (0x0 << g_instance.work_mode) | (0x1 << g_instance.slv_oe) | ((g_instance.data_bit_length - 1) << g_instance.dfs);
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spi[2]->rxftlr = g_instance.command.len / data_width - 1;
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spi_handle->imr = 0x00;
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spi_handle->ssienr = 0x01;
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}
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else if (g_instance.command.cmd == READ_DATA_BYTE)
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{
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spi_handle->ctrlr0 = (0x0 << g_instance.work_mode) | (0x0 << g_instance.slv_oe) | ((g_instance.data_bit_length - 1) << g_instance.dfs);
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spi_set_tmod(2, SPI_TMOD_TRANS);
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spi_handle->txftlr = 0x00;
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spi_handle->imr = 0x00;
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spi_handle->ssienr = 0x01;
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switch(frame_width)
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{
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case SPI_TRANS_INT:
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for (uint32_t i = 0; i < g_instance.command.len / 4; i++)
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{
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spi_handle->dr[0] = ((uint32_t *)g_instance.command.addr)[i];
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}
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break;
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case SPI_TRANS_SHORT:
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for (uint32_t i = 0; i < g_instance.command.len / 2; i++)
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{
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spi_handle->dr[0] = ((uint16_t *)g_instance.command.addr)[i];
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}
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break;
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default:
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for (uint32_t i = 0; i < g_instance.command.len; i++)
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{
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spi_handle->dr[0] = ((uint8_t *)g_instance.command.addr)[i];
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}
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break;
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}
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}
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else if (g_instance.command.cmd == WRITE_DATA_BLOCK)
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{
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spi_handle->ctrlr0 = (0x0 << g_instance.work_mode) | (0x1 << g_instance.slv_oe) | ((32 - 1) << g_instance.dfs);
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spi_handle->dmacr = 0x01;
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spi_handle->imr = 0x00;
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spi_handle->ssienr = 0x01;
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sysctl_dma_select(g_instance.dmac_channel, SYSCTL_DMA_SELECT_SSI0_RX_REQ + spi_num * 2);
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dmac_set_single_mode(g_instance.dmac_channel, (void *)(&spi_handle->dr[0]), (void *)(g_instance.command.addr & 0xFFFFFFF0), DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
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DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, g_instance.command.len * 4);
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}
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else if (g_instance.command.cmd == READ_DATA_BLOCK)
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{
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spi_handle->ctrlr0 = (0x0 << g_instance.work_mode) | (0x0 << g_instance.slv_oe) | ((32 - 1) << g_instance.dfs);
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spi_set_tmod(2, SPI_TMOD_TRANS);
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spi_handle->dmacr = 0x02;
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spi_handle->imr = 0x00;
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spi_handle->ssienr = 0x01;
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sysctl_dma_select(g_instance.dmac_channel, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2);
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dmac_set_single_mode(g_instance.dmac_channel, (void *)(g_instance.command.addr & 0xFFFFFFF0), (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
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DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, g_instance.command.len * 4);
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}
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else
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{
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spi_slave_idle_mode();
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return;
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}
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gpiohs_set_pin(g_instance.ready_pin, GPIO_PV_LOW);
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}
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static void spi_slave_transfer_mode(void)
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{
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spi_transfer_width_t frame_width = spi_get_frame_size(g_instance.data_bit_length - 1);
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uint32_t command_len = 0;
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switch(frame_width)
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{
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case SPI_TRANS_INT:
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command_len = g_instance.command.len / 4;
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break;
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case SPI_TRANS_SHORT:
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command_len = g_instance.command.len / 2;
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break;
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default:
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command_len = g_instance.command.len;
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break;
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}
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volatile spi_t *spi_handle = spi[2];
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g_instance.command.err = 0;
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if (g_instance.command.cmd == WRITE_CONFIG || g_instance.command.cmd == WRITE_DATA_BYTE)
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{
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if (spi_handle->rxflr < command_len - 1)
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g_instance.command.err = 1;
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}
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else if (g_instance.command.cmd == READ_CONFIG || g_instance.command.cmd == READ_DATA_BYTE)
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{
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if (spi_handle->txflr != 0)
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g_instance.command.err = 2;
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} else if (g_instance.command.cmd == WRITE_DATA_BLOCK || g_instance.command.cmd == READ_DATA_BLOCK)
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{
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if (dmac->channel[g_instance.dmac_channel].intstatus != 0x02)
|
||||
g_instance.command.err = 3;
|
||||
}
|
||||
else
|
||||
{
|
||||
spi_slave_idle_mode();
|
||||
return;
|
||||
}
|
||||
|
||||
if (g_instance.command.err == 0)
|
||||
{
|
||||
if (g_instance.command.cmd == WRITE_CONFIG)
|
||||
{
|
||||
switch(frame_width)
|
||||
{
|
||||
case SPI_TRANS_INT:
|
||||
for (uint32_t i = 0; i < command_len; i++)
|
||||
{
|
||||
((uint32_t *)&g_instance.config_ptr[g_instance.command.addr])[i] = spi_handle->dr[0];
|
||||
}
|
||||
break;
|
||||
case SPI_TRANS_SHORT:
|
||||
for (uint32_t i = 0; i < command_len; i++)
|
||||
{
|
||||
((uint16_t *)&g_instance.config_ptr[g_instance.command.addr])[i] = spi_handle->dr[0];
|
||||
}
|
||||
break;
|
||||
default:
|
||||
for (uint32_t i = 0; i < command_len; i++)
|
||||
{
|
||||
((uint8_t *)&g_instance.config_ptr[g_instance.command.addr])[i] = spi_handle->dr[0];
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (g_instance.command.cmd == WRITE_DATA_BYTE)
|
||||
{
|
||||
switch(frame_width)
|
||||
{
|
||||
case SPI_TRANS_INT:
|
||||
for (uint32_t i = 0; i < command_len; i++)
|
||||
{
|
||||
((uint32_t *)g_instance.command.addr)[i] = spi_handle->dr[0];
|
||||
}
|
||||
break;
|
||||
case SPI_TRANS_SHORT:
|
||||
for (uint32_t i = 0; i < command_len; i++)
|
||||
{
|
||||
((uint16_t *)g_instance.command.addr)[i] = spi_handle->dr[0];
|
||||
}
|
||||
break;
|
||||
default:
|
||||
for (uint32_t i = 0; i < command_len; i++)
|
||||
{
|
||||
((uint8_t *)g_instance.command.addr)[i] = spi_handle->dr[0];
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
if(g_instance.callback != NULL)
|
||||
{
|
||||
g_instance.callback((void *)&g_instance.command);
|
||||
}
|
||||
spi_slave_idle_mode();
|
||||
}
|
||||
|
||||
static void spi_slave_cs_irq(void)
|
||||
{
|
||||
if (g_instance.status == IDLE)
|
||||
spi_slave_idle_mode();
|
||||
else if (g_instance.status == COMMAND)
|
||||
spi_slave_command_mode();
|
||||
else if (g_instance.status == TRANSFER)
|
||||
spi_slave_transfer_mode();
|
||||
}
|
||||
|
||||
void spi_slave_config(uint8_t int_pin, uint8_t ready_pin, dmac_channel_number_t dmac_channel, size_t data_bit_length, uint8_t *data, uint32_t len, spi_slave_receive_callback_t callback)
|
||||
{
|
||||
g_instance.status = IDLE;
|
||||
g_instance.config_ptr = data;
|
||||
g_instance.config_len = len;
|
||||
g_instance.work_mode = 6;
|
||||
g_instance.slv_oe = 10;
|
||||
g_instance.dfs = 16;
|
||||
g_instance.data_bit_length = data_bit_length;
|
||||
g_instance.ready_pin = ready_pin;
|
||||
g_instance.int_pin = int_pin;
|
||||
g_instance.callback = callback;
|
||||
g_instance.dmac_channel = dmac_channel;
|
||||
sysctl_reset(SYSCTL_RESET_SPI2);
|
||||
sysctl_clock_enable(SYSCTL_CLOCK_SPI2);
|
||||
sysctl_clock_set_threshold(SYSCTL_THRESHOLD_SPI2, 9);
|
||||
|
||||
uint32_t data_width = data_bit_length / 8;
|
||||
volatile spi_t *spi_handle = spi[2];
|
||||
spi_handle->ssienr = 0x00;
|
||||
spi_handle->ctrlr0 = (0x0 << g_instance.work_mode) | (0x1 << g_instance.slv_oe) | ((data_bit_length - 1) << g_instance.dfs);
|
||||
spi_handle->dmatdlr = 0x04;
|
||||
spi_handle->dmardlr = 0x03;
|
||||
spi_handle->dmacr = 0x00;
|
||||
spi_handle->txftlr = 0x00;
|
||||
spi_handle->rxftlr = 0x08 / data_width - 1;
|
||||
spi_handle->imr = 0x10;
|
||||
spi_handle->ssienr = 0x01;
|
||||
|
||||
gpiohs_set_drive_mode(g_instance.ready_pin, GPIO_DM_OUTPUT);
|
||||
gpiohs_set_pin(g_instance.ready_pin, GPIO_PV_HIGH);
|
||||
|
||||
gpiohs_set_drive_mode(g_instance.int_pin, GPIO_DM_INPUT_PULL_UP);
|
||||
gpiohs_set_pin_edge(g_instance.int_pin, GPIO_PE_RISING);
|
||||
gpiohs_set_irq(g_instance.int_pin, 3, spi_slave_cs_irq);
|
||||
|
||||
plic_set_priority(IRQN_SPI_SLAVE_INTERRUPT, 4);
|
||||
plic_irq_enable(IRQN_SPI_SLAVE_INTERRUPT);
|
||||
plic_irq_register(IRQN_SPI_SLAVE_INTERRUPT, spi_slave_irq, NULL);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue