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Merge pull request #4 from kendryte/v0.3.0rc 

V0.3.0rc
This commit is contained in:
latyas 2018-10-10 20:31:07 +08:00 committed by GitHub
parent 8bb1ccd7da b32e6046e5
commit 9430d192e5
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
47 changed files with 917 additions and 3196 deletions
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1
cmake/compile-flags.cmake
View File

@ -18,6 +18,7 @@ add_compile_flags(BOTH
-ffunction-sections
-fdata-sections
-fstrict-volatile-bitfields
-fno-zero-initialized-in-bss
-Os
-ggdb
)

29
lib/bsp/config/fpioa_cfg.c
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@ -1,29 +0,0 @@
/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "fpioa_cfg.h"
const fpioa_cfg_t g_fpioa_cfg =
{
.version = 1,
.io_count = FPIOA_NUM_IO,
.io_functions =
{
[0] = FUNC_JTAG_TCLK,
}
};

42
lib/bsp/config/fpioa_cfg.h
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@ -1,42 +0,0 @@
/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _FPIOA_CFG_H
#define _FPIOA_CFG_H
#include <fpioa.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct _fpioa_cfg
{
uint32_t version;
uint32_t io_count;
fpioa_function_t io_functions[FPIOA_NUM_IO];
} fpioa_cfg_t;
extern const fpioa_cfg_t g_fpioa_cfg;
int fpioa_get_io_by_func(fpioa_function_t function);
#ifdef __cplusplus
}
#endif
#endif

51
lib/bsp/entry_user.c
View File

@ -25,17 +25,15 @@
#include "syslog.h"
#include "uarths.h"
#define PLL0_OUTPUT_FREQ 320000000UL
#define PLL1_OUTPUT_FREQ 160000000UL
#define PLL2_OUTPUT_FREQ 45158400UL
extern volatile uint64_t g_wake_up[2];
core_instance_t core1_instance;
volatile char * const ram = (volatile char*)RAM_BASE_ADDR;
extern char _heap_start[];
extern char _heap_end[];
extern volatile uint64_t g_wake_up[2];
void thread_entry(int core_id)
{
while (!atomic_read(&g_wake_up[core_id]));
@ -47,6 +45,16 @@ void core_enable(int core_id)
atomic_set(&g_wake_up[core_id], 1);
}
int register_core1(core_function func, void *ctx)
{
if(func == NULL)
return -1;
core1_instance.callback = func;
core1_instance.ctx = ctx;
core_enable(1);
return 0;
}
int __attribute__((weak)) os_entry(int core_id, int number_of_cores, int (*user_main)(int, char**))
{
/* Call main if there is no OS */
@ -63,38 +71,33 @@ void _init_bsp(int core_id, int number_of_cores)
if (core_id == 0)
{
/* Copy lma data to memory */
init_lma();
/* Initialize bss data to 0 */
init_bss();
/* Init FPIOA */
fpioa_init();
/* PLL init */
sysctl_set_pll_frequency(PLL0_OUTPUT_FREQ, PLL1_OUTPUT_FREQ, PLL2_OUTPUT_FREQ);
/* Init UART */
uarths_init();
/* Dmac init */
dmac_init();
/* Plic init */
plic_init();
/* Init FPIOA */
fpioa_init();
/* Register finalization function */
atexit(__libc_fini_array);
/* Init libc array for C++ */
__libc_init_array();
}
int ret = 0;
if (core_id == 0)
{
core1_instance.callback = NULL;
core1_instance.ctx = NULL;
ret = os_entry(core_id, number_of_cores, main);
}
else
{
thread_entry(core_id);
if(core1_instance.callback == NULL)
asm volatile ("wfi");
else
ret = core1_instance.callback(core1_instance.ctx);
}
if (core_id == 0)
{
/* Enable Core 1 to run main */
core_enable(1);
}
int ret = os_entry(core_id, number_of_cores, main);
exit(ret);
}

7
lib/bsp/include/bsp.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef _KENDRYTE_BSP_H
#define _KENDRYTE_BSP_H
#include "atomic.h"
#include "entry.h"
#include "sleep.h"
#include "encoding.h"
#endif

10
lib/bsp/include/entry.h
View File

@ -23,6 +23,16 @@
extern "C" {
#endif
typedef int (*core_function)(void *ctx);
typedef struct _core_instance_t
{
core_function callback;
void *ctx;
} core_instance_t;
int register_core1(core_function func, void *ctx);
static inline void init_lma(void)
{
extern unsigned int _data_lma;

14
lib/bsp/syscalls.c
View File

@ -106,14 +106,6 @@ void __attribute__((noreturn)) sys_exit(int code)
unsigned long core_id = current_coreid();
/* First print some diagnostic information. */
LOGW(TAG, "sys_exit called by core %ld with 0x%lx\n", core_id, (uint64_t)code);
/* Write exit register to pause netlist simulation */
volatile uint32_t *reg = (volatile uint32_t *)0x50440080UL;
/* Write stop bit and write back */
*reg = (1UL << 31);
/* Send 0 to uart */
uarths_putchar(0);
while (1)
continue;
}
@ -125,8 +117,6 @@ static int sys_nosys(long a0, long a1, long a2, long a3, long a4, long a5, unsig
UNUSED(a5);
LOGE(TAG, "Unsupported syscall %ld: a0=%lx, a1=%lx, a2=%lx!\n", n, a0, a1, a2);
/* Send 0 to uart */
uarths_putchar(0);
while (1)
continue;
return -ENOSYS;
@ -198,7 +188,7 @@ static ssize_t sys_write(int file, const void *ptr, size_t len)
/**
* Write to a file.
*
* ssize_t write(int file, const void* ptr, size_t len)
* ssize_t write(int file, const void *ptr, size_t len)
*
* IN : regs[10] = file, regs[11] = ptr, regs[12] = len
* OUT: regs[10] = len
@ -286,7 +276,7 @@ static int sys_gettimeofday(struct timeval *tp, void *tzp)
/**
* Get the current time. Only relatively correct.
*
* int gettimeofday(struct timeval* tp, void* tzp)
* int gettimeofday(struct timeval *tp, void *tzp)
*
* IN : regs[10] = tp
* OUT: regs[10] = Upon successful completion, 0 shall be

308
lib/drivers/aes.c
View File

@ -12,18 +12,20 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <sysctl.h>
#include <aes.h>
#include <stdlib.h>
#include "sysctl.h"
#include "aes.h"
#include "utils.h"
volatile aes_t* const aes = (volatile aes_t*)AES_BASE_ADDR;
volatile aes_t *const aes = (volatile aes_t *)AES_BASE_ADDR;
void aes_clk_init()
static void aes_clk_init()
{
sysctl_clock_enable(SYSCTL_CLOCK_AES);
sysctl_reset(SYSCTL_RESET_AES);
}
static void aes_write_add(uint32_t aad_data)
static void aes_write_aad(uint32_t aad_data)
{
aes->aes_aad_data = aad_data;
}
@ -33,7 +35,7 @@ static void aes_write_text(uint32_t text_data)
aes->aes_text_data = text_data;
}
static void gcm_write_tag(uint32_t* tag)
static void gcm_write_tag(uint32_t *tag)
{
aes->gcm_in_tag[0] = tag[3];
aes->gcm_in_tag[1] = tag[2];
@ -66,7 +68,31 @@ static uint32_t gcm_get_tag_chk(void)
return aes->tag_chk;
}
static void gcm_get_tag(uint8_t *gcm_tag)
static void gcm_clear_chk_tag(void)
{
aes->tag_clear = 0;
}
static uint32_t gcm_check_tag(uint32_t *gcm_tag)
{
while (!gcm_get_tag_in_flag())
;
gcm_write_tag(gcm_tag);
while (!gcm_get_tag_chk())
;
if (gcm_get_tag_chk() == 0x2)
{
gcm_clear_chk_tag();
return 1;
}
else
{
gcm_clear_chk_tag();
return 0;
}
}
void gcm_get_tag(uint8_t *gcm_tag)
{
uint32_t uint32_tag;
uint8_t i = 0;
@ -94,35 +120,13 @@ static void gcm_get_tag(uint8_t *gcm_tag)
gcm_tag[i++] = (uint8_t)((uint32_tag >> 16) & 0xff);
gcm_tag[i++] = (uint8_t)((uint32_tag >> 8) & 0xff);
gcm_tag[i++] = (uint8_t)((uint32_tag)&0xff);
gcm_check_tag((uint32_t *)gcm_tag);
}
static void gcm_clear_chk_tag(void)
{
aes->tag_clear = 0;
}
static uint32_t gcm_check_tag(uint32_t *gcm_tag)
{
while (!gcm_get_tag_in_flag())
;
gcm_write_tag(gcm_tag);
while (!gcm_get_tag_chk())
;
if (gcm_get_tag_chk() == 0x2)
{
gcm_clear_chk_tag();
return 1;
}
else
{
gcm_clear_chk_tag();
return 0;
}
}
static void aes_init(uint8_t *input_key, size_t input_key_len, uint8_t *iv,
size_t iv_len, uint8_t *gcm_add, aes_cipher_mode_t cipher_mode,
aes_encrypt_sel_t encrypt_sel, size_t gcm_add_len, size_t input_data_len)
void aes_init(uint8_t *input_key, size_t input_key_len, uint8_t *iv,size_t iv_len, uint8_t *gcm_aad,
aes_cipher_mode_t cipher_mode, aes_encrypt_sel_t encrypt_sel, size_t gcm_aad_len, size_t input_data_len)
{
size_t remainder, uint32_num, uint8_num, i;
uint32_t uint32_data;
@ -136,102 +140,57 @@ static void aes_init(uint8_t *input_key, size_t input_key_len, uint8_t *iv,
for (i = 0; i < uint32_num; i++)
{
if (i < 4)
aes->aes_key[i] = *((uint32_t*)(&input_key[input_key_len - (4 * i) - 4]));
aes->aes_key[i] = *((uint32_t *)(&input_key[input_key_len - (4 * i) - 4]));
else
aes->aes_key_ext[i - 4] = *((uint32_t*)(&input_key[input_key_len - (4 * i) - 4]));
}
remainder = input_key_len % 4;
if (remainder)
{
switch (remainder)
{
case 1:
uint8_data[0] = input_key[0];
break;
case 2:
uint8_data[0] = input_key[0];
uint8_data[1] = input_key[1];
break;
case 3:
uint8_data[0] = input_key[0];
uint8_data[1] = input_key[1];
uint8_data[2] = input_key[2];
break;
default:
break;
}
if (uint32_num < 4)
aes->aes_key[uint32_num] = *((uint32_t*)(&uint8_data[0]));
else
aes->aes_key_ext[uint32_num - 4] = *((uint32_t*)(&uint8_data[0]));
aes->aes_key_ext[i - 4] = *((uint32_t *)(&input_key[input_key_len - (4 * i) - 4]));
}
uint32_num = iv_len / 4;
for (i = 0; i < uint32_num; i++)
aes->aes_iv[i] = *((uint32_t*)(&iv[iv_len - (4 * i) - 4]));
remainder = iv_len % 4;
if (remainder)
{
switch (remainder)
{
case 1:
uint8_data[0] = iv[0];
break;
case 2:
uint8_data[0] = iv[0];
uint8_data[1] = iv[1];
break;
case 3:
uint8_data[0] = iv[0];
uint8_data[1] = iv[1];
uint8_data[2] = iv[2];
break;
default:
break;
}
aes->aes_iv[uint32_num] = *((uint32_t*)(&uint8_data[0]));
}
aes->mode_ctl.kmode = input_key_len / 8 - 2; /* 00:AES_128 01:AES_192 10:AES_256 11:RESERVED */
aes->aes_iv[i] = *((uint32_t *)(&iv[iv_len - (4 * i) - 4]));
aes->mode_ctl.kmode = input_key_len / 8 - 2; /* b'00:AES_128 b'01:AES_192 b'10:AES_256 b'11:RESERVED */
aes->mode_ctl.cipher_mode = cipher_mode;
aes->encrypt_sel = encrypt_sel;
aes->gb_aad_end_adr = gcm_add_len - 1;
aes->gb_pc_end_adr = padding_len - 1;
aes->gb_aad_num = gcm_aad_len - 1;
aes->gb_pc_num = padding_len - 1;
aes->gb_aes_en |= 1;
if (cipher_mode == AES_GCM)
{
uint32_num = gcm_add_len / 4;
uint32_num = gcm_aad_len / 4;
for (i = 0; i < uint32_num; i++)
{
uint32_data = *((uint32_t*)(&gcm_add[i * 4]));
uint32_data = *((uint32_t *)(&gcm_aad[i * 4]));
while (!aes_get_data_in_flag())
;
aes_write_add(uint32_data);
aes_write_aad(uint32_data);
}
uint8_num = 4 * uint32_num;
remainder = gcm_add_len % 4;
remainder = gcm_aad_len % 4;
if (remainder)
{
switch (remainder)
{
case 1:
uint8_data[0] = gcm_add[uint8_num];
uint8_data[0] = gcm_aad[uint8_num];
break;
case 2:
uint8_data[0] = gcm_add[uint8_num];
uint8_data[1] = gcm_add[uint8_num + 1];
uint8_data[0] = gcm_aad[uint8_num];
uint8_data[1] = gcm_aad[uint8_num + 1];
break;
case 3:
uint8_data[0] = gcm_add[uint8_num];
uint8_data[1] = gcm_add[uint8_num + 1];
uint8_data[2] = gcm_add[uint8_num + 2];
uint8_data[0] = gcm_aad[uint8_num];
uint8_data[1] = gcm_aad[uint8_num + 1];
uint8_data[2] = gcm_aad[uint8_num + 2];
break;
default:
break;
}
uint32_data = *((uint32_t*)(&uint8_data[0]));
uint32_data = *((uint32_t *)(&uint8_data[0]));
while (!aes_get_data_in_flag())
;
aes_write_add(uint32_data);
aes_write_aad(uint32_data);
}
}
}
@ -246,7 +205,7 @@ static void process_less_80_bytes(uint8_t *input_data, uint8_t *output_data, siz
uint32_num = input_data_len / 4;
for (i = 0; i < uint32_num; i++)
{
uint32_data = *((uint32_t*)(&input_data[i * 4]));
uint32_data = *((uint32_t *)(&input_data[i * 4]));
while (!aes_get_data_in_flag())
;
aes_write_text(uint32_data);
@ -272,7 +231,7 @@ static void process_less_80_bytes(uint8_t *input_data, uint8_t *output_data, siz
default:
break;
}
uint32_data = *((uint32_t*)(&uint8_data[0]));
uint32_data = *((uint32_t *)(&uint8_data[0]));
while (!aes_get_data_in_flag())
;
aes_write_text(uint32_data);
@ -292,13 +251,13 @@ static void process_less_80_bytes(uint8_t *input_data, uint8_t *output_data, siz
{
while (!aes_get_data_out_flag())
;
*((uint32_t*)(&output_data[i * 4])) = aes_read_out_data();
*((uint32_t *)(&output_data[i * 4])) = aes_read_out_data();
}
if ((cipher_mode == AES_GCM) && (remainder))
{
while (!aes_get_data_out_flag())
;
*((uint32_t*)(&uint8_data[0])) = aes_read_out_data();
*((uint32_t *)(&uint8_data[0])) = aes_read_out_data();
switch (remainder)
{
case 1:
@ -319,7 +278,7 @@ static void process_less_80_bytes(uint8_t *input_data, uint8_t *output_data, siz
}
}
static void aes_process(uint8_t *input_data, uint8_t *output_data, size_t input_data_len, aes_cipher_mode_t cipher_mode)
void aes_process(uint8_t *input_data, uint8_t *output_data, size_t input_data_len, aes_cipher_mode_t cipher_mode)
{
size_t temp_len = 0;
uint32_t i = 0;
@ -334,32 +293,129 @@ static void aes_process(uint8_t *input_data, uint8_t *output_data, size_t input_
process_less_80_bytes(&input_data[i * 80], &output_data[i * 80], temp_len, cipher_mode);
}
void aes_hard_decrypt(aes_param_t *param)
void aes_ecb128_hard_decrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data)
{
size_t padding_len = param->input_data_len;
if (param->cipher_mode == AES_CBC || param->cipher_mode == AES_ECB)
{
padding_len = ((padding_len + 15) / 16) * 16;
}
aes_init(param->input_key, param->input_key_len, param->iv, param->iv_len, param->gcm_add,
param->cipher_mode, AES_HARD_DECRYPTION, param->gcm_add_len, param->input_data_len);
aes_process(param->input_data, param->output_data, padding_len, param->cipher_mode);
if (param->cipher_mode == AES_GCM)
{
gcm_get_tag(param->gcm_tag);
gcm_check_tag((uint32_t *)param->gcm_tag);
}
size_t padding_len = ((input_len + 15) / 16) * 16;
aes_init(input_key, AES_128, NULL, 0L, NULL, AES_ECB, AES_HARD_DECRYPTION, 0L, input_len);
aes_process(input_data, output_data, padding_len, AES_ECB);
}
void aes_hard_encrypt(aes_param_t *param)
void aes_ecb128_hard_encrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data)
{
aes_init(param->input_key, param->input_key_len, param->iv, param->iv_len, param->gcm_add,
param->cipher_mode, AES_HARD_ENCRYPTION, param->gcm_add_len, param->input_data_len);
aes_process(param->input_data, param->output_data, param->input_data_len, param->cipher_mode);
if (param->cipher_mode == AES_GCM)
{
gcm_get_tag(param->gcm_tag);
gcm_check_tag((uint32_t *)param->gcm_tag);
}
aes_init(input_key, AES_128, NULL, 0L, NULL, AES_ECB, AES_HARD_ENCRYPTION, 0L, input_len);
aes_process(input_data, output_data, input_len, AES_ECB);
}
void aes_ecb192_hard_decrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data)
{
size_t padding_len = ((input_len + 15) / 16) * 16;
aes_init(input_key, AES_192, NULL, 0L, NULL, AES_ECB, AES_HARD_DECRYPTION, 0L, input_len);
aes_process(input_data, output_data, padding_len, AES_ECB);
}
void aes_ecb192_hard_encrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data)
{
aes_init(input_key, AES_192, NULL, 0L, NULL, AES_ECB, AES_HARD_ENCRYPTION, 0L, input_len);
aes_process(input_data, output_data, input_len, AES_ECB);
}
void aes_ecb256_hard_decrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data)
{
size_t padding_len = ((input_len + 15) / 16) * 16;
aes_init(input_key, AES_256, NULL, 0L, NULL, AES_ECB, AES_HARD_DECRYPTION, 0L, input_len);
aes_process(input_data, output_data, padding_len, AES_ECB);
}
void aes_ecb256_hard_encrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data)
{
aes_init(input_key, AES_256, NULL, 0L, NULL, AES_ECB, AES_HARD_ENCRYPTION, 0L, input_len);
aes_process(input_data, output_data, input_len, AES_ECB);
}
void aes_cbc128_hard_decrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data)
{
size_t padding_len = ((input_len + 15) / 16) * 16;
aes_init(context->input_key, AES_128, context->iv, IV_LEN_128, NULL, AES_CBC, AES_HARD_DECRYPTION, 0L, input_len);
aes_process(input_data, output_data, padding_len, AES_CBC);
}
void aes_cbc128_hard_encrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data)
{
aes_init(context->input_key, AES_128, context->iv, IV_LEN_128, NULL, AES_CBC, AES_HARD_ENCRYPTION, 0L, input_len);
aes_process(input_data, output_data, input_len, AES_CBC);
}
void aes_cbc192_hard_decrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data)
{
size_t padding_len = ((input_len + 15) / 16) * 16;
aes_init(context->input_key, AES_192, context->iv, IV_LEN_128, NULL, AES_CBC, AES_HARD_DECRYPTION, 0L, input_len);
aes_process(input_data, output_data, padding_len, AES_CBC);
}
void aes_cbc192_hard_encrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data)
{
aes_init(context->input_key, AES_192, context->iv, IV_LEN_128, NULL, AES_CBC, AES_HARD_ENCRYPTION, 0L, input_len);
aes_process(input_data, output_data, input_len, AES_CBC);
}
void aes_cbc256_hard_decrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data)
{
size_t padding_len = ((input_len + 15) / 16) * 16;
aes_init(context->input_key, AES_256, context->iv, IV_LEN_128, NULL, AES_CBC, AES_HARD_DECRYPTION, 0L, input_len);
aes_process(input_data, output_data, padding_len, AES_CBC);
}
void aes_cbc256_hard_encrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data)
{
aes_init(context->input_key, AES_256, context->iv, IV_LEN_128, NULL, AES_CBC, AES_HARD_ENCRYPTION, 0L, input_len);
aes_process(input_data, output_data, input_len, AES_CBC);
}
void aes_gcm128_hard_decrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag)
{
aes_init(context->input_key, AES_128, context->iv, IV_LEN_96, context->gcm_aad,
AES_GCM, AES_HARD_DECRYPTION, context->gcm_aad_len, input_len);
aes_process(input_data, output_data, input_len, AES_GCM);
gcm_get_tag(gcm_tag);
}
void aes_gcm128_hard_encrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag)
{
aes_init(context->input_key, AES_128, context->iv, IV_LEN_96, context->gcm_aad,
AES_GCM, AES_HARD_ENCRYPTION, context->gcm_aad_len, input_len);
aes_process(input_data, output_data, input_len, AES_GCM);
gcm_get_tag(gcm_tag);
}
void aes_gcm192_hard_decrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag)
{
aes_init(context->input_key, AES_192, context->iv, IV_LEN_96, context->gcm_aad,
AES_GCM, AES_HARD_DECRYPTION, context->gcm_aad_len, input_len);
aes_process(input_data, output_data, input_len, AES_GCM);
gcm_get_tag(gcm_tag);
}
void aes_gcm192_hard_encrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag)
{
aes_init(context->input_key, AES_192, context->iv, IV_LEN_96, context->gcm_aad,
AES_GCM, AES_HARD_ENCRYPTION, context->gcm_aad_len, input_len);
aes_process(input_data, output_data, input_len, AES_GCM);
gcm_get_tag(gcm_tag);
}
void aes_gcm256_hard_decrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag)
{
aes_init(context->input_key, AES_256, context->iv, IV_LEN_96, context->gcm_aad,
AES_GCM, AES_HARD_DECRYPTION, context->gcm_aad_len, input_len);
aes_process(input_data, output_data, input_len, AES_GCM);
gcm_get_tag(gcm_tag);
}
void aes_gcm256_hard_encrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag)
{
aes_init(context->input_key, AES_256, context->iv, IV_LEN_96, context->gcm_aad,
AES_GCM, AES_HARD_ENCRYPTION, context->gcm_aad_len, input_len);
aes_process(input_data, output_data, input_len, AES_GCM);
gcm_get_tag(gcm_tag);
}

6
lib/drivers/clint.c
View File

@ -60,7 +60,7 @@ int clint_timer_stop(void)
uint64_t clint_timer_get_freq(void)
{
/* The clock is divided by CLINT_CLOCK_DIV */
return sysctl_get_freq() / CLINT_CLOCK_DIV;
return sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / CLINT_CLOCK_DIV;
}
int clint_timer_start(uint64_t interval, int single_shot)
@ -130,7 +130,7 @@ int clint_timer_set_single_shot(int single_shot)
return 0;
}
int clint_timer_register(clint_timer_callback_t callback, void* ctx)
int clint_timer_register(clint_timer_callback_t callback, void *ctx)
{
/* Read core id */
unsigned long core_id = current_coreid();
@ -200,7 +200,7 @@ int clint_ipi_clear(size_t core_id)
return 0;
}
int clint_ipi_register(clint_ipi_callback_t callback, void* ctx)
int clint_ipi_register(clint_ipi_callback_t callback, void *ctx)
{
/* Read core id */
unsigned long core_id = current_coreid();

10
lib/drivers/common.c
View File

@ -16,28 +16,28 @@
#include "encoding.h"
#include "utils.h"
void set_bit(volatile uint32_t* bits, uint32_t mask, uint32_t value)
void set_bit(volatile uint32_t *bits, uint32_t mask, uint32_t value)
{
uint32_t org = (*bits) & ~mask;
*bits = org | (value & mask);
}
void set_bit_offset(volatile uint32_t* bits, uint32_t mask, size_t offset, uint32_t value)
void set_bit_offset(volatile uint32_t *bits, uint32_t mask, size_t offset, uint32_t value)
{
set_bit(bits, mask << offset, value << offset);
}
void set_gpio_bit(volatile uint32_t* bits, size_t offset, uint32_t value)
void set_gpio_bit(volatile uint32_t *bits, size_t offset, uint32_t value)
{
set_bit_offset(bits, 1, offset, value);
}
uint32_t get_bit(volatile uint32_t* bits, uint32_t mask, size_t offset)
uint32_t get_bit(volatile uint32_t *bits, uint32_t mask, size_t offset)
{
return ((*bits) & (mask << offset)) >> offset;
}
uint32_t get_gpio_bit(volatile uint32_t* bits, size_t offset)
uint32_t get_gpio_bit(volatile uint32_t *bits, size_t offset)
{
return get_bit(bits, 1, offset);
}

15
lib/drivers/dvp.c
View File

@ -103,20 +103,6 @@ uint8_t dvp_sccb_receive_data(uint8_t dev_addr, uint16_t reg_addr)
return (uint8_t) DVP_SCCB_RDATA_BYTE(dvp->sccb_cfg);
}
static void dvp_io_init(void)
{
/* Init DVP IO map and function settings */
fpioa_set_function(15, FUNC_CMOS_RST);
fpioa_set_function(17, FUNC_CMOS_PWDN);
fpioa_set_function(20, FUNC_CMOS_XCLK);
fpioa_set_function(18, FUNC_CMOS_VSYNC);
fpioa_set_function(19, FUNC_CMOS_HREF);
fpioa_set_function(21, FUNC_CMOS_PCLK);
fpioa_set_function(22, FUNC_SCCB_SCLK);
fpioa_set_function(23, FUNC_SCCB_SDA);
sysctl_spi0_dvp_data_set(1);
}
static void dvp_reset(void)
{
/* First power down */
@ -139,7 +125,6 @@ void dvp_init(uint8_t reg_len)
sysctl_reset(SYSCTL_RESET_DVP);
dvp->cmos_cfg &= (~DVP_CMOS_CLK_DIV_MASK);
dvp->cmos_cfg |= DVP_CMOS_CLK_DIV(0) | DVP_CMOS_CLK_ENABLE;
dvp_io_init();
dvp_sccb_clk_init();
dvp_reset();
}

16
lib/drivers/fft.c
View File

@ -13,17 +13,17 @@
* limitations under the License.
*/
#include <stddef.h>
#include <dmac.h>
#include <utils.h>
#include <sysctl.h>
#include <fft.h>
#include "dmac.h"
#include "utils.h"
#include "sysctl.h"
#include "fft.h"
static volatile fft_t *const fft = (volatile fft_t *)FFT_BASE_ADDR;
static void fft_init(uint8_t point, uint8_t mode, uint16_t shift, uint8_t is_dma, uint8_t input_mode, uint8_t data_mode)
{
fft->fft_ctrl.fft_point = point; /* 0:512, 1:256, 2:128, 3:64 */
fft->fft_ctrl.fft_mode = mode; /* 1: fft, 0: ifft */
fft->fft_ctrl.fft_point = point;
fft->fft_ctrl.fft_mode = mode;
fft->fft_ctrl.fft_shift = shift;
fft->fft_ctrl.dma_send = is_dma;
fft->fft_ctrl.fft_enable = 1;
@ -59,9 +59,9 @@ void fft_complex_uint16_dma(dmac_channel_number_t dma_send_channel_num, dmac_cha
fft_init(point, direction, shift, 1, 0, 0);
sysctl_dma_select(dma_receive_channel_num, SYSCTL_DMA_SELECT_FFT_RX_REQ);
sysctl_dma_select(dma_send_channel_num, SYSCTL_DMA_SELECT_FFT_TX_REQ);
dmac_set_single_mode(dma_receive_channel_num, (void*)(&fft->fft_output_fifo), output, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
dmac_set_single_mode(dma_receive_channel_num, (void *)(&fft->fft_output_fifo), output, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
DMAC_MSIZE_4, DMAC_TRANS_WIDTH_64, point_num>>1);
dmac_set_single_mode(dma_send_channel_num, input, (void*)(&fft->fft_input_fifo), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
dmac_set_single_mode(dma_send_channel_num, input, (void *)(&fft->fft_input_fifo), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
DMAC_MSIZE_4, DMAC_TRANS_WIDTH_64, point_num>>1);
dmac_wait_done(dma_receive_channel_num);
}

2
lib/drivers/fpioa.c
View File

@ -5385,7 +5385,7 @@ int fpioa_set_tie_value(fpioa_function_t function, int value)
return 0;
}
int fpioa_get_io_by_func(fpioa_function_t function)
int fpioa_get_io_by_function(fpioa_function_t function)
{
int index = 0;
for (index = 0; index < FPIOA_NUM_IO; index++)

6
lib/drivers/gpio.c
View File

@ -28,7 +28,7 @@ int gpio_init(void)
void gpio_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode)
{
configASSERT(pin < GPIO_MAX_PINNO);
int io_number = fpioa_get_io_by_func(FUNC_GPIO0 + pin);
int io_number = fpioa_get_io_by_function(FUNC_GPIO0 + pin);
configASSERT(io_number > 0);
fpioa_pull_t pull;
@ -64,7 +64,7 @@ gpio_pin_value_t gpio_get_pin(uint8_t pin)
{
configASSERT(pin < GPIO_MAX_PINNO);
uint32_t dir = get_gpio_bit(gpio->direction.u32, pin);
volatile uint32_t* reg = dir ? gpio->data_output.u32 : gpio->data_input.u32;
volatile uint32_t *reg = dir ? gpio->data_output.u32 : gpio->data_input.u32;
return get_gpio_bit(reg, pin);
}
@ -72,7 +72,7 @@ void gpio_set_pin(uint8_t pin, gpio_pin_value_t value)
{
configASSERT(pin < GPIO_MAX_PINNO);
uint32_t dir = get_gpio_bit(gpio->direction.u32, pin);
volatile uint32_t* reg = dir ? gpio->data_output.u32 : gpio->data_input.u32;
volatile uint32_t *reg = dir ? gpio->data_output.u32 : gpio->data_input.u32;
configASSERT(dir == 1);
set_gpio_bit(reg, pin, value);
}

10
lib/drivers/gpiohs.c
View File

@ -32,7 +32,7 @@ gpiohs_pin_context pin_context[32];
void gpiohs_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode)
{
configASSERT(pin < GPIOHS_MAX_PINNO);
int io_number = fpioa_get_io_by_func(FUNC_GPIOHS0 + pin);
int io_number = fpioa_get_io_by_function(FUNC_GPIOHS0 + pin);
configASSERT(io_number > 0);
fpioa_pull_t pull;
@ -61,8 +61,8 @@ void gpiohs_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode)
}
fpioa_set_io_pull(io_number, pull);
volatile uint32_t* reg = dir ? gpiohs->output_en.u32 : gpiohs->input_en.u32;
volatile uint32_t* reg_d = !dir ? gpiohs->output_en.u32 : gpiohs->input_en.u32;
volatile uint32_t *reg = dir ? gpiohs->output_en.u32 : gpiohs->input_en.u32;
volatile uint32_t *reg_d = !dir ? gpiohs->output_en.u32 : gpiohs->input_en.u32;
set_gpio_bit(reg_d, pin, 0);
set_gpio_bit(reg, pin, 1);
}
@ -108,9 +108,9 @@ void gpiohs_set_pin_edge(uint8_t pin, gpio_pin_edge_t edge)
pin_context[pin].edge = edge;
}
int gpiohs_pin_onchange_isr(void* userdata)
int gpiohs_pin_onchange_isr(void *userdata)
{
gpiohs_pin_context* ctx = (gpiohs_pin_context*)userdata;
gpiohs_pin_context *ctx = (gpiohs_pin_context *)userdata;
size_t pin = ctx->pin;
uint32_t rise, fall;
switch (ctx->edge)

34
lib/drivers/i2c.c
View File

@ -36,29 +36,27 @@ static void i2c_clk_init(i2c_device_number_t i2c_num)
}
void i2c_init(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width,
i2c_bus_speed_mode_t bus_speed_mode)
uint32_t i2c_clk)
{
configASSERT(i2c_num < I2C_MAX_NUM);
configASSERT(address_width == 7 || address_width == 10);
volatile i2c_t *i2c_adapter = i2c[i2c_num];
int speed_mode = 1;
i2c_clk_init(i2c_num);
switch (bus_speed_mode) {
case I2C_BS_STANDARD:
speed_mode = 1;
break;
default:
break;
}
uint32_t v_i2c_freq = sysctl_clock_get_freq(SYSCTL_CLOCK_I2C0 + i2c_num);
uint16_t v_period_clk_cnt = v_i2c_freq / i2c_clk / 2;
if(v_period_clk_cnt == 0)
v_period_clk_cnt = 1;
i2c_adapter->enable = 0;
i2c_adapter->con = I2C_CON_MASTER_MODE | I2C_CON_SLAVE_DISABLE | I2C_CON_RESTART_EN |
(address_width == 10 ? I2C_CON_10BITADDR_SLAVE : 0) | I2C_CON_SPEED(speed_mode);
i2c_adapter->ss_scl_hcnt = I2C_SS_SCL_HCNT_COUNT(37);
i2c_adapter->ss_scl_lcnt = I2C_SS_SCL_LCNT_COUNT(40);
(address_width == 10 ? I2C_CON_10BITADDR_SLAVE : 0) | I2C_CON_SPEED(1);
i2c_adapter->ss_scl_hcnt = I2C_SS_SCL_HCNT_COUNT(v_period_clk_cnt);
i2c_adapter->ss_scl_lcnt = I2C_SS_SCL_LCNT_COUNT(v_period_clk_cnt);
i2c_adapter->tar = I2C_TAR_ADDRESS(slave_address);
i2c_adapter->intr_mask = 0;
i2c_adapter->dma_cr = 0x3;
@ -95,7 +93,7 @@ void i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_
configASSERT(i2c_num < I2C_MAX_NUM);
volatile i2c_t* i2c_adapter = i2c[i2c_num];
uint32_t* buf = malloc(send_buf_len * sizeof(uint32_t));
uint32_t *buf = malloc(send_buf_len * sizeof(uint32_t));
int i;
for (i = 0; i < send_buf_len; i++)
{
@ -103,11 +101,11 @@ void i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_
}
sysctl_dma_select((sysctl_dma_channel_t)dma_channel_num, SYSCTL_DMA_SELECT_I2C0_TX_REQ + i2c_num * 2);
dmac_set_single_mode(dma_channel_num, buf, (void*)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
dmac_set_single_mode(dma_channel_num, buf, (void *)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, send_buf_len);
dmac_wait_done(dma_channel_num);
free((void*)buf);
free((void *)buf);
while (i2c_adapter->status & I2C_STATUS_ACTIVITY)
{
@ -162,7 +160,7 @@ void i2c_recv_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_
volatile i2c_t* i2c_adapter = i2c[i2c_num];
uint32_t* write_cmd = malloc(sizeof(uint32_t) * (send_buf_len + receive_buf_len));
uint32_t *write_cmd = malloc(sizeof(uint32_t) * (send_buf_len + receive_buf_len));
size_t i;
for(i = 0; i < send_buf_len; i++)
write_cmd[i] = *send_buf++;
@ -172,10 +170,10 @@ void i2c_recv_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_
sysctl_dma_select((sysctl_dma_channel_t)dma_send_channel_num, SYSCTL_DMA_SELECT_I2C0_TX_REQ + i2c_num * 2);
sysctl_dma_select((sysctl_dma_channel_t)dma_receive_channel_num, SYSCTL_DMA_SELECT_I2C0_RX_REQ + i2c_num * 2);
dmac_set_single_mode(dma_receive_channel_num, (void*)(&i2c_adapter->data_cmd), write_cmd, DMAC_ADDR_NOCHANGE,
dmac_set_single_mode(dma_receive_channel_num, (void *)(&i2c_adapter->data_cmd), write_cmd, DMAC_ADDR_NOCHANGE,
DMAC_ADDR_INCREMENT,DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, receive_buf_len);
dmac_set_single_mode(dma_send_channel_num, write_cmd, (void*)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT,
dmac_set_single_mode(dma_send_channel_num, write_cmd, (void *)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT,
DMAC_ADDR_NOCHANGE,DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, receive_buf_len + send_buf_len);
dmac_wait_done(dma_send_channel_num);

364
lib/drivers/include/aes.h
View File

@ -36,6 +36,12 @@ typedef enum _aes_kmode
AES_256 = 32,
} aes_kmode_t;
typedef enum _aes_iv_len
{
IV_LEN_96 = 12,
IV_LEN_128 = 16,
} aes_iv_len_t;
typedef enum _aes_encrypt_sel
{
AES_HARD_ENCRYPTION = 0,
@ -44,13 +50,17 @@ typedef enum _aes_encrypt_sel
typedef struct _aes_mode_ctl
{
/* set the first bit and second bit 00:ecb; 01:cbc,10：aes_gcm */
/* [2:0]:000:ecb; 001:cbc,010:gcm */
uint32_t cipher_mode : 3;
/* [4:3]:00:128; 01:192; 10:256;11:reserved*/
/* [4:3]:00:aes-128; 01:aes-192; 10:aes-256;11:reserved*/
uint32_t kmode : 2;
uint32_t endian : 6;
uint32_t stream_mode : 3;
uint32_t reserved : 18;
/* [6:5]:input key order 1：little endian; 0: big endian */
uint32_t key_order : 2;
/* [8:7]:input data order 1：little endian; 0: big endian */
uint32_t input_order : 2;
/* [10:9]:output data order 1：little endian; 0: big endian */
uint32_t output_order : 2;
uint32_t reserved : 21;
} __attribute__((packed, aligned(4))) aes_mode_ctl_t;
/**
@ -58,69 +68,341 @@ typedef struct _aes_mode_ctl
*/
typedef struct _aes
{
/* (0x00) customer key.1st~4th byte key */
uint32_t aes_key[4];
/* 0: encrption ; 1: dencrption */
/* (0x10) 0: encryption; 1: decryption */
uint32_t encrypt_sel;
/**
* [1:0], Set the first bit and second bit 00:ecb; 01:cbc;
* 10,11：aes_gcm
*/
/* (0x14) aes mode reg */
aes_mode_ctl_t mode_ctl;
/* (0x18) Initialisation Vector. GCM support 96bit. CBC support 128bit */
uint32_t aes_iv[4];
/* aes interrupt enable */
/* (0x28) input data endian;1:little endian; 0:big endian */
uint32_t aes_endian;
/* aes interrupt flag */
/* (0x2c) calculate status. 1:finish; 0:not finish */
uint32_t aes_finish;
/* gcm add data begin address */
/* (0x30) aes out data to dma 0:cpu 1:dma */
uint32_t dma_sel;
/* gcm add data end address */
uint32_t gb_aad_end_adr;
/* gcm plantext/ciphter text data begin address */
uint32_t gb_pc_ini_adr;
/* gcm plantext/ciphter text data end address */
uint32_t gb_pc_end_adr;
/* gcm plantext/ciphter text data */
/* (0x34) gcm Additional authenticated data number */
uint32_t gb_aad_num;
uint32_t reserved;
/* (0x3c) aes plantext/ciphter text input data number */
uint32_t gb_pc_num;
/* (0x40) aes plantext/ciphter text input data */
uint32_t aes_text_data;
/* AAD data */
/* (0x44) Additional authenticated data */
uint32_t aes_aad_data;
/**
* [1:0],00:check not finish; 01: check fail; 10: check success;11:
* reversed
* (0x48) [1:0],b'00:check not finish; b'01:check fail; b'10:check success;
* b'11:reversed
*/
uint32_t tag_chk;
/* data can input flag 1: data can input; 0 : data cannot input */
/* (0x4c) data can input flag. 1: data can input; 0 : data cannot input */
uint32_t data_in_flag;
/* gcm input tag for compare with the calculate tag */
/* (0x50) gcm input tag for compare with the calculate tag */
uint32_t gcm_in_tag[4];
/* gcm plantext/ciphter text data */
/* (0x60) aes plantext/ciphter text output data */
uint32_t aes_out_data;
/* (0x64) aes module enable */
uint32_t gb_aes_en;
/* data can output flag 1: data ready 0: data not ready */
/* (0x68) data can output flag 1: data ready 0: data not ready */
uint32_t data_out_flag;
/* allow tag input when use GCM */
/* (0x6c) allow tag input when use gcm */
uint32_t tag_in_flag;
/* (0x70) clear tag_chk */
uint32_t tag_clear;
uint32_t gcm_out_tag[4];
/* (0x84) customer key for aes-192 aes-256.5th~8th byte key */
uint32_t aes_key_ext[4];
} __attribute__((packed, aligned(4))) aes_t;
typedef struct _aes_param
typedef struct _gcm_context
{
uint8_t *input_data;
size_t input_data_len;
/* The buffer holding the encryption or decryption key. */
uint8_t *input_key;
size_t input_key_len;
/* The initialization vector. must be 96 bit */
uint8_t *iv;
uint8_t iv_len;
uint8_t* gcm_add;
size_t gcm_add_len;
aes_cipher_mode_t cipher_mode;
uint8_t *output_data;
uint8_t *gcm_tag;
} aes_param_t;
/* The buffer holding the Additional authenticated data. or NULL */
uint8_t *gcm_aad;
/* The length of the Additional authenticated data. or 0L */
size_t gcm_aad_len;
} gcm_context_t;
void aes_hard_decrypt(aes_param_t *param);
void aes_hard_encrypt(aes_param_t *param);
typedef struct _cbc_context
{
/* The buffer holding the encryption or decryption key. */
uint8_t *input_key;
/* The initialization vector. must be 128 bit */
uint8_t *iv;
} cbc_context_t;
/**
* @brief AES-ECB-128 decryption
*
* @param[in] input_key The decryption key. must be 16bytes.
* @param[in] input_data The buffer holding the input data.
* @param[in] input_len The length of a data unit in bytes.
* This can be any length between 16 bytes and 2^31 bytes inclusive
* (between 1 and 2^27 block cipher blocks).
* @param[out] output_data The buffer holding the output data.
*/
void aes_ecb128_hard_decrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data);
/**
* @brief AES-ECB-128 encryption
*
* @param[in] input_key The encryption key. must be 16bytes.
* @param[in] input_data The buffer holding the input data.
* @param[in] input_len The length of a data unit in bytes.
* This can be any length between 16 bytes and 2^31 bytes inclusive
* (between 1 and 2^27 block cipher blocks).
* @param[out] output_data The buffer holding the output data.
*/
void aes_ecb128_hard_encrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data);
/**
* @brief AES-ECB-192 decryption
*
* @param[in] input_key The decryption key. must be 24bytes.
* @param[in] input_data The buffer holding the input data.
* @param[in] input_len The length of a data unit in bytes.
* This can be any length between 16 bytes and 2^31 bytes inclusive
* (between 1 and 2^27 block cipher blocks).
* @param[out] output_data The buffer holding the output data.
*/
void aes_ecb192_hard_decrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data);
/**
* @brief AES-ECB-192 encryption
*
* @param[in] input_key The encryption key. must be 24bytes.
* @param[in] input_data The buffer holding the input data.
* @param[in] input_len The length of a data unit in bytes.
* This can be any length between 16 bytes and 2^31 bytes inclusive
* (between 1 and 2^27 block cipher blocks).
* @param[out] output_data The buffer holding the output data.
*/
void aes_ecb192_hard_encrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data);
/**
* @brief AES-ECB-256 decryption
*
* @param[in] input_key The decryption key. must be 32bytes.
* @param[in] input_data The buffer holding the input data.
* @param[in] input_len The length of a data unit in bytes.
* This can be any length between 16 bytes and 2^31 bytes inclusive
* (between 1 and 2^27 block cipher blocks).
* @param[out] output_data The buffer holding the output data.
*/
void aes_ecb256_hard_decrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data);
/**
* @brief AES-ECB-256 encryption
*
* @param[in] input_key The encryption key. must be 32bytes.
* @param[in] input_data The buffer holding the input data.
* @param[in] input_len The length of a data unit in bytes.
* This can be any length between 16 bytes and 2^31 bytes inclusive
* (between 1 and 2^27 block cipher blocks).
* @param[out] output_data The buffer holding the output data.
*/
void aes_ecb256_hard_encrypt(uint8_t *input_key, uint8_t *input_data, size_t input_len, uint8_t *output_data);
/**
* @brief AES-CBC-128 decryption
*
* @param[in] context The cbc context to use for encryption or decryption.
* @param[in] input_key The decryption key. must be 16bytes.
* @param[in] input_data The buffer holding the input data.
* @param[in] input_len The length of a data unit in bytes.
* This can be any length between 16 bytes and 2^31 bytes inclusive
* (between 1 and 2^27 block cipher blocks).
* @param[out] output_data The buffer holding the output data.
*/
void aes_cbc128_hard_decrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data);
/**
* @brief AES-CBC-128 encryption
*
* @param[in] context The cbc context to use for encryption or decryption.
* @param[in] input_key The encryption key. must be 16bytes.
* @param[in] input_data The buffer holding the input data.
* @param[in] input_len The length of a data unit in bytes.
* This can be any length between 16 bytes and 2^31 bytes inclusive
* (between 1 and 2^27 block cipher blocks).
* @param[out] output_data The buffer holding the output data.
*/
void aes_cbc128_hard_encrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data);
/**
* @brief AES-CBC-192 decryption
*
* @param[in] context The cbc context to use for encryption or decryption.
* @param[in] input_key The decryption key. must be 24bytes.
* @param[in] input_data The buffer holding the input data.
* @param[in] input_len The length of a data unit in bytes.
* This can be any length between 16 bytes and 2^31 bytes inclusive
* (between 1 and 2^27 block cipher blocks).
* @param[out] output_data The buffer holding the output data.
*/
void aes_cbc192_hard_decrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data);
/**
* @brief AES-CBC-192 encryption
*
* @param[in] context The cbc context to use for encryption or decryption.
* @param[in] input_key The encryption key. must be 24bytes.
* @param[in] input_data The buffer holding the input data.
* @param[in] input_len The length of a data unit in bytes.
* This can be any length between 16 bytes and 2^31 bytes inclusive
* (between 1 and 2^27 block cipher blocks).
* @param[out] output_data The buffer holding the output data.
*/
void aes_cbc192_hard_encrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data);
/**
* @brief AES-CBC-256 decryption
*
* @param[in] context The cbc context to use for encryption or decryption.
* @param[in] input_key The decryption key. must be 32bytes.
* @param[in] input_data The buffer holding the input data.
* @param[in] input_len The length of a data unit in bytes.
* This can be any length between 16 bytes and 2^31 bytes inclusive
* (between 1 and 2^27 block cipher blocks).
* @param[out] output_data The buffer holding the output data.
*/
void aes_cbc256_hard_decrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data);
/**
* @brief AES-CBC-256 encryption
*
* @param[in] context The cbc context to use for encryption or decryption.
* @param[in] input_key The encryption key. must be 32bytes.
* @param[in] input_data The buffer holding the input data.
* @param[in] input_len The length of a data unit in bytes.
* This can be any length between 16 bytes and 2^31 bytes inclusive
* (between 1 and 2^27 block cipher blocks).
* @param[out] output_data The buffer holding the output data.
*/
void aes_cbc256_hard_encrypt(cbc_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data);
/**
* @brief AES-GCM-128 decryption
*
* @param[in] context The gcm context to use for encryption or decryption.
* @param[in] input_key The decryption key. must be 16bytes.
* @param[in] input_data The buffer holding the input data.
* @param[in] input_len The length of a data unit in bytes.
* This can be any length between 16 bytes and 2^31 bytes inclusive
* (between 1 and 2^27 block cipher blocks).
* @param[out] output_data The buffer holding the output data.
* @param[out] gcm_tag The buffer for holding the tag.The length of the tag must be 4 bytes.
*/
void aes_gcm128_hard_decrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag);
/**
* @brief AES-GCM-128 encryption
*
* @param[in] context The gcm context to use for encryption or decryption.
* @param[in] input_key The encryption key. must be 16bytes.
* @param[in] input_data The buffer holding the input data.
* @param[in] input_len The length of a data unit in bytes.
* This can be any length between 16 bytes and 2^31 bytes inclusive
* (between 1 and 2^27 block cipher blocks).
* @param[out] output_data The buffer holding the output data.
* @param[out] gcm_tag The buffer for holding the tag.The length of the tag must be 4 bytes.
*/
void aes_gcm128_hard_encrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag);
/**
* @brief AES-GCM-192 decryption
*
* @param[in] context The gcm context to use for encryption or decryption.
* @param[in] input_key The decryption key. must be 24bytes.
* @param[in] input_data The buffer holding the input data.
* @param[in] input_len The length of a data unit in bytes.
* This can be any length between 16 bytes and 2^31 bytes inclusive
* (between 1 and 2^27 block cipher blocks).
* @param[out] output_data The buffer holding the output data.
* @param[out] gcm_tag The buffer for holding the tag.The length of the tag must be 4 bytes.
*/
void aes_gcm192_hard_decrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag);
/**
* @brief AES-GCM-192 encryption
*
* @param[in] context The gcm context to use for encryption or decryption.
* @param[in] input_key The encryption key. must be 24bytes.
* @param[in] input_data The buffer holding the input data.
* @param[in] input_len The length of a data unit in bytes.
* This can be any length between 16 bytes and 2^31 bytes inclusive
* (between 1 and 2^27 block cipher blocks).
* @param[out] output_data The buffer holding the output data.
* @param[out] gcm_tag The buffer for holding the tag.The length of the tag must be 4 bytes.
*/
void aes_gcm192_hard_encrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag);
/**
* @brief AES-GCM-256 decryption
*
* @param[in] context The gcm context to use for encryption or decryption.
* @param[in] input_key The decryption key. must be 32bytes.
* @param[in] input_data The buffer holding the input data.
* @param[in] input_len The length of a data unit in bytes.
* This can be any length between 16 bytes and 2^31 bytes inclusive
* (between 1 and 2^27 block cipher blocks).
* @param[out] output_data The buffer holding the output data.
* @param[out] gcm_tag The buffer for holding the tag.The length of the tag must be 4 bytes.
*/
void aes_gcm256_hard_decrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag);
/**
* @brief AES-GCM-256 encryption
*
* @param[in] context The gcm context to use for encryption or decryption.
* @param[in] input_key The encryption key. must be 32bytes.
* @param[in] input_data The buffer holding the input data.
* @param[in] input_len The length of a data unit in bytes.
* This can be any length between 16 bytes and 2^31 bytes inclusive
* (between 1 and 2^27 block cipher blocks).
* @param[out] output_data The buffer holding the output data.
* @param[out] gcm_tag The buffer for holding the tag.The length of the tag must be 4 bytes.
*/
void aes_gcm256_hard_encrypt(gcm_context_t *context, uint8_t *input_data, size_t input_len, uint8_t *output_data, uint8_t *gcm_tag);
/**
* @brief This function initializes the AES hard module.
*
* @param[in] input_key The buffer holding the encryption or decryption key.
* @param[in] input_key_len The length of the input_key.must be 16bytes || 24bytes || 32bytes.
* @param[in] iv The initialization vector.
* @param[in] iv_len The length of the iv.GCM must be 12bytes. CBC must be 16bytes. ECB set 0L.
* @param[in] gcm_aad The buffer holding the Additional authenticated data. or NULL
* @param[in] cipher_mode Cipher Modes.must be AES_CBC || AES_ECB || AES_GCM.
* Other cipher modes, please look forward to the next generation of kendryte.
* @param[in] encrypt_sel The operation to perform:encryption or decryption.
* @param[in] gcm_aad_len The length of the gcm_aad.
* @param[in] input_data_len The length of the input_data.
*/
void aes_init(uint8_t *input_key, size_t input_key_len, uint8_t *iv,size_t iv_len, uint8_t *gcm_aad,
aes_cipher_mode_t cipher_mode, aes_encrypt_sel_t encrypt_sel, size_t gcm_aad_len, size_t input_data_len);
/**
* @brief This function feeds an input buffer into an encryption or decryption operation.
*
* @param[in] input_data The buffer holding the input data.
* @param[out] output_data The buffer holding the output data.
* @param[in] input_data_len The length of the input_data.
* @param[in] cipher_mode Cipher Modes.must be AES_CBC || AES_ECB || AES_GCM.
* Other cipher modes, please look forward to the next generation of kendryte.
*/
void aes_process(uint8_t *input_data, uint8_t *output_data, size_t input_data_len, aes_cipher_mode_t cipher_mode);
/**
* @brief This function get the gcm tag to verify.
*
* @param[out] gcm_tag The buffer holding the gcm tag.The length of the tag must be 16bytes.
*/
void gcm_get_tag(uint8_t *gcm_tag);
#ifdef __cplusplus
}

12
lib/drivers/include/clint.h
View File

@ -134,12 +134,12 @@ extern volatile clint_t* const clint;
/**
* @brief Definitions for the timer callbacks
*/
typedef int (*clint_timer_callback_t)(void* ctx);
typedef int (*clint_timer_callback_t)(void *ctx);
/**
* @brief Definitions for local interprocessor interrupt callbacks
*/
typedef int (*clint_ipi_callback_t)(void* ctx);
typedef int (*clint_ipi_callback_t)(void *ctx);
typedef struct _clint_timer_instance
{
@ -147,13 +147,13 @@ typedef struct _clint_timer_instance
uint64_t cycles;
uint64_t single_shot;
clint_timer_callback_t callback;
void* ctx;
void *ctx;
} clint_timer_instance_t;
typedef struct _clint_ipi_instance
{
clint_ipi_callback_t callback;
void* ctx;
void *ctx;
} clint_ipi_instance_t;
/**
@ -248,7 +248,7 @@ int clint_timer_set_single_shot(int single_shot);
* - 0 Success
* - Other Fail
*/
int clint_timer_register(clint_timer_callback_t callback, void* ctx);
int clint_timer_register(clint_timer_callback_t callback, void *ctx);
/**
* @brief Deregister user callback function
@ -319,7 +319,7 @@ int clint_ipi_clear(size_t core_id);
* - 0 Success
* - Other Fail
*/
int clint_ipi_register(clint_ipi_callback_t callback, void* ctx);
int clint_ipi_register(clint_ipi_callback_t callback, void *ctx);
/**
* @brief Deregister user callback function

59
lib/drivers/include/fft.h
View File

@ -68,16 +68,15 @@ typedef enum _fft_direction
*
*/
/**
* @brief input data fifo
* @brief The calculation data is input through this register
*
* No. 0 Register (0x00)
*/
typedef struct _fft_fft_input_fifo
typedef struct _fft_input_fifo
{
uint64_t fft_input_fifo : 64;
} __attribute__((packed, aligned(8))) fft_fft_input_fifo_t;
} __attribute__((packed, aligned(8))) fft_input_fifo_t;
/**
* @brief fft ctrl reg
@ -86,12 +85,25 @@ typedef struct _fft_fft_input_fifo
*/
typedef struct _fft_fft_ctrl
{
/**
*FFT calculation data length:
*b'000:512 point; b'001:256 point; b'010:128 point; b'011:64 point;
*/
uint64_t fft_point : 3;
/* FFT mode: b'0:FFT b'1:IFFT */
uint64_t fft_mode : 1;
/* Corresponding to the nine layer butterfly shift operation, 0x0: does not shift; 0x1: shift 1st layer. ...*/
uint64_t fft_shift : 9;
/* FFT enable: b'0:disable b'1:enable */
uint64_t fft_enable : 1;
/* FFT DMA enable: b'0:disable b'1:enable */
uint64_t dma_send : 1;
/**
*Input data arrangement: b'00:RIRI; b'01:only real part exist, RRRR;
*b'10:First input the real part and then input the imaginary part.
*/
uint64_t fft_input_mode : 2;
/* Effective width of input data. b'0:64bit effective; b'1:32bit effective */
uint64_t fft_data_mode : 1;
uint64_t reserved : 46;
} __attribute__((packed, aligned(8))) fft_fft_ctrl_t;
@ -103,8 +115,11 @@ typedef struct _fft_fft_ctrl
*/
typedef struct _fft_fifo_ctrl
{
/* Response memory initialization flag.b'1:initialization */
uint64_t resp_fifo_flush_n : 1;
/* Command memory initialization flag.b'1:initialization */
uint64_t cmd_fifo_flush_n : 1;
/* Output interface memory initialization flag.b'1:initialization */
uint64_t gs_fifo_flush_n : 1;
uint64_t reserved : 61;
} __attribute__((packed, aligned(8))) fft_fifo_ctrl_t;
@ -116,6 +131,11 @@ typedef struct _fft_fifo_ctrl
*/
typedef struct _fft_intr_mask
{
/**
*FFT return status set.
*b'0:FFT returns to the state after completion.
*b'1:FFT does not return to the state after completion
*/
uint64_t fft_done_mask : 1;
uint64_t reserved : 63;
} __attribute__((packed, aligned(8))) fft_intr_mask_t;
@ -127,6 +147,7 @@ typedef struct _fft_intr_mask
*/
typedef struct _fft_intr_clear
{
/* The interrupt state clears. b'1:clear current interrupt request */
uint64_t fft_done_clear : 1;
uint64_t reserved1 : 63;
} __attribute__((packed, aligned(8))) fft_intr_clear_t;
@ -136,32 +157,36 @@ typedef struct _fft_intr_clear
*
* No. 5 Register (0x28)
*/
typedef struct _fft_fft_status
typedef struct _fft_status
{
/* FFT calculation state.b'0:not completed; b'1:completed */
uint64_t fft_done_status : 1;
uint64_t reserved1 : 63;
} __attribute__((packed, aligned(8))) fft_fft_status_t;
} __attribute__((packed, aligned(8))) fft_status_t;
/**
* @brief fft_status_raw
* @brief fft status raw
*
* No. 6 Register (0x30)
*/
typedef struct _fft_fft_status_raw
typedef struct _fft_status_raw
{
/* FFT calculation state. b'1:done */
uint64_t fft_done_status_raw : 1;
uint64_t reserved : 63;
} __attribute__((packed, aligned(8))) fft_fft_status_raw_t;
/* FFT calculation state. b'1:working */
uint64_t fft_work_status_raw : 1;
uint64_t reserved : 62;
} __attribute__((packed, aligned(8))) fft_status_raw_t;
/**
* @brief fft_output_fifo
* @brief Output of FFT calculation data through this register
*
* No. 7 Register (0x38)
*/
typedef struct _fft_fft_output_fifo
typedef struct _fft_output_fifo
{
uint64_t fft_output_fifo : 64;
} __attribute__((packed, aligned(8))) fft_fft_output_fifo_t;
} __attribute__((packed, aligned(8))) fft_output_fifo_t;
/**
* @brief Fast Fourier transform (FFT) algorithm accelerator object
@ -177,7 +202,7 @@ typedef struct _fft_fft_output_fifo
typedef struct _fft
{
/* No. 0 (0x00): input data fifo */
fft_fft_input_fifo_t fft_input_fifo;
fft_input_fifo_t fft_input_fifo;
/* No. 1 (0x08): fft ctrl reg */
fft_fft_ctrl_t fft_ctrl;
/* No. 2 (0x10): fifo ctrl */
@ -187,11 +212,11 @@ typedef struct _fft
/* No. 4 (0x20): interrupt clear */
fft_intr_clear_t intr_clear;
/* No. 5 (0x28): fft status reg */
fft_fft_status_t fft_status;
fft_status_t fft_status;
/* No. 6 (0x30): fft_status_raw */
fft_fft_status_raw_t fft_status_raw;
fft_status_raw_t fft_status_raw;
/* No. 7 (0x38): fft_output_fifo */
fft_fft_output_fifo_t fft_output_fifo;
fft_output_fifo_t fft_output_fifo;
} __attribute__((packed, aligned(8))) fft_t;

2
lib/drivers/include/fpioa.h
View File

@ -990,7 +990,7 @@ int fpioa_get_io_driving(int number);
* - -1 Fail
* - Other The IO number
*/
int fpioa_get_io_by_func(fpioa_function_t function);
int fpioa_get_io_by_function(fpioa_function_t function);
#ifdef __cplusplus

4
lib/drivers/include/i2c.h
View File

@ -346,10 +346,10 @@ typedef enum _i2c_bus_speed_mode
* @param[in] i2c_num i2c number
* @param[in] slave_address i2c slave device address
* @param[in] address_width address width 7bit or 10bit
* @param[in] bus_speed_mode i2c rate
* @param[in] i2c_clk i2c clk rate
*/
void i2c_init(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width,
i2c_bus_speed_mode_t bus_speed_mode);
uint32_t i2c_clk);
/**
* @brief I2c send data

58
lib/drivers/include/sha256.h
View File

@ -21,28 +21,62 @@
extern "C" {
#endif
#define ENABLE_SHA 1
#define SHA256_BIG_ENDIAN (0x1 << 16)
#define ENABLE_SHA (0x1)
#define SHA256_BIG_ENDIAN (0x1)
#define SHA256_HASH_LEN 32
#define SHA256_HASH_WORDS 8
#define SHA256_BLOCK_LEN 64L
typedef struct _sha_num_reg
{
/* The total amount of data calculated by SHA256 is set by this register, and the smallest unit is 512bit. */
uint32_t sha_data_cnt : 16;
/* currently calculated block number. 512bit=1block*/
uint32_t sha_data_num : 16;
} __attribute__((packed, aligned(4))) sha_num_reg_t;
typedef struct _sha_function_reg_0
{
/* write:SHA256 enable register. read:Calculation completed flag */
uint32_t sha_en : 1;
uint32_t reserved00 : 7;
/* SHA256 calculation overflow flag */
uint32_t sha_overflow : 1;
uint32_t reserved01 : 7;
/* Endian setting; b'0:little endian b'1:big endian */
uint32_t sha_endian : 1;
uint32_t reserved02 : 15;
} __attribute__((packed, aligned(4))) sha_function_reg_0_t;
typedef struct _sha_function_reg_1
{
/* Sha and DMA handshake signals enable.b'1:enable;b'0:disable */
uint32_t dma_en : 1;
uint32_t reserved10 : 7;
/* b'1:sha256 fifo is full; b'0:not full */
uint32_t fifo_in_full : 1;
uint32_t reserved11 : 23;
} __attribute__((packed, aligned(4))) sha_function_reg_1_t;
typedef struct _sha256
{
/* Calculated sha256 return value. */
uint32_t sha_result[8];
/* SHA256 input data from this register. */
uint32_t sha_data_in1;
uint32_t sha_data_in2;
uint32_t sha_data_num;
uint32_t sha_status;
uint32_t reserved0;
uint32_t sha_input_ctrl;
uint32_t reselved0;
sha_num_reg_t sha_num_reg;
/* */
sha_function_reg_0_t sha_function_reg_0;
uint32_t reserved1;
sha_function_reg_1_t sha_function_reg_1;
} __attribute__((packed, aligned(4))) sha256_t;
typedef struct _sha256_context
{
size_t total_length;
size_t buffer_length;
size_t total_len;
size_t buffer_len;
union
{
uint32_t words[16];
@ -56,7 +90,7 @@ typedef struct _sha256_context
* @param[in] context SHA256 context object
*
*/
void sha256_init(sha256_context_t *context, size_t buf_len);
void sha256_init(sha256_context_t *context, size_t input_len);
/**
* @brief Called repeatedly with chunks of the message to be hashed
@ -66,7 +100,7 @@ void sha256_init(sha256_context_t *context, size_t buf_len);
* @param[in] buf_len length of data chunk
*
*/
void sha256_update(sha256_context_t *context, const void *data_buf, size_t buf_len);
void sha256_update(sha256_context_t *context, const void *input, size_t input_len);
/**
* @brief Finish SHA256 hash process, output the result.
@ -85,7 +119,7 @@ void sha256_final(sha256_context_t *context, uint8_t *output);
* @param[out] output Output buffer
*
*/
void sha256_hard_calculate(const uint8_t *data, size_t data_len, uint8_t *output);
void sha256_hard_calculate(const uint8_t *input, size_t input_len, uint8_t *output);
#ifdef __cplusplus
}

3
lib/drivers/include/spi.h
View File

@ -167,13 +167,14 @@ extern volatile spi_t *const spi[4];
* @param[in] mode Spi mode
* @param[in] frame_format Spi frame format
* @param[in] data_bit_length Spi data bit length
* @param[in] endian 0:little-endian 1:big-endian
*
* @return Result
* - 0 Success
* - Other Fail
*/
void spi_init(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_format_t frame_format,
size_t data_bit_length);
size_t data_bit_length, uint32_t endian);
/**
* @brief Set multiline configuration

125
lib/drivers/include/sysctl.h
View File

@ -176,6 +176,7 @@ typedef enum _sysctl_clock_t
SYSCTL_CLOCK_RTC,
SYSCTL_CLOCK_ACLK = 40,
SYSCTL_CLOCK_HCLK,
SYSCTL_CLOCK_IN0,
SYSCTL_CLOCK_MAX
} sysctl_clock_t;
@ -186,7 +187,7 @@ typedef enum _sysctl_clock_select_t
{
SYSCTL_CLOCK_SELECT_PLL0_BYPASS,
SYSCTL_CLOCK_SELECT_PLL1_BYPASS,
SYSCTL_CLOCK_SELECT_PLL3_BYPASS,
SYSCTL_CLOCK_SELECT_PLL2_BYPASS,
SYSCTL_CLOCK_SELECT_PLL2,
SYSCTL_CLOCK_SELECT_ACLK,
SYSCTL_CLOCK_SELECT_SPI3,
@ -235,7 +236,7 @@ typedef enum _sysctl_threshold_t
/**
* @brief System controller reset control id
*/
typedef enum _sysctl_reset_e
typedef enum _sysctl_reset_t
{
SYSCTL_RESET_SOC,
SYSCTL_RESET_ROM,
@ -269,10 +270,26 @@ typedef enum _sysctl_reset_e
SYSCTL_RESET_MAX = 31
} sysctl_reset_t;
typedef enum _io_power_mode
typedef enum _sysctl_power_bank
{
POWER_V33,
POWER_V18
SYSCTL_POWER_BANK0,
SYSCTL_POWER_BANK1,
SYSCTL_POWER_BANK2,
SYSCTL_POWER_BANK3,
SYSCTL_POWER_BANK4,
SYSCTL_POWER_BANK5,
SYSCTL_POWER_BANK6,
SYSCTL_POWER_BANK7,
SYSCTL_POWER_BANK_MAX,
} sysctl_power_bank_t;
/**
* @brief System controller reset control id
*/
typedef enum _sysctl_io_power_mode
{
SYSCTL_POWER_V33,
SYSCTL_POWER_V18
} sysctl_io_power_mode_t;
/**
@ -739,7 +756,6 @@ typedef struct _sysctl_power_sel
uint32_t reserved : 24;
} __attribute__((packed, aligned(4))) sysctl_power_sel_t;
/**
* @brief System controller object
*
@ -819,6 +835,25 @@ typedef struct _sysctl
uint32_t resv31;
} __attribute__((packed, aligned(4))) sysctl_t;
/**
* @brief Abstruct PLL struct
*/
typedef struct _sysctl_general_pll
{
uint32_t clkr : 4;
uint32_t clkf : 6;
uint32_t clkod : 4;
uint32_t bwadj : 6;
uint32_t pll_reset : 1;
uint32_t pll_pwrd : 1;
uint32_t pll_intfb : 1;
uint32_t pll_bypass : 1;
uint32_t pll_test : 1;
uint32_t pll_out_en : 1;
uint32_t pll_ckin_sel : 2;
uint32_t reserved : 4;
} __attribute__((packed, aligned(4))) sysctl_general_pll_t;
/**
* @brief System controller object instanse
*/
@ -892,15 +927,6 @@ int sysctl_clock_set_clock_select(sysctl_clock_select_t which, int select);
*/
int sysctl_clock_get_clock_select(sysctl_clock_select_t which);
/**
* @brief Get clock source frequency
*
* @param[in] input The input clock source
*
* @return The frequency of clock source
*/
uint32_t sysctl_clock_source_get_freq(sysctl_clock_source_t input);
/**
* @brief Get PLL frequency
*
@ -910,17 +936,6 @@ uint32_t sysctl_clock_source_get_freq(sysctl_clock_source_t input);
*/
uint32_t sysctl_pll_get_freq(sysctl_pll_t pll);
/**
* @brief Set PLL frequency and input clock
*
* @param[in] pll The PLL id
* @param[in] sel The selected PLL input clock
* @param[in] freq The frequency
*
* @return The frequency of PLL
*/
uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, sysctl_clock_source_t source, uint32_t freq);
/**
* @brief Get base clock frequency by clock id
*
@ -937,42 +952,6 @@ uint32_t sysctl_clock_get_freq(sysctl_clock_t clock);
*/
void sysctl_reset(sysctl_reset_t reset);
/**
* @brief Get git commit id
*
* @return The 4 bytes git commit id
*/
uint32_t sysctl_get_git_id(void);
/**
* @brief Get base clock frequency, default is 26MHz
*
* @return The base clock frequency
*/
uint32_t sysctl_get_freq(void);
/**
* @brief Get pll lock status
*
* @param[in] pll The pll id
*
* @return The lock status
* - 1 Pll is lock
* - 0 Pll have lost lock
*/
int sysctl_pll_is_lock(sysctl_pll_t pll);
/**
* @brief Clear pll lock status
*
* @param[in] pll The pll id
*
* @return Result
* - 0 Success
* - Other Fail
*/
int sysctl_pll_clear_slip(sysctl_pll_t pll);
/**
* @brief Enable the PLL and power on with reset
*
@ -1007,15 +986,6 @@ int sysctl_pll_disable(sysctl_pll_t pll);
*/
int sysctl_dma_select(sysctl_dma_channel_t channel, sysctl_dma_select_t select);
/**
* @brief Fast set all PLL and CPU clock
*
* @return Result
* - 0 Success
* - Other Fail
*/
uint32_t sysctl_pll_fast_enable_pll(void);
/**
* @brief Set SPI0_D0-D7 DVP_D0-D7 as spi and dvp data pin
*
@ -1025,7 +995,7 @@ uint32_t sysctl_pll_fast_enable_pll(void);
* - 0 Success
* - Other Fail
*/
uint32_t sysctl_spi0_dvp_data_set(uint8_t en);
uint32_t sysctl_set_spi0_dvp_data(uint8_t en);
/**
* @brief Set io power mode
@ -1037,20 +1007,23 @@ uint32_t sysctl_spi0_dvp_data_set(uint8_t en);
* - 0 Success
* - Other Fail
*/
uint32_t sysctl_power_mode_sel(uint8_t power_bank, sysctl_io_power_mode_t io_power_mode);
void sysctl_set_power_mode(sysctl_power_bank_t power_bank, sysctl_io_power_mode_t io_power_mode);
/**
* @brief Set frequency of CPU
* @param[in] frequency The desired frequency in Hz
* @param[in] freq The desired frequency in Hz
*
* @return The actual frequency of CPU after set
*/
uint32_t sysctl_set_cpu_frequency(uint32_t frequency);
uint32_t sysctl_cpu_set_freq(uint32_t freq);
/**
* @brief Init PLL freqency
* @param[in] pll The PLL id
* @param[in] pll_freq The desired frequency in Hz
*/
void sysctl_set_pll_frequency(uint64_t pll0, uint64_t pll1, uint64_t pll2);
uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, uint32_t pll_freq);
/**
* @brief Enable interrupt

10
lib/drivers/include/utils.h
View File

@ -297,7 +297,7 @@ extern "C" {
* @param[in] mask mask value
* @param[in] value The value to set
*/
void set_bit(volatile uint32_t* bits, uint32_t mask, uint32_t value);
void set_bit(volatile uint32_t *bits, uint32_t mask, uint32_t value);
/**
* @brief Set value by mask
@ -307,7 +307,7 @@ void set_bit(volatile uint32_t* bits, uint32_t mask, uint32_t value);
* @param[in] offset Mask's offset
* @param[in] value The value to set
*/
void set_bit_offset(volatile uint32_t* bits, uint32_t mask, size_t offset, uint32_t value);
void set_bit_offset(volatile uint32_t *bits, uint32_t mask, size_t offset, uint32_t value);
/**
* @brief Set bit for gpio, only set one bit
@ -316,7 +316,7 @@ void set_bit_offset(volatile uint32_t* bits, uint32_t mask, size_t offset, uint3
* @param[in] idx Offset value
* @param[in] value The value to set
*/
void set_gpio_bit(volatile uint32_t* bits, size_t idx, uint32_t value);
void set_gpio_bit(volatile uint32_t *bits, size_t idx, uint32_t value);
/**
* @brief Get bits value of mask
@ -327,7 +327,7 @@ void set_gpio_bit(volatile uint32_t* bits, size_t idx, uint32_t value);
*
* @return The bits value of mask
*/
uint32_t get_bit(volatile uint32_t* bits, uint32_t mask, size_t offset);
uint32_t get_bit(volatile uint32_t *bits, uint32_t mask, size_t offset);
/**
* @brief Get a bit value by offset
@ -338,7 +338,7 @@ uint32_t get_bit(volatile uint32_t* bits, uint32_t mask, size_t offset);
*
* @return The bit value
*/
uint32_t get_gpio_bit(volatile uint32_t* bits, size_t offset);
uint32_t get_gpio_bit(volatile uint32_t *bits, size_t offset);
#ifdef __cplusplus
}

8
lib/drivers/include/wdt.h
View File

@ -141,6 +141,14 @@ void wdt_start(wdt_device_number_t id, uint64_t time_out_ms, plic_irq_callback_t
*/
void wdt_stop(wdt_device_number_t id);
/**
* @brief Clear wdt interrupt
*
* @param[in] id Wdt id 0 or 1
*
*/
void wdt_clear_interrupt(wdt_device_number_t id);
#ifdef __cplusplus
}
#endif

4
lib/drivers/plic.c
View File

@ -24,7 +24,7 @@ volatile plic_t* const plic = (volatile plic_t*)PLIC_BASE_ADDR;
typedef struct _plic_instance_t
{
plic_irq_callback_t callback;
void* ctx;
void *ctx;
} plic_instance_t;
static plic_instance_t plic_instance[PLIC_NUM_CORES][IRQN_MAX];
@ -138,7 +138,7 @@ int plic_irq_complete(uint32_t source)
return 0;
}
void plic_irq_register(plic_irq_t irq, plic_irq_callback_t callback, void* ctx)
void plic_irq_register(plic_irq_t irq, plic_irq_callback_t callback, void *ctx)
{
/* Read core id */
unsigned long core_id = current_coreid();

2
lib/drivers/rtc.c
View File

@ -577,7 +577,7 @@ int rtc_init(void)
rtc_protect_set(0);
/* Set RTC clock frequency */
rtc_timer_set_clock_frequency(
sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0)
sysctl_clock_get_freq(SYSCTL_CLOCK_IN0)
);
rtc_timer_set_clock_count_value(1);

63
lib/drivers/sha256.c
View File

@ -32,7 +32,7 @@ static const uint8_t padding[64] =
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static inline uint64_t byteswap64(uint64_t x)
@ -42,47 +42,46 @@ static inline uint64_t byteswap64(uint64_t x)
return ((uint64_t)BYTESWAP(b) << 32) | (uint64_t)BYTESWAP(a);
}
void sha256_init(sha256_context_t *context, size_t buf_len)
void sha256_init(sha256_context_t *context, size_t input_len)
{
sysctl_clock_enable(SYSCTL_CLOCK_SHA);
sysctl_reset(SYSCTL_RESET_SHA);
sha256->sha_data_num = (uint32_t)((buf_len + SHA256_BLOCK_LEN + 8) / SHA256_BLOCK_LEN);
sha256->sha_input_ctrl &= (~0x1);
sha256->sha_status |= SHA256_BIG_ENDIAN;
sha256->sha_status |= ENABLE_SHA;
context->total_length = 0LL;
context->buffer_length = 0L;
sha256->sha_num_reg.sha_data_cnt = (uint32_t)((input_len + SHA256_BLOCK_LEN + 8) / SHA256_BLOCK_LEN);
sha256->sha_function_reg_1.dma_en = 0x0;
sha256->sha_function_reg_0.sha_endian = SHA256_BIG_ENDIAN;
sha256->sha_function_reg_0.sha_en = ENABLE_SHA;
context->total_len = 0L;
context->buffer_len = 0L;
}
void sha256_update(sha256_context_t *context, const void *data_buf, size_t buf_len)
void sha256_update(sha256_context_t *context, const void *input, size_t input_len)
{
const uint8_t* data = data_buf;
const uint8_t *data = input;
size_t buffer_bytes_left;
size_t bytes_to_copy;
uint32_t i;
while (buf_len)
while (input_len)
{
buffer_bytes_left = SHA256_BLOCK_LEN - context->buffer_length;
buffer_bytes_left = SHA256_BLOCK_LEN - context->buffer_len;
bytes_to_copy = buffer_bytes_left;
if (bytes_to_copy > buf_len)
bytes_to_copy = buf_len;
memcpy(&context->buffer.bytes[context->buffer_length], data, bytes_to_copy);
context->total_length += bytes_to_copy * 8;
context->buffer_length += bytes_to_copy;
if (bytes_to_copy > input_len)
bytes_to_copy = input_len;
memcpy(&context->buffer.bytes[context->buffer_len], data, bytes_to_copy);
context->total_len += bytes_to_copy * 8L;
context->buffer_len += bytes_to_copy;
data += bytes_to_copy;
buf_len -= bytes_to_copy;
if (context->buffer_length == SHA256_BLOCK_LEN)
input_len -= bytes_to_copy;
if (context->buffer_len == SHA256_BLOCK_LEN)
{
for (i = 0; i < 16; i++)
{
while (sha256->sha_input_ctrl & (1 << 8))
while (sha256->sha_function_reg_1.fifo_in_full)
;
sha256->sha_data_in1 = context->buffer.words[i];
}
context->buffer_length = 0L;
context->buffer_len = 0L;
}
}
}
@ -93,29 +92,29 @@ void sha256_final(sha256_context_t *context, uint8_t *output)
size_t length_pad;
uint32_t i;
bytes_to_pad = 120 - context->buffer_length;
if (bytes_to_pad > 64)
bytes_to_pad -= 64;
length_pad = BYTESWAP64(context->total_length);
bytes_to_pad = 120L - context->buffer_len;
if (bytes_to_pad > 64L)
bytes_to_pad -= 64L;
length_pad = BYTESWAP64(context->total_len);
sha256_update(context, padding, bytes_to_pad);
sha256_update(context, &length_pad, 8);
while (!(sha256->sha_status & 0x01))
sha256_update(context, &length_pad, 8L);
while (!(sha256->sha_function_reg_0.sha_en))
;
if (output)
{
for (i = 0; i < SHA256_HASH_WORDS; i++)
{
*((uint32_t*)output) = sha256->sha_result[SHA256_HASH_WORDS - i - 1];
*((uint32_t *)output) = sha256->sha_result[SHA256_HASH_WORDS - i - 1];
output += 4;
}
}
}
void sha256_hard_calculate(const uint8_t *data, size_t data_len, uint8_t *output)
void sha256_hard_calculate(const uint8_t *input, size_t input_len, uint8_t *output)
{
sha256_context_t sha;
sha256_init(&sha, data_len);
sha256_update(&sha, data, data_len);
sha256_init(&sha, input_len);
sha256_update(&sha, input, input_len);
sha256_final(&sha, output);
}

9
lib/drivers/spi.c
View File

@ -59,7 +59,7 @@ static void spi_set_tmod(uint8_t spi_num, uint32_t tmod)
}
void spi_init(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_format_t frame_format,
size_t data_bit_length)
size_t data_bit_length, uint32_t endian)
{
configASSERT(data_bit_length >= 4 && data_bit_length <= 32);
configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2);
@ -108,6 +108,7 @@ void spi_init(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_for
spi_adapter->ssienr = 0x00;
spi_adapter->ctrlr0 = (work_mode << 6) | (frame_format << frf_offset) | ((data_bit_length - 1) << dfs_offset);
spi_adapter->spi_ctrlr0 = 0;
spi_adapter->endian = endian;
}
void spi_init_non_standard(spi_device_num_t spi_num, uint32_t instruction_length, uint32_t address_length,
@ -221,7 +222,7 @@ void spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_nu
DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, cmd_len + tx_len);
spi_handle->ser = 1U << chip_select;
dmac_wait_done(channel_num);
free((void*)buf);
free((void *)buf);
while ((spi_handle->sr & 0x05) != 0x04)
;
@ -263,7 +264,7 @@ void spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_
DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, tx_len);
spi_handle->ser = 1U << chip_select;
dmac_wait_done(channel_num);
free((void*)buf);
free((void *)buf);
while ((spi_handle->sr & 0x05) != 0x04)
;
@ -459,7 +460,7 @@ void spi_send_data_multiple_dma(dmac_channel_number_t channel_num, spi_device_nu
DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, cmd_len + tx_len);
spi_handle->ser = 1U << chip_select;
dmac_wait_done(channel_num);
free((void*)buf);
free((void *)buf);
while ((spi_handle->sr & 0x05) != 0x04)
;

193
lib/drivers/sysctl.c
View File

@ -403,8 +403,16 @@ int sysctl_clock_disable(sysctl_clock_t clock)
int sysctl_clock_set_threshold(sysctl_threshold_t which, int threshold)
{
int result = 0;
switch (which)
{
/*
* These threshold is 2 bit width
*/
case SYSCTL_THRESHOLD_ACLK:
sysctl->clk_sel0.aclk_divider_sel = (uint8_t)threshold & 0x03;
break;
/*
* These threshold is 3 bit width
*/
@ -500,10 +508,10 @@ int sysctl_clock_set_threshold(sysctl_threshold_t which, int threshold)
break;
default:
result = -1;
break;
}
return 0;
return result;
}
int sysctl_clock_get_threshold(sysctl_threshold_t which)
@ -606,6 +614,7 @@ int sysctl_clock_get_threshold(sysctl_threshold_t which)
int sysctl_clock_set_clock_select(sysctl_clock_select_t which, int select)
{
int result = 0;
switch (which)
{
/*
@ -617,7 +626,7 @@ int sysctl_clock_set_clock_select(sysctl_clock_select_t which, int select)
case SYSCTL_CLOCK_SELECT_PLL1_BYPASS:
sysctl->pll1.pll_bypass1 = select & 0x01;
break;
case SYSCTL_CLOCK_SELECT_PLL3_BYPASS:
case SYSCTL_CLOCK_SELECT_PLL2_BYPASS:
sysctl->pll2.pll_bypass2 = select & 0x01;
break;
case SYSCTL_CLOCK_SELECT_ACLK:
@ -647,10 +656,11 @@ int sysctl_clock_set_clock_select(sysctl_clock_select_t which, int select)
break;
default:
result = -1;
break;
}
return 0;
return result;
}
int sysctl_clock_get_clock_select(sysctl_clock_select_t which)
@ -668,7 +678,7 @@ int sysctl_clock_get_clock_select(sysctl_clock_select_t which)
case SYSCTL_CLOCK_SELECT_PLL1_BYPASS:
clock_select = (int)sysctl->pll1.pll_bypass1;
break;
case SYSCTL_CLOCK_SELECT_PLL3_BYPASS:
case SYSCTL_CLOCK_SELECT_PLL2_BYPASS:
clock_select = (int)sysctl->pll2.pll_bypass2;
break;
case SYSCTL_CLOCK_SELECT_PLL2:
@ -721,7 +731,6 @@ uint32_t sysctl_clock_source_get_freq(sysctl_clock_source_t input)
case SYSCTL_SOURCE_ACLK:
result = sysctl_clock_get_freq(SYSCTL_CLOCK_ACLK);
break;
default:
result = 0;
break;
@ -729,7 +738,7 @@ uint32_t sysctl_clock_source_get_freq(sysctl_clock_source_t input)
return result;
}
int sysctl_pll_is_lock(sysctl_pll_t pll)
static int sysctl_pll_is_lock(sysctl_pll_t pll)
{
/*
* All bit enable means PLL lock
@ -772,7 +781,7 @@ int sysctl_pll_is_lock(sysctl_pll_t pll)
return 0;
}
int sysctl_pll_clear_slip(sysctl_pll_t pll)
static int sysctl_pll_clear_slip(sysctl_pll_t pll)
{
if (pll >= SYSCTL_PLL_MAX)
return -1;
@ -838,6 +847,8 @@ int sysctl_pll_enable(sysctl_pll_t pll)
*/
sysctl->pll0.pll_reset0 = 0;
sysctl->pll0.pll_reset0 = 1;
asm volatile ("nop");
asm volatile ("nop");
sysctl->pll0.pll_reset0 = 0;
break;
@ -857,6 +868,8 @@ int sysctl_pll_enable(sysctl_pll_t pll)
*/
sysctl->pll1.pll_reset1 = 0;
sysctl->pll1.pll_reset1 = 1;
asm volatile ("nop");
asm volatile ("nop");
sysctl->pll1.pll_reset1 = 0;
break;
@ -876,6 +889,8 @@ int sysctl_pll_enable(sysctl_pll_t pll)
*/
sysctl->pll2.pll_reset2 = 0;
sysctl->pll2.pll_reset2 = 1;
asm volatile ("nop");
asm volatile ("nop");
sysctl->pll2.pll_reset2 = 0;
break;
@ -960,7 +975,7 @@ uint32_t sysctl_pll_get_freq(sysctl_pll_t pll)
case SYSCTL_PLL2:
/*
* Get input frequency accroding select register
* Get input freq accroding select register
*/
select = sysctl->pll2.pll_ckin_sel2;
if (select < sizeof(get_source_pll2))
@ -978,14 +993,14 @@ uint32_t sysctl_pll_get_freq(sysctl_pll_t pll)
}
/*
* Get final PLL output frequency
* Get final PLL output freq
* FOUT = FIN / NR * NF / OD
*/
freq_out = (double)freq_in / (double)nr * (double)nf / (double)od;
return freq_out;
}
uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, sysctl_clock_source_t source, uint32_t freq)
static uint32_t sysctl_pll_source_set_freq(sysctl_pll_t pll, sysctl_clock_source_t source, uint32_t freq)
{
uint32_t freq_in = 0;
@ -1006,7 +1021,7 @@ uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, sysctl_clock_source_t source, uin
return 0;
freq_in = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0);
/*
* Check input clock frequency
* Check input clock freq
*/
if (freq_in == 0)
return 0;
@ -1019,7 +1034,7 @@ uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, sysctl_clock_source_t source, uin
if (source < sizeof(get_select_pll2))
freq_in = sysctl_clock_source_get_freq(source);
/*
* Check input clock frequency
* Check input clock freq
*/
if (freq_in == 0)
return 0;
@ -1076,12 +1091,7 @@ uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, sysctl_clock_source_t source, uin
val = fout / fin;
terr = 0.5 / ((double)(nf_max / 2));
first = firstx = 1;
if (terr == -1)
{
printf("NR\tNF\tOD\tNB\tFvco\t\terror\n");
printf("------------------------------------------------------\n");
}
else if (terr != -2)
if (terr != -2)
{
first = 0;
if (terr == 0)
@ -1183,16 +1193,14 @@ uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, sysctl_clock_source_t source, uin
x_nb = nb;
x_fvco = fvco;
x_err = err;
first = firstx = 0;
merr = fabs(err);
first = firstx = 0;
merr = fabs(err);
if (terr != -1)
continue;
printf("%d\t%lld\t%d\t%d\t%e\t%#+g\n", nrx, nfx, no, nb, fvco, err);
}
}
if (!found)
{
printf("Error: No workable settings found.\n");
return 0;
}
@ -1204,29 +1212,9 @@ uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, sysctl_clock_source_t source, uin
err = x_err;
if ((terr != -2) && (fabs(err) >= terr * (1 - 1e-6)))
{
printf("Error: No appropriate ratio found.\n");
return 0;
}
#ifdef CONFIG_PLL_DEBUG_ENABLE
printf("NR = %d\n", nrx);
printf("NF = %lld\n", nfx);
printf("OD = %d\n", no);
printf("NB = %d\n", nb);
printf("\n");
printf("Fin = %g\n", fin);
printf("Fvco = %g\n", fvco);
printf("Fout = %g\n", fvco / no);
printf("error = %+g\n", err);
printf("\n");
printf("CLKR[3:0] = %02x\n", nrx - 1);
printf("CLKF[5:0] = %02x\n", (unsigned int)nfx - 1);
printf("CLKOD[3:0] = %02x\n", no - 1);
printf("BWADJ[5:0] = %02x\n", nb - 1);
#endif /* CONFIG_PLL_DEBUG_ENABLE */
/*
* Begin write PLL registers' value,
* Using atomic write method.
@ -1290,6 +1278,14 @@ uint32_t sysctl_clock_get_freq(sysctl_clock_t clock)
switch (clock)
{
/*
* The clock IN0
*/
case SYSCTL_CLOCK_IN0:
source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0);
result = source;
break;
/*
* These clock directly under PLL clock domain
* They are using gated divider.
@ -1604,7 +1600,7 @@ uint32_t sysctl_clock_get_freq(sysctl_clock_t clock)
result = source;
break;
case SYSCTL_CLOCK_RTC:
source = sysctl_clock_get_freq(SYSCTL_CLOCK_APB1);
source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0);
result = source;
break;
@ -1727,71 +1723,92 @@ uint32_t sysctl_pll_fast_enable_pll(void)
return 0;
}
uint32_t sysctl_spi0_dvp_data_set(uint8_t en)
uint32_t sysctl_set_spi0_dvp_data(uint8_t en)
{
sysctl->misc.spi_dvp_data_enable = en;
return 0;
}
uint32_t sysctl_power_mode_sel(uint8_t power_bank, sysctl_io_power_mode_t io_power_mode)
void sysctl_set_power_mode(sysctl_power_bank_t power_bank, sysctl_io_power_mode_t io_power_mode)
{
if(io_power_mode)
*((uint32_t *)(&sysctl->power_sel)) |= (1 << power_bank);
else
*((uint32_t *)(&sysctl->power_sel)) &= ~(1 << power_bank);
return 0;
}
void sysctl_set_pll_frequency(uint64_t pll0, uint64_t pll1, uint64_t pll2)
uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, uint32_t pll_freq)
{
sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_IN0);
if(pll_freq == 0)
return 0;
sysctl_pll_enable(SYSCTL_PLL0);
sysctl_pll_set_freq(SYSCTL_PLL0, SYSCTL_SOURCE_IN0, pll0);
while (sysctl_pll_is_lock(SYSCTL_PLL0) == 0)
sysctl_pll_clear_slip(SYSCTL_PLL0);
sysctl_clock_enable(SYSCTL_CLOCK_PLL0);
sysctl->clk_sel0.aclk_divider_sel = 0;
sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0);
sysctl_pll_enable(SYSCTL_PLL1);
sysctl_pll_set_freq(SYSCTL_PLL1, SYSCTL_SOURCE_IN0, pll1);
while (sysctl_pll_is_lock(SYSCTL_PLL1) == 0)
sysctl_pll_clear_slip(SYSCTL_PLL1);
sysctl_clock_enable(SYSCTL_CLOCK_PLL1);
sysctl_pll_enable(SYSCTL_PLL2);
sysctl_pll_set_freq(SYSCTL_PLL2, SYSCTL_SOURCE_IN0, pll2);
while (sysctl_pll_is_lock(SYSCTL_PLL2) == 0)
sysctl_pll_clear_slip(SYSCTL_PLL2);
sysctl_clock_enable(SYSCTL_CLOCK_PLL2);
}
uint32_t sysctl_set_cpu_frequency(uint32_t frequency)
{
sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_IN0);
sysctl->pll0.pll_reset0 = 1;
uint32_t result = sysctl_pll_set_freq(SYSCTL_PLL0, SYSCTL_SOURCE_IN0, frequency * 2);
sysctl->pll0.pll_reset0 = 0;
while (1)
volatile sysctl_general_pll_t *v_pll_t;
switch(pll)
{
uint32_t lock = sysctl->pll_lock.pll_lock0 & 0x3;
if (lock == 0x3)
{
case SYSCTL_PLL0:
v_pll_t = (sysctl_general_pll_t *)(&sysctl->pll0);
break;
case SYSCTL_PLL1:
v_pll_t = (sysctl_general_pll_t *)(&sysctl->pll1);
break;
case SYSCTL_PLL2:
v_pll_t = (sysctl_general_pll_t *)(&sysctl->pll2);
break;
default:
return 0;
break;
}
else
{
sysctl->pll_lock.pll_slip_clear0 = 1;
}
}
sysctl->pll0.pll_out_en0 = 1;
sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0);
/* 1. Change CPU CLK to XTAL */
if(pll == SYSCTL_PLL0)
sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_IN0);
/* 2. Disable PLL output */
v_pll_t->pll_out_en = 0;
/* 3. Turn off PLL */
v_pll_t->pll_pwrd = 0;
/* 4. Set PLL new value */
uint32_t result;
if(pll == SYSCTL_PLL2)
result = sysctl_pll_source_set_freq(pll, v_pll_t->pll_ckin_sel, pll_freq);
else
result = sysctl_pll_source_set_freq(pll, SYSCTL_SOURCE_IN0, pll_freq);
/* 5. Power on PLL */
v_pll_t->pll_pwrd = 1;
/* 6. Reset PLL then Release Reset*/
v_pll_t->pll_reset = 0;
v_pll_t->pll_reset = 1;
/* wait 100ns */
asm volatile ("nop");
asm volatile ("nop");
v_pll_t->pll_reset = 0;
/* 7. Get lock status, wait PLL stable */
while (sysctl_pll_is_lock(pll) == 0)
sysctl_pll_clear_slip(pll);
/* 8. Enable PLL output */
v_pll_t->pll_out_en = 1;
/* 9. Change CPU CLK to PLL */
if(pll == SYSCTL_PLL0)
sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0);
return result;
}
uint32_t sysctl_cpu_set_freq(uint32_t freq)
{
if(freq == 0)
return 0;
return sysctl_pll_set_freq(SYSCTL_PLL0, (sysctl->clk_sel0.aclk_divider_sel + 1) * 2 * freq);
}
void sysctl_enable_irq(void)
{
set_csr(mie, MIP_MEIP);

10
lib/drivers/utils.c
View File

@ -16,28 +16,28 @@
#include "encoding.h"
#include "utils.h"
void set_bit(volatile uint32_t* bits, uint32_t mask, uint32_t value)
void set_bit(volatile uint32_t *bits, uint32_t mask, uint32_t value)
{
uint32_t org = (*bits) & ~mask;
*bits = org | (value & mask);
}
void set_bit_offset(volatile uint32_t* bits, uint32_t mask, size_t offset, uint32_t value)
void set_bit_offset(volatile uint32_t *bits, uint32_t mask, size_t offset, uint32_t value)
{
set_bit(bits, mask << offset, value << offset);
}
void set_gpio_bit(volatile uint32_t* bits, size_t offset, uint32_t value)
void set_gpio_bit(volatile uint32_t *bits, size_t offset, uint32_t value)
{
set_bit_offset(bits, 1, offset, value);
}
uint32_t get_bit(volatile uint32_t* bits, uint32_t mask, size_t offset)
uint32_t get_bit(volatile uint32_t *bits, uint32_t mask, size_t offset)
{
return ((*bits) & (mask << offset)) >> offset;
}
uint32_t get_gpio_bit(volatile uint32_t* bits, size_t offset)
uint32_t get_gpio_bit(volatile uint32_t *bits, size_t offset)
{
return get_bit(bits, 1, offset);
}

366
lib/firmware/include/font.h
View File

@ -1,366 +0,0 @@
/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _FONT_H_
#define _FONT_H_
#include <stdint.h>
uint8_t const ascii0816[] =
{
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x81, 0xA5, 0x81, 0x81, 0xBD,
0x99, 0x81, 0x81, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0xFF,
0xDB, 0xFF, 0xFF, 0xC3, 0xE7, 0xFF, 0xFF, 0x7E, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x6C, 0xFE, 0xFE, 0xFE, 0xFE, 0x7C, 0x38, 0x10,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x38, 0x7C, 0xFE,
0x7C, 0x38, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
0x3C, 0x3C, 0xE7, 0xE7, 0xE7, 0x18, 0x18, 0x3C, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x18, 0x3C, 0x7E, 0xFF, 0xFF, 0x7E, 0x18, 0x18, 0x3C,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x3C,
0x3C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xE7, 0xC3, 0xC3, 0xE7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x66, 0x42, 0x42, 0x66, 0x3C, 0x00,
0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC3, 0x99, 0xBD,
0xBD, 0x99, 0xC3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x1E, 0x0E,
0x1A, 0x32, 0x78, 0xCC, 0xCC, 0xCC, 0xCC, 0x78, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x3C, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x18, 0x7E, 0x18, 0x18,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x33, 0x3F, 0x30, 0x30, 0x30,
0x30, 0x70, 0xF0, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x63,
0x7F, 0x63, 0x63, 0x63, 0x63, 0x67, 0xE7, 0xE6, 0xC0, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x18, 0x18, 0xDB, 0x3C, 0xE7, 0x3C, 0xDB, 0x18, 0x18,
0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xE0, 0xF0, 0xF8, 0xFE, 0xF8,
0xF0, 0xE0, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x06, 0x0E,
0x1E, 0x3E, 0xFE, 0x3E, 0x1E, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x18, 0x3C, 0x7E, 0x18, 0x18, 0x18, 0x7E, 0x3C, 0x18, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66,
0x66, 0x00, 0x66, 0x66, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0xDB,
0xDB, 0xDB, 0x7B, 0x1B, 0x1B, 0x1B, 0x1B, 0x1B, 0x00, 0x00, 0x00, 0x00,
0x00, 0x7C, 0xC6, 0x60, 0x38, 0x6C, 0xC6, 0xC6, 0x6C, 0x38, 0x0C, 0xC6,
0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xFE, 0xFE, 0xFE, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x3C,
0x7E, 0x18, 0x18, 0x18, 0x7E, 0x3C, 0x18, 0x7E, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x18, 0x3C, 0x7E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x18, 0x7E, 0x3C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x18, 0x0C, 0xFE, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x60, 0xFE, 0x60, 0x30, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xC0,
0xC0, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x28, 0x6C, 0xFE, 0x6C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x10, 0x38, 0x38, 0x7C, 0x7C, 0xFE, 0xFE, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFE, 0x7C, 0x7C,
0x38, 0x38, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x18, 0x3C, 0x3C, 0x3C, 0x18, 0x18, 0x18, 0x00, 0x18, 0x18,
0x00, 0x00, 0x00, 0x00, 0x00, 0x66, 0x66, 0x66, 0x24, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6C,
0x6C, 0xFE, 0x6C, 0x6C, 0x6C, 0xFE, 0x6C, 0x6C, 0x00, 0x00, 0x00, 0x00,
0x18, 0x18, 0x7C, 0xC6, 0xC2, 0xC0, 0x7C, 0x06, 0x06, 0x86, 0xC6, 0x7C,
0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC2, 0xC6, 0x0C, 0x18,
0x30, 0x60, 0xC6, 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x6C,
0x6C, 0x38, 0x76, 0xDC, 0xCC, 0xCC, 0xCC, 0x76, 0x00, 0x00, 0x00, 0x00,
0x00, 0x30, 0x30, 0x30, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x18, 0x30, 0x30, 0x30, 0x30,
0x30, 0x30, 0x18, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x18,
0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x18, 0x30, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x66, 0x3C, 0xFF, 0x3C, 0x66, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x7E,
0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x18, 0x30, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x02, 0x06, 0x0C, 0x18, 0x30, 0x60, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x38, 0x6C, 0xC6, 0xC6, 0xD6, 0xD6, 0xC6, 0xC6, 0x6C, 0x38,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x38, 0x78, 0x18, 0x18, 0x18,
0x18, 0x18, 0x18, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0xC6,
0x06, 0x0C, 0x18, 0x30, 0x60, 0xC0, 0xC6, 0xFE, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x7C, 0xC6, 0x06, 0x06, 0x3C, 0x06, 0x06, 0x06, 0xC6, 0x7C,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x1C, 0x3C, 0x6C, 0xCC, 0xFE,
0x0C, 0x0C, 0x0C, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xC0,
0xC0, 0xC0, 0xFC, 0x06, 0x06, 0x06, 0xC6, 0x7C, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x38, 0x60, 0xC0, 0xC0, 0xFC, 0xC6, 0xC6, 0xC6, 0xC6, 0x7C,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xC6, 0x06, 0x06, 0x0C, 0x18,
0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0xC6,
0xC6, 0xC6, 0x7C, 0xC6, 0xC6, 0xC6, 0xC6, 0x7C, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x7C, 0xC6, 0xC6, 0xC6, 0x7E, 0x06, 0x06, 0x06, 0x0C, 0x78,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00,
0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x18, 0x18, 0x00, 0x00, 0x00, 0x18, 0x18, 0x30, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x30, 0x18, 0x0C, 0x06,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00,
0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
0x30, 0x18, 0x0C, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x7C, 0xC6, 0xC6, 0x0C, 0x18, 0x18, 0x18, 0x00, 0x18, 0x18,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0xC6, 0xC6, 0xDE, 0xDE,
0xDE, 0xDC, 0xC0, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x38,
0x6C, 0xC6, 0xC6, 0xFE, 0xC6, 0xC6, 0xC6, 0xC6, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0xFC, 0x66, 0x66, 0x66, 0x7C, 0x66, 0x66, 0x66, 0x66, 0xFC,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x66, 0xC2, 0xC0, 0xC0, 0xC0,
0xC0, 0xC2, 0x66, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x6C,
0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x6C, 0xF8, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0xFE, 0x66, 0x62, 0x68, 0x78, 0x68, 0x60, 0x62, 0x66, 0xFE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x66, 0x62, 0x68, 0x78, 0x68,
0x60, 0x60, 0x60, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x66,
0xC2, 0xC0, 0xC0, 0xDE, 0xC6, 0xC6, 0x66, 0x3A, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0xC6, 0xC6, 0xC6, 0xC6, 0xFE, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x18, 0x18, 0x18, 0x18, 0x18,
0x18, 0x18, 0x18, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x0C,
0x0C, 0x0C, 0x0C, 0x0C, 0xCC, 0xCC, 0xCC, 0x78, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0xE6, 0x66, 0x66, 0x6C, 0x78, 0x78, 0x6C, 0x66, 0x66, 0xE6,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x60, 0x60, 0x60, 0x60, 0x60,
0x60, 0x62, 0x66, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC6, 0xEE,
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0x00, 0x00, 0x00, 0xFF, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1F, 0x18, 0x18, 0x18, 0x18,
0x18, 0x18, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x18, 0x18,
0x18, 0x18, 0x18, 0xFF, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x18, 0x18, 0x18, 0x18, 0x18, 0x1F, 0x18, 0x1F, 0x18, 0x18, 0x18, 0x18,
0x18, 0x18, 0x18, 0x18, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x37,
0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
0x36, 0x37, 0x30, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x30, 0x37, 0x36, 0x36, 0x36, 0x36,
0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0xF7, 0x00, 0xFF,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0xFF, 0x00, 0xF7, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
0x36, 0x36, 0x36, 0x36, 0x36, 0x37, 0x30, 0x37, 0x36, 0x36, 0x36, 0x36,
0x36, 0x36, 0x36, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x36, 0x36, 0x36, 0x36,
0x36, 0xF7, 0x00, 0xF7, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
0x18, 0x18, 0x18, 0x18, 0x18, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0xFF,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0xFF, 0x00, 0xFF, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x36, 0x36, 0x36, 0x36,
0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x3F,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x18, 0x18,
0x18, 0x1F, 0x18, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x18, 0x1F, 0x18, 0x18, 0x18, 0x18,
0x18, 0x18, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
0x36, 0x36, 0x36, 0xFF, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
0x18, 0x18, 0x18, 0x18, 0x18, 0xFF, 0x18, 0xFF, 0x18, 0x18, 0x18, 0x18,
0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0xF8,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x1F, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xF0, 0xF0, 0xF0,
0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
0x0F, 0x0F, 0x0F, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x76, 0xDC, 0xD8, 0xD8, 0xD8, 0xDC, 0x76, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x78, 0xCC, 0xCC, 0xCC, 0xD8, 0xCC, 0xC6, 0xC6, 0xC6, 0xCC,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xC6, 0xC6, 0xC0, 0xC0, 0xC0,
0xC0, 0xC0, 0xC0, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xFE, 0x6C, 0x6C, 0x6C, 0x6C, 0x6C, 0x6C, 0x6C, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0xFE, 0xC6, 0x60, 0x30, 0x18, 0x30, 0x60, 0xC6, 0xFE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0xD8, 0xD8,
0xD8, 0xD8, 0xD8, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x66, 0x66, 0x66, 0x66, 0x66, 0x7C, 0x60, 0x60, 0xC0, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x76, 0xDC, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x18, 0x3C, 0x66, 0x66,
0x66, 0x3C, 0x18, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
0x6C, 0xC6, 0xC6, 0xFE, 0xC6, 0xC6, 0x6C, 0x38, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x38, 0x6C, 0xC6, 0xC6, 0xC6, 0x6C, 0x6C, 0x6C, 0x6C, 0xEE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x30, 0x18, 0x0C, 0x3E, 0x66,
0x66, 0x66, 0x66, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x7E, 0xDB, 0xDB, 0xDB, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x03, 0x06, 0x7E, 0xDB, 0xDB, 0xF3, 0x7E, 0x60, 0xC0,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x30, 0x60, 0x60, 0x7C, 0x60,
0x60, 0x60, 0x30, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C,
0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0xFE, 0x00, 0x00, 0xFE, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x7E, 0x18,
0x18, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
0x18, 0x0C, 0x06, 0x0C, 0x18, 0x30, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x0C, 0x18, 0x30, 0x60, 0x30, 0x18, 0x0C, 0x00, 0x7E,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x1B, 0x1B, 0x18, 0x18, 0x18,
0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x18, 0x18, 0x18, 0x18, 0xD8, 0xD8, 0xD8, 0x70, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x7E, 0x00, 0x18, 0x18, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x76, 0xDC, 0x00,
0x76, 0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x6C, 0x6C,
0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0C, 0x0C,
0x0C, 0x0C, 0x0C, 0xEC, 0x6C, 0x6C, 0x3C, 0x1C, 0x00, 0x00, 0x00, 0x00,
0x00, 0xD8, 0x6C, 0x6C, 0x6C, 0x6C, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0xD8, 0x30, 0x60, 0xC8, 0xF8, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x7C, 0x7C, 0x7C, 0x7C, 0x7C, 0x7C, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00};
#endif

82
lib/firmware/include/lcd.h
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@ -1,82 +0,0 @@
/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _LCD_H_
#define _LCD_H_
#include <stdint.h>
/* clang-format off */
#define LCD_X_MAX (240)
#define LCD_Y_MAX (320)
#define BLACK 0x0000
#define NAVY 0x000F
#define DARKGREEN 0x03E0
#define DARKCYAN 0x03EF
#define MAROON 0x7800
#define PURPLE 0x780F
#define OLIVE 0x7BE0
#define LIGHTGREY 0xC618
#define DARKGREY 0x7BEF
#define BLUE 0x001F
#define GREEN 0x07E0
#define CYAN 0x07FF
#define RED 0xF800
#define MAGENTA 0xF81F
#define YELLOW 0xFFE0
#define WHITE 0xFFFF
#define ORANGE 0xFD20
#define GREENYELLOW 0xAFE5
#define PINK 0xF81F
#define USER_COLOR 0xAA55
/* clang-format on */
typedef enum _lcd_dir
{
DIR_XY_RLUD = 0x00,
DIR_YX_RLUD = 0x20,
DIR_XY_LRUD = 0x40,
DIR_YX_LRUD = 0x60,
DIR_XY_RLDU = 0x80,
DIR_YX_RLDU = 0xA0,
DIR_XY_LRDU = 0xC0,
DIR_YX_LRDU = 0xE0,
DIR_XY_MASK = 0x20,
DIR_MASK = 0xE0,
} lcd_dir_t;
typedef struct _lcd_ctl
{
uint8_t mode;
uint8_t dir;
uint16_t width;
uint16_t height;
} lcd_ctl_t;
int lcd_busy(void);
void lcd_polling_enable(void);
void lcd_interrupt_enable(void);
void lcd_init(void);
void lcd_clear(uint16_t color);
void lcd_set_direction(lcd_dir_t dir);
void lcd_set_area(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
void lcd_draw_point(uint16_t x, uint16_t y, uint16_t color);
void lcd_draw_string(uint16_t x, uint16_t y, char *str, uint16_t color);
void lcd_draw_picture(uint16_t x1, uint16_t y1, uint16_t width, uint16_t height, uint32_t *ptr);
void lcd_draw_rectangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t width, uint16_t color);
void lcd_ram_draw_string(char *str, uint32_t *ptr, uint16_t font_color, uint16_t bg_color);
#endif

115
lib/firmware/include/nt35310.h
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@ -1,115 +0,0 @@
/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _NT35310_H_
#define _NT35310_H_
#include <stdint.h>
/* clang-format off */
#define NO_OPERATION 0x00
#define SOFTWARE_RESET 0x01
#define READ_ID 0x04
#define READ_STATUS 0x09
#define READ_POWER_MODE 0x0A
#define READ_MADCTL 0x0B
#define READ_PIXEL_FORMAT 0x0C
#define READ_IMAGE_FORMAT 0x0D
#define READ_SIGNAL_MODE 0x0E
#define READ_SELT_DIAG_RESULT 0x0F
#define SLEEP_ON 0x10
#define SLEEP_OFF 0x11
#define PARTIAL_DISPALY_ON 0x12
#define NORMAL_DISPALY_ON 0x13
#define INVERSION_DISPALY_OFF 0x20
#define INVERSION_DISPALY_ON 0x21
#define GAMMA_SET 0x26
#define DISPALY_OFF 0x28
#define DISPALY_ON 0x29
#define HORIZONTAL_ADDRESS_SET 0x2A
#define VERTICAL_ADDRESS_SET 0x2B
#define MEMORY_WRITE 0x2C
#define COLOR_SET 0x2D
#define MEMORY_READ 0x2E
#define PARTIAL_AREA 0x30
#define VERTICAL_SCROL_DEFINE 0x33
#define TEAR_EFFECT_LINE_OFF 0x34
#define TEAR_EFFECT_LINE_ON 0x35
#define MEMORY_ACCESS_CTL 0x36
#define VERTICAL_SCROL_S_ADD 0x37
#define IDLE_MODE_OFF 0x38
#define IDLE_MODE_ON 0x39
#define PIXEL_FORMAT_SET 0x3A
#define WRITE_MEMORY_CONTINUE 0x3C
#define READ_MEMORY_CONTINUE 0x3E
#define SET_TEAR_SCANLINE 0x44
#define GET_SCANLINE 0x45
#define WRITE_BRIGHTNESS 0x51
#define READ_BRIGHTNESS 0x52
#define WRITE_CTRL_DISPALY 0x53
#define READ_CTRL_DISPALY 0x54
#define WRITE_BRIGHTNESS_CTL 0x55
#define READ_BRIGHTNESS_CTL 0x56
#define WRITE_MIN_BRIGHTNESS 0x5E
#define READ_MIN_BRIGHTNESS 0x5F
#define READ_ID1 0xDA
#define READ_ID2 0xDB
#define READ_ID3 0xDC
#define RGB_IF_SIGNAL_CTL 0xB0
#define NORMAL_FRAME_CTL 0xB1
#define IDLE_FRAME_CTL 0xB2
#define PARTIAL_FRAME_CTL 0xB3
#define INVERSION_CTL 0xB4
#define BLANK_PORCH_CTL 0xB5
#define DISPALY_FUNCTION_CTL 0xB6
#define ENTRY_MODE_SET 0xB7
#define BACKLIGHT_CTL1 0xB8
#define BACKLIGHT_CTL2 0xB9
#define BACKLIGHT_CTL3 0xBA
#define BACKLIGHT_CTL4 0xBB
#define BACKLIGHT_CTL5 0xBC
#define BACKLIGHT_CTL7 0xBE
#define BACKLIGHT_CTL8 0xBF
#define POWER_CTL1 0xC0
#define POWER_CTL2 0xC1
#define VCOM_CTL1 0xC5
#define VCOM_CTL2 0xC7
#define NV_MEMORY_WRITE 0xD0
#define NV_MEMORY_PROTECT_KEY 0xD1
#define NV_MEMORY_STATUS_READ 0xD2
#define READ_ID4 0xD3
#define POSITIVE_GAMMA_CORRECT 0xE0
#define NEGATIVE_GAMMA_CORRECT 0xE1
#define DIGITAL_GAMMA_CTL1 0xE2
#define DIGITAL_GAMMA_CTL2 0xE3
#define INTERFACE_CTL 0xF6
#define DCX_IO (8)
#define RESET_IO (30)
#define RESET_GPIONUM (3)
#define DCX_GPIONUM (2)
#define SPI_CHANNEL 0
#define SPI_SLAVE_SELECT 3
/* clang-format on */
void tft_hard_init(void);
void tft_write_command(uint8_t cmd);
void tft_write_byte(uint8_t *data_buf, uint32_t length);
void tft_write_half(uint16_t *data_buf, uint32_t length);
void tft_write_word(uint32_t *data_buf, uint32_t length, uint32_t flag);
void tft_fill_data(uint32_t *data_buf, uint32_t length);
#endif

26
lib/firmware/include/ov2640.h
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@ -1,26 +0,0 @@
/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _OV2640_H
#define _OV2640_H
#include <stdint.h>
#define OV2640_ADDR 0x60
int ov2640_init(void);
int ov2640_read_id(uint16_t *manuf_id, uint16_t *device_id);
#endif /* _OV2640_H */

43
lib/firmware/include/ov5640.h
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@ -1,43 +0,0 @@
/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _OV5640_H
#define _OV5640_H
#include <stdint.h>
#define OV5640_ID 0X5640
#define OV5640_ADDR 0X78
#define OV5640_CHIPIDH 0X300A
#define OV5640_CHIPIDL 0X300B
#define XSIZE 320
#define YSIZE 240
#define LCD_GRAM_ADDRESS 0x60020000
#define QQVGA_160_120 0
#define QCIF_176_144 1
#define QVGA_320_240 2
#define WQVGA_400_240 3
#define CIF_352_288 4
#define jpeg_buf_size (30*1024)
uint8_t ov5640_wr_reg(uint16_t reg, uint8_t data);
uint8_t ov5640_rd_reg(uint16_t reg);
uint8_t ov5640_init(void);
void ov5640_flash_lamp(uint8_t sw);
#endif

287
lib/firmware/include/ov5640cfg.h
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@ -1,287 +0,0 @@
/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _OV5640CFG_H
#define _OV5640CFG_H
#include "ov5640.h"
const uint16_t ov5640_init_reg_tbl[][2]=
{
/* 24MHz input clock, 24MHz PCLK */
0x3008, 0x42, /* software power down, bit[6] */
0x3103, 0x03, /* system clock from PLL, bit[1] */
0x3017, 0xff, /* FREX, Vsync, HREF, PCLK, D[9:6] output enable */
0x3018, 0xff, /* D[5:0], GPIO[1:0] output enable */
0x3034, 0x1a, /* MIPI 10-bit*/
0x3035, 0x41, /* PLL */
0x3036, 0x40, /* PLL */
0x3037, 0x13, /* PLL root divider, bit[4], PLL pre-divider, bit[3:0] */
0x3108, 0x01, /* PCLK root divider, bit[5:4], SCLK2x root divider, bit[3:2] */
/* SCLK root divider, bit[1:0] */
0x3630, 0x36,
0x3631, 0x0e,
0x3632, 0xe2,
0x3633, 0x12,
0x3621, 0xe0,
0x3704, 0xa0,
0x3703, 0x5a,
0x3715, 0x78,
0x3717, 0x01,
0x370b, 0x60,
0x3705, 0x1a,
0x3905, 0x02,
0x3906, 0x10,
0x3901, 0x0a,
0x3731, 0x12,
0x3600, 0x08, /* VCM control */
0x3601, 0x33, /* VCM control */
0x302d, 0x60, /* system control */
0x3620, 0x52,
0x371b, 0x20,
0x471c, 0x50,
0x3a13, 0x43, /* pre-gain = 1.047x */
0x3a18, 0x00, /* gain ceiling */
0x3a19, 0xf8, /* gain ceiling = 15.5x */
0x3635, 0x13,
0x3636, 0x03,
0x3634, 0x40,
0x3622, 0x01,
/* 50/60Hz detection 50/60Hz */
0x3c01, 0x34, /* Band auto, bit[7] */
0x3c04, 0x28, /* threshold low sum */
0x3c05, 0x98, /* threshold high sum */
0x3c06, 0x00, /* light meter 1 threshold[15:8] */
0x3c07, 0x07, /* light meter 1 threshold[7:0] */
0x3c08, 0x00, /* light meter 2 threshold[15:8] */
0x3c09, 0x1c, /* light meter 2 threshold[7:0] */
0x3c0a, 0x9c, /* sample number[15:8] */
0x3c0b, 0x40, /* sample number[7:0] */
0x3810, 0x00, /* Timing Hoffset[11:8] */
0x3811, 0x10, /* Timing Hoffset[7:0] */
0x3812, 0x00, /* Timing Voffset[10:8] */
0x3708, 0x64,
0x4001, 0x02, /* BLC start from line 2 */
0x4005, 0x1a, /* BLC always update */
0x3000, 0x00, /* enable blocks */
0x3004, 0xff, /* enable clocks */
0x300e, 0x58, /* MIPI power down, DVP enable */
0x302e, 0x00,
0x4300, 0x61,
0X501F, 0x01,
0x3820, 0x46, /* flip */
0x3821, 0x00, /* mirror */
0x3800, 0x00, /* HS */
0x3801, 0x00, /* HS */
0x3802, 0x00, /* VS */
0x3803, 0x00, /* VS */
0x3804, 0x0a, /* HW (HE) */
0x3805, 0x3f, /* HW (HE) */
0x3806, 0x06, /* VH (VE) */
0x3807, 0xa9, /* VH (VE) */
0x3814, 0x31, /* timing X inc */
0x3815, 0x31, /* timing Y inc */
0x3808, 0x01, /* DVPHO */
0x3809, 0x40, /* DVPHO */
0x380a, 0x00, /* DVPVO */
0x380b, 0xF0, /* DVPVO */
0x380c, 0x05, /* HTS */
0x380d, 0xF8, /* HTS */
0x380e, 0x03, /* VTS */
0x380f, 0x84, /* VTS */
0x3810, 0x00, /* HTS */
0x3811, 0x00, /* HTS */
0x3812, 0x00, /* VTS */
0x3813, 0x00, /* VTS */
0x3618, 0x00,
0x3612, 0x29,
0x3709, 0x52,
0x370c, 0x03,
0x3a02, 0x02, /* 60Hz max exposure */
0x3a03, 0xe0, /* 60Hz max exposure */
0x3a14, 0x02, /* 50Hz max exposure */
0x3a15, 0xe0, /* 50Hz max exposure */
0x4004, 0x02, /* BLC line number */
0x3002, 0x1c, /* reset JFIFO, SFIFO, JPG */
0x3006, 0xc3, /* disable clock of JPEG2x, JPEG */
0x4713, 0x03, /* JPEG mode 3 */
0x4407, 0x04, /* Quantization scale */
0x460b, 0x37,
0x460c, 0x20,
0x4837, 0x16, /* MIPI global timing */
0x3824, 0x04, /* PCLK manual divider */
0x5001, 0xA3, /* SDE on, scale on, UV average off, color matrix on, AWB on */
0x3503, 0x00, /* AEC/AGC on */
0x440e, 0x00,
0x5000, 0xa7, /* Lenc on, raw gamma on, BPC on, WPC on, CIP on */
/* AEC target*/
0x3a0f, 0x30, /* stable range in high */
0x3a10, 0x28, /* stable range in low */
0x3a1b, 0x30, /* stable range out high */
0x3a1e, 0x26, /* stable range out low */
0x3a11, 0x60, /* fast zone high */
0x3a1f, 0x14, /* fast zone low */
/* Lens correction for */
0x5800, 0x23,
0x5801, 0x14,
0x5802, 0x0f,
0x5803, 0x0f,
0x5804, 0x12,
0x5805, 0x26,
0x5806, 0x0c,
0x5807, 0x08,
0x5808, 0x05,
0x5809, 0x05,
0x580a, 0x08,
0x580b, 0x0d,
0x580c, 0x08,
0x580d, 0x03,
0x580e, 0x00,
0x580f, 0x00,
0x5810, 0x03,
0x5811, 0x09,
0x5812, 0x07,
0x5813, 0x03,
0x5814, 0x00,
0x5815, 0x01,
0x5816, 0x03,
0x5817, 0x08,
0x5818, 0x0d,
0x5819, 0x08,
0x581a, 0x05,
0x581b, 0x06,
0x581c, 0x08,
0x581d, 0x0e,
0x581e, 0x29,
0x581f, 0x17,
0x5820, 0x11,
0x5821, 0x11,
0x5822, 0x15,
0x5823, 0x28,
0x5824, 0x46,
0x5825, 0x26,
0x5826, 0x08,
0x5827, 0x26,
0x5828, 0x64,
0x5829, 0x26,
0x582a, 0x24,
0x582b, 0x22,
0x582c, 0x24,
0x582d, 0x24,
0x582e, 0x06,
0x582f, 0x22,
0x5830, 0x40,
0x5831, 0x42,
0x5832, 0x24,
0x5833, 0x26,
0x5834, 0x24,
0x5835, 0x22,
0x5836, 0x22,
0x5837, 0x26,
0x5838, 0x44,
0x5839, 0x24,
0x583a, 0x26,
0x583b, 0x28,
0x583c, 0x42,
0x583d, 0xce, /* lenc BR offset */
/* AWB */
0x5180, 0xff, /* AWB B block */
0x5181, 0xf2, /* AWB control */
0x5182, 0x00, /* [7:4] max local counter, [3:0] max fast counter */
0x5183, 0x14, /* AWB advanced */
0x5184, 0x25,
0x5185, 0x24,
0x5186, 0x09,
0x5187, 0x09,
0x5188, 0x09,
0x5189, 0x75,
0x518a, 0x54,
0x518b, 0xe0,
0x518c, 0xb2,
0x518d, 0x42,
0x518e, 0x3d,
0x518f, 0x56,
0x5190, 0x46,
0x5191, 0xf8, /* AWB top limit */
0x5192, 0x04, /* AWB bottom limit */
0x5193, 0x70, /* red limit */
0x5194, 0xf0, /* green limit */
0x5195, 0xf0, /* blue limit */
0x5196, 0x03, /* AWB control*/
0x5197, 0x01, /* local limit */
0x5198, 0x04,
0x5199, 0x12,
0x519a, 0x04,
0x519b, 0x00,
0x519c, 0x06,
0x519d, 0x82,
0x519e, 0x38, /* AWB control */
/* Gamma */
0x5480, 0x01, /* Gamma bias plus on, bit[0] */
0x5481, 0x08,
0x5482, 0x14,
0x5483, 0x28,
0x5484, 0x51,
0x5485, 0x65,
0x5486, 0x71,
0x5487, 0x7d,
0x5488, 0x87,
0x5489, 0x91,
0x548a, 0x9a,
0x548b, 0xaa,
0x548c, 0xb8,
0x548d, 0xcd,
0x548e, 0xdd,
0x548f, 0xea,
0x5490, 0x1d,
/* color matrix */
0x5381, 0x1e, /* CMX1 for Y */
0x5382, 0x5b, /* CMX2 for Y */
0x5383, 0x08, /* CMX3 for Y */
0x5384, 0x0a, /* CMX4 for U */
0x5385, 0x7e, /* CMX5 for U */
0x5386, 0x88, /* CMX6 for U */
0x5387, 0x7c, /* CMX7 for V */
0x5388, 0x6c, /* CMX8 for V */
0x5389, 0x10, /* CMX9 for V */
0x538a, 0x01, /* sign[9] */
0x538b, 0x98, /* sign[8:1] */
/* UV adjust UV */
0x5580, 0x06, /* saturation on, bit[1] */
0x5583, 0x40,
0x5584, 0x10,
0x5589, 0x10,
0x558a, 0x00,
0x558b, 0xf8,
0x501d, 0x40, /* enable manual offset of contrast */
/* CIP */
0x5300, 0x08, /* CIP sharpen MT threshold 1 */
0x5301, 0x30, /* CIP sharpen MT threshold 2 */
0x5302, 0x10, /* CIP sharpen MT offset 1 */
0x5303, 0x00, /* CIP sharpen MT offset 2 */
0x5304, 0x08, /* CIP DNS threshold 1 */
0x5305, 0x30, /* CIP DNS threshold 2 */
0x5306, 0x08, /* CIP DNS offset 1 */
0x5307, 0x16, /* CIP DNS offset 2 */
0x5309, 0x08, /* CIP sharpen TH threshold 1 */
0x530a, 0x30, /* CIP sharpen TH threshold 2 */
0x530b, 0x04, /* CIP sharpen TH offset 1 */
0x530c, 0x06, /* CIP sharpen TH offset 2 */
0x5025, 0x00,
0x3008, 0x02, /* wake up from standby, bit[6] */
0x4740, 0X21, /*VSYNC active HIGH */
};
#endif

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lib/firmware/include/sd3068.h
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/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _SD3068_H
#define _SD3068_H
#include <stdint.h>
#include "i2c.h"
#define SD3068_ADDR 0x32
#define SD3068_ADDR_LENTH 7
typedef struct _sd_time
{
uint32_t year:6;
uint32_t month:4;
uint32_t day:5;
uint32_t hour:5;
uint32_t min:6;
uint32_t sec:6;
} __attribute__((packed, aligned(4))) sd_time_t;
void sd3068_init(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width,i2c_bus_speed_mode_t bus_speed_mode);
int sd3068_write_enable(void);
int sd3068_write_disable(void);
int sd3068_set_time(sd_time_t time);
int sd3068_get_time(sd_time_t *time);
int sd3068_write_data(uint8_t addr, uint8_t *data_buf, uint8_t length);
int sd3068_read_data(uint8_t addr, uint8_t *data_buf, uint8_t length);
int sd3068_set_time_dma(sd_time_t time);
int sd3068_write_enable_dma(void);
int sd3068_get_time_dma(sd_time_t *time);
int sd3068_read_data_dma(uint8_t addr, uint8_t *data_buf, uint8_t length);
int sd3068_write_data_dma(uint8_t addr, uint8_t *data_buf, uint8_t length);
#endif

113
lib/firmware/include/w25qxx.h
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/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _W25QXX_H
#define _W25QXX_H
#include <stdint.h>
/* clang-format off */
#define DATALENGTH 8
#define SPI_SLAVE_SELECT (0x01)
#define w25qxx_FLASH_PAGE_SIZE 256
#define w25qxx_FLASH_SECTOR_SIZE 4096
#define w25qxx_FLASH_PAGE_NUM_PER_SECTOR 16
#define w25qxx_FLASH_CHIP_SIZE (16777216 UL)
#define WRITE_ENABLE 0x06
#define WRITE_DISABLE 0x04
#define READ_REG1 0x05
#define READ_REG2 0x35
#define READ_REG3 0x15
#define WRITE_REG1 0x01
#define WRITE_REG2 0x31
#define WRITE_REG3 0x11
#define READ_DATA 0x03
#define FAST_READ 0x0B
#define FAST_READ_DUAL_OUTPUT 0x3B
#define FAST_READ_QUAL_OUTPUT 0x6B
#define FAST_READ_DUAL_IO 0xBB
#define FAST_READ_QUAL_IO 0xEB
#define DUAL_READ_RESET 0xFFFF
#define QUAL_READ_RESET 0xFF
#define PAGE_PROGRAM 0x02
#define QUAD_PAGE_PROGRAM 0x32
#define SECTOR_ERASE 0x20
#define BLOCK_32K_ERASE 0x52
#define BLOCK_64K_ERASE 0xD8
#define CHIP_ERASE 0x60
#define READ_ID 0x90
#define ENABLE_QPI 0x38
#define EXIT_QPI 0xFF
#define ENABLE_RESET 0x66
#define RESET_DEVICE 0x99
#define REG1_BUSY_MASK 0x01
#define REG2_QUAL_MASK 0x02
#define LETOBE(x) ((x >> 24) | ((x & 0x00FF0000) >> 8) | ((x & 0x0000FF00) << 8) | (x << 24))
/* clang-format on */
/**
* @brief w25qxx operating status enumerate
*/
typedef enum _w25qxx_status
{
W25QXX_OK = 0,
W25QXX_BUSY,
W25QXX_ERROR,
} w25qxx_status_t;
/**
* @brief w25qxx read operating enumerate
*/
typedef enum _w25qxx_read
{
W25QXX_STANDARD = 0,
W25QXX_STANDARD_FAST,
W25QXX_DUAL,
W25QXX_DUAL_FAST,
W25QXX_QUAD,
W25QXX_QUAD_FAST,
} w25qxx_read_t;
w25qxx_status_t w25qxx_init(uint8_t spi_index, uint8_t spi_ss);
w25qxx_status_t w25qxx_is_busy(void);
w25qxx_status_t w25qxx_chip_erase(void);
w25qxx_status_t w25qxx_enable_quad_mode(void);
w25qxx_status_t w25qxx_disable_quad_mode(void);
w25qxx_status_t w25qxx_sector_erase(uint32_t addr);
w25qxx_status_t w25qxx_32k_block_erase(uint32_t addr);
w25qxx_status_t w25qxx_64k_block_erase(uint32_t addr);
w25qxx_status_t w25qxx_read_status_reg1(uint8_t *reg_data);
w25qxx_status_t w25qxx_read_status_reg2(uint8_t *reg_data);
w25qxx_status_t w25qxx_write_status_reg(uint8_t reg1_data, uint8_t reg2_data);
w25qxx_status_t w25qxx_read_id(uint8_t *manuf_id, uint8_t *device_id);
w25qxx_status_t w25qxx_write_data(uint32_t addr, uint8_t *data_buf, uint32_t length);
w25qxx_status_t w25qxx_write_data_direct(uint32_t addr, uint8_t *data_buf, uint32_t length);
w25qxx_status_t w25qxx_read_data(uint32_t addr, uint8_t *data_buf, uint32_t length, w25qxx_read_t mode);
w25qxx_status_t w25qxx_enable_xip_mode(void);
w25qxx_status_t w25qxx_disable_xip_mode(void);
w25qxx_status_t w25qxx_read_id_dma(uint8_t *manuf_id, uint8_t *device_id);
w25qxx_status_t w25qxx_sector_erase_dma(uint32_t addr);
w25qxx_status_t w25qxx_init_dma(uint8_t spi_index, uint8_t spi_ss);
w25qxx_status_t w25qxx_write_data_direct_dma(uint32_t addr, uint8_t *data_buf, uint32_t length);
w25qxx_status_t w25qxx_read_data_dma(uint32_t addr, uint8_t *data_buf, uint32_t length, w25qxx_read_t mode);
w25qxx_status_t w25qxx_is_busy_dma(void);
w25qxx_status_t w25qxx_enable_quad_mode_dma(void);
#endif

210
lib/firmware/lcd.c
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/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <string.h>
#include "lcd.h"
#include "nt35310.h"
#include "font.h"
#include "utils.h"
#include "sleep.h"
static lcd_ctl_t lcd_ctl;
void lcd_polling_enable(void)
{
lcd_ctl.mode = 0;
}
void lcd_interrupt_enable(void)
{
lcd_ctl.mode = 1;
}
void lcd_init(void)
{
uint8_t data = 0;
tft_hard_init();
/*soft reset*/
tft_write_command(SOFTWARE_RESET);
msleep(100);
/*exit sleep*/
tft_write_command(SLEEP_OFF);
msleep(100);
/*pixel format*/
tft_write_command(PIXEL_FORMAT_SET);
data = 0x55;
tft_write_byte(&data, 1);
lcd_set_direction(DIR_XY_RLUD);
/*display on*/
tft_write_command(DISPALY_ON);
lcd_polling_enable();
}
void lcd_set_direction(lcd_dir_t dir)
{
lcd_ctl.dir = dir;
if (dir & DIR_XY_MASK)
{
lcd_ctl.width = LCD_Y_MAX - 1;
lcd_ctl.height = LCD_X_MAX - 1;
}
else
{
lcd_ctl.width = LCD_X_MAX - 1;
lcd_ctl.height = LCD_Y_MAX - 1;
}
tft_write_command(MEMORY_ACCESS_CTL);
tft_write_byte((uint8_t *)&dir, 1);
}
void lcd_set_area(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
{
uint8_t data[4] = {0};
data[0] = (uint8_t)(x1 >> 8);
data[1] = (uint8_t)(x1);
data[2] = (uint8_t)(x2 >> 8);
data[3] = (uint8_t)(x2);
tft_write_command(HORIZONTAL_ADDRESS_SET);
tft_write_byte(data, 4);
data[0] = (uint8_t)(y1 >> 8);
data[1] = (uint8_t)(y1);
data[2] = (uint8_t)(y2 >> 8);
data[3] = (uint8_t)(y2);
tft_write_command(VERTICAL_ADDRESS_SET);
tft_write_byte(data, 4);
tft_write_command(MEMORY_WRITE);
}
void lcd_draw_point(uint16_t x, uint16_t y, uint16_t color)
{
lcd_set_area(x, y, x, y);
tft_write_half(&color, 1);
}
void lcd_draw_char(uint16_t x, uint16_t y, char c, uint16_t color)
{
uint8_t i = 0;
uint8_t j = 0;
uint8_t data = 0;
for (i = 0; i < 16; i++)
{
data = ascii0816[c * 16 + i];
for (j = 0; j < 8; j++)
{
if (data & 0x80)
lcd_draw_point(x + j, y, color);
data <<= 1;
}
y++;
}
}
void lcd_draw_string(uint16_t x, uint16_t y, char *str, uint16_t color)
{
while (*str)
{
lcd_draw_char(x, y, *str, color);
str++;
x += 8;
}
}
void lcd_ram_draw_string(char *str, uint32_t *ptr, uint16_t font_color, uint16_t bg_color)
{
uint8_t i = 0;
uint8_t j = 0;
uint8_t data = 0;
uint8_t *pdata = NULL;
uint16_t width = 0;
uint32_t *pixel = NULL;
width = 4 * strlen(str);
while (*str)
{
pdata = (uint8_t *)&ascii0816[(*str) * 16];
for (i = 0; i < 16; i++)
{
data = *pdata++;
pixel = ptr + i * width;
for (j = 0; j < 4; j++)
{
switch (data >> 6)
{
case 0:
*pixel = ((uint32_t)bg_color << 16) | bg_color;
break;
case 1:
*pixel = ((uint32_t)bg_color << 16) | font_color;
break;
case 2:
*pixel = ((uint32_t)font_color << 16) | bg_color;
break;
case 3:
*pixel = ((uint32_t)font_color << 16) | font_color;
break;
default:
*pixel = 0;
break;
}
data <<= 2;
pixel++;
}
}
str++;
ptr += 4;
}
}
void lcd_clear(uint16_t color)
{
uint32_t data = ((uint32_t)color << 16) | (uint32_t)color;
lcd_set_area(0, 0, lcd_ctl.width, lcd_ctl.height);
tft_fill_data(&data, LCD_X_MAX * LCD_Y_MAX / 2);
}
void lcd_draw_rectangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t width, uint16_t color)
{
uint32_t data_buf[640] = {0};
uint32_t *p = data_buf;
uint32_t data = color;
uint32_t index = 0;
data = (data << 16) | data;
for (index = 0; index < 160 * width; index++)
*p++ = data;
lcd_set_area(x1, y1, x2, y1 + width - 1);
tft_write_word(data_buf, ((x2 - x1 + 1) * width + 1) / 2, 0);
lcd_set_area(x1, y2 - width + 1, x2, y2);
tft_write_word(data_buf, ((x2 - x1 + 1) * width + 1) / 2, 0);
lcd_set_area(x1, y1, x1 + width - 1, y2);
tft_write_word(data_buf, ((y2 - y1 + 1) * width + 1) / 2, 0);
lcd_set_area(x2 - width + 1, y1, x2, y2);
tft_write_word(data_buf, ((y2 - y1 + 1) * width + 1) / 2, 0);
}
void lcd_draw_picture(uint16_t x1, uint16_t y1, uint16_t width, uint16_t height, uint32_t *ptr)
{
lcd_set_area(x1, y1, x1 + width - 1, y1 + height - 1);
tft_write_word(ptr, width * height / 2, lcd_ctl.mode ? 2 : 0);
}

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lib/firmware/nt35310.c
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/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "nt35310.h"
#include "sysctl.h"
#include "fpioa.h"
#include "gpiohs.h"
#include "spi.h"
#include "dmac.h"
#include "plic.h"
#include <utils.h>
#define __SPI_SYSCTL(x, y) SYSCTL_##x##_SPI##y
#define _SPI_SYSCTL(x, y) __SPI_SYSCTL(x, y)
#define SPI_SYSCTL(x) _SPI_SYSCTL(x, SPI_CHANNEL)
#define __SPI_SS(x, y) FUNC_SPI##x##_SS##y
#define _SPI_SS(x, y) __SPI_SS(x, y)
#define SPI_SS _SPI_SS(SPI_CHANNEL, SPI_SLAVE_SELECT)
#define __SPI(x, y) FUNC_SPI##x##_##y
#define _SPI(x, y) __SPI(x, y)
#define SPI(x) _SPI(SPI_CHANNEL, x)
#define TEST2_0
void init_dcx(void)
{
fpioa_set_function(DCX_IO, FUNC_GPIOHS0 + DCX_GPIONUM);/*dcx*/
gpiohs_set_drive_mode(DCX_GPIONUM, GPIO_DM_OUTPUT);
gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_HIGH);
#ifndef TEST2_0
fpioa_set_function(RESET_IO, FUNC_GPIOHS0 + RESET_GPIONUM);/*reset*/
gpiohs_set_drive_mode(RESET_GPIONUM, GPIO_DM_OUTPUT);
gpiohs_set_pin(RESET_GPIONUM, GPIO_PV_HIGH);
#endif
}
void set_dcx_control(void)
{
gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_LOW);
}
void set_dcx_data(void)
{
gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_HIGH);
}
void pin_mux_init(void)
{
#ifndef TEST2_0
fpioa_set_function(31, SPI_SS);
fpioa_set_function(32, SPI(SCLK));
#else
fpioa_set_function(6, SPI_SS);
fpioa_set_function(7, SPI(SCLK));
#endif
sysctl_spi0_dvp_data_set(1);
}
void tft_hard_init(void)
{
init_dcx();
pin_mux_init();
spi_init(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 8);
}
void tft_write_command(uint8_t cmd)
{
set_dcx_control();
spi_init(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 8);
spi_init_non_standard(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/);
spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT, (uint8_t *)(&cmd), 1,SPI_TRANS_CHAR);
}
void tft_write_byte(uint8_t *data_buf, uint32_t length)
{
set_dcx_data();
spi_init(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 8);
spi_init_non_standard(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/);
spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT, data_buf, length, SPI_TRANS_CHAR);
}
void tft_write_half(uint16_t *data_buf, uint32_t length)
{
set_dcx_data();
spi_init(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 16);
spi_init_non_standard(SPI_CHANNEL, 16/*instrction length*/, 0/*address length*/, 0/*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/);
spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_SHORT);
}
void tft_write_word(uint32_t *data_buf, uint32_t length, uint32_t flag)
{
set_dcx_data();
spi_init(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 32);
spi_init_non_standard(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/);
spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_INT);
}
void tft_fill_data(uint32_t *data_buf, uint32_t length)
{
set_dcx_data();
spi_init(SPI_CHANNEL, SPI_WORK_MODE_2, SPI_FF_OCTAL, 32);
spi_init_non_standard(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/);
spi_fill_data_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT,data_buf, length);
}

243
lib/firmware/ov2640.c
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@ -1,243 +0,0 @@
/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdio.h>
#include "ov2640.h"
#include "dvp.h"
#include "plic.h"
/* QVGA Window Size */
static const uint8_t ov2640_config[][2] =
{
{0xff, 0x00},
{0x2c, 0xff},
{0x2e, 0xdf},
{0xff, 0x01},
{0x3c, 0x32},
{0x11, 0x00},
{0x09, 0x00},
{0x04, 0x28},
{0x13, 0xe5},
{0x14, 0xa8},
{0x15, 0x00},
{0x2c, 0x0c},
{0x33, 0x78},
{0x3a, 0x33},
{0x3b, 0xfb},
{0x3e, 0x00},
{0x43, 0x11},
{0x16, 0x10},
{0x39, 0x92},
{0x35, 0xda},
{0x22, 0x1a},
{0x23, 0x00},
{0x34, 0xc0},
{0x06, 0x88},
{0x07, 0xc0},
{0x0d, 0x87},
{0x0e, 0x41},
{0x4c, 0x00},
{0x48, 0x00},
{0x5b, 0x00},
{0x42, 0x03},
{0x4a, 0x81},
{0x21, 0x99},
{0x24, 0x40},
{0x25, 0x38},
{0x26, 0x82},
{0x5c, 0x00},
{0x63, 0x00},
{0x61, 0x70},
{0x62, 0x80},
{0x7c, 0x05},
{0x20, 0x80},
{0x28, 0x30},
{0x6c, 0x00},
{0x6d, 0x80},
{0x6e, 0x00},
{0x70, 0x02},
{0x71, 0x94},
{0x73, 0xc1},
{0x0c, 0x3c},
{0x5d, 0x55},
{0x5e, 0x7d},
{0x5f, 0x7d},
{0x60, 0x55},
{0x12, 0x40},
{0x32, 0xC9},
{0x17, 0x11},
{0x18, 0x43},
{0x19, 0x00},
{0x1a, 0x97},
{0x32, 0x09},
{0x37, 0x42},
{0x4f, 0xbb},
{0x50, 0x9c},
{0x6d, 0x80},
{0x35, 0x88},
{0x22, 0x0a},
{0x6d, 0x80},
{0x3d, 0xe1},
{0xff, 0x00},
{0xe5, 0x7f},
{0xf9, 0xc0},
{0x41, 0x24},
{0x44, 0x06},
{0xe0, 0x14},
{0x76, 0xff},
{0x33, 0xa0},
{0x42, 0x20},
{0x43, 0x18},
{0x4c, 0x00},
{0x87, 0xd0},
{0x88, 0x3f},
{0xd7, 0x03},
{0xd9, 0x10},
{0xd3, 0x82},
{0xc8, 0x08},
{0xc9, 0x80},
{0x7c, 0x00},
{0x7d, 0x00},
{0x7c, 0x03},
{0x7d, 0x48},
{0x7d, 0x48},
{0x7c, 0x08},
{0x7d, 0x20},
{0x7d, 0x10},
{0x7d, 0x0e},
{0x90, 0x00},
{0x91, 0x0e},
{0x91, 0x1a},
{0x91, 0x31},
{0x91, 0x5a},
{0x91, 0x69},
{0x91, 0x75},
{0x91, 0x7e},
{0x91, 0x88},
{0x91, 0x8f},
{0x91, 0x96},
{0x91, 0xa3},
{0x91, 0xaf},
{0x91, 0xc4},
{0x91, 0xd7},
{0x91, 0xe8},
{0x91, 0x20},
{0x92, 0x00},
{0x93, 0x06},
{0x93, 0xe3},
{0x93, 0x03},
{0x93, 0x03},
{0x93, 0x00},
{0x93, 0x02},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x96, 0x00},
{0x97, 0x08},
{0x97, 0x19},
{0x97, 0x02},
{0x97, 0x0c},
{0x97, 0x24},
{0x97, 0x30},
{0x97, 0x28},
{0x97, 0x26},
{0x97, 0x02},
{0x97, 0x98},
{0x97, 0x80},
{0x97, 0x00},
{0x97, 0x00},
{0xa4, 0x00},
{0xa8, 0x00},
{0xc5, 0x11},
{0xc6, 0x51},
{0xbf, 0x80},
{0xc7, 0x10},
{0xb6, 0x66},
{0xb8, 0xa5},
{0xb7, 0x64},
{0xb9, 0x7c},
{0xb3, 0xaf},
{0xb4, 0x97},
{0xb5, 0xff},
{0xb0, 0xc5},
{0xb1, 0x94},
{0xb2, 0x0f},
{0xc4, 0x5c},
{0xa6, 0x00},
{0xa7, 0x20},
{0xa7, 0xd8},
{0xa7, 0x1b},
{0xa7, 0x31},
{0xa7, 0x00},
{0xa7, 0x18},
{0xa7, 0x20},
{0xa7, 0xd8},
{0xa7, 0x19},
{0xa7, 0x31},
{0xa7, 0x00},
{0xa7, 0x18},
{0xa7, 0x20},
{0xa7, 0xd8},
{0xa7, 0x19},
{0xa7, 0x31},
{0xa7, 0x00},
{0xa7, 0x18},
{0xe0, 0x04},
{0xc0, 0x64},
{0xc1, 0x4b},
{0x86, 0x3d},
{0x50, 0x80},
{0x51, 0xc8},
{0x52, 0x96},
{0x53, 0x00},
{0x54, 0x00},
{0x55, 0x00},
{0x57, 0x00},
{0x5a, 0x50},
{0x5b, 0x3c},
{0x5c, 0x00},
{0xd3, 0x04},
{0xe0, 0x00},
{0xc3, 0xef},
{0x7f, 0x00},
{0xda, 0x08},
{0xe5, 0x1f},
{0xe1, 0x67},
{0xdd, 0x7f},
{0x05, 0x00},
{0x98, 0x00},
{0x99, 0x00},
{0x00, 0x00},
};
int ov2640_init(void)
{
uint16_t index = 0;
for (index = 0; ov2640_config[index][0]; index++)
dvp_sccb_send_data(OV2640_ADDR, ov2640_config[index][0], ov2640_config[index][1]);
return 0;
}
int ov2640_read_id(uint16_t *manuf_id, uint16_t *device_id)
{
dvp_sccb_send_data(OV2640_ADDR, 0xFF, 0x01);
*manuf_id = (dvp_sccb_receive_data(OV2640_ADDR, 0x1C) << 8) | dvp_sccb_receive_data(OV2640_ADDR, 0x1D);
*device_id = (dvp_sccb_receive_data(OV2640_ADDR, 0x0A) << 8) | dvp_sccb_receive_data(OV2640_ADDR, 0x0B);
return 0;
}

82
lib/firmware/ov5640.c
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/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ov5640.h"
#include "ov5640cfg.h"
#include <stdio.h>
#include "ov2640.h"
#include "dvp.h"
#include "plic.h"
extern void mdelay(uint32_t ms);
void hal_delay(uint32_t delay)
{
mdelay(delay);
}
uint8_t ov5640_wr_reg(uint16_t reg,uint8_t data)
{
dvp_sccb_send_data(OV5640_ADDR, reg, data);
return 0;
}
uint8_t ov5640_rd_reg(uint16_t reg)
{
return dvp_sccb_receive_data(OV5640_ADDR, reg);
}
uint8_t ov5640_init(void)
{
uint16_t i = 0;
uint16_t reg = 0;
reg = ov5640_rd_reg(OV5640_CHIPIDH);
reg <<= 8;
reg |= ov5640_rd_reg(OV5640_CHIPIDL);
printf("ID: %X \r\n", reg);
if(reg != OV5640_ID)
{
printf("ID: %d \r\n", reg);
return 1;
}
ov5640_wr_reg(0x3103,0X11); /*system clock from pad, bit[1]*/
ov5640_wr_reg(0X3008,0X82);
hal_delay(10);
for(i = 0; i<sizeof(ov5640_init_reg_tbl) / 4; i++)
{
ov5640_wr_reg(ov5640_init_reg_tbl[i][0], ov5640_init_reg_tbl[i][1]);
}
hal_delay(50);
/* Test for flash light*/
ov5640_flash_lamp(1);
hal_delay(50);
ov5640_flash_lamp(0);
return 0x00;
}
void ov5640_flash_lamp(uint8_t sw)
{
ov5640_wr_reg(0x3016, 0X02);
ov5640_wr_reg(0x301C, 0X02);
if(sw)
ov5640_wr_reg(0X3019, 0X02);
else
ov5640_wr_reg(0X3019, 0X00);
}

206
lib/firmware/sd3068.c
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/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdio.h>
#include "sd3068.h"
#include "fpioa.h"
#include "utils.h"
#include "sysctl.h"
#include <stdlib.h>
#include <string.h>
uint32_t i2c_bus_no = 0;
void sd3068_init(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width,i2c_bus_speed_mode_t bus_speed_mode)
{
i2c_bus_no = i2c_num;
i2c_init(i2c_num, slave_address, address_width, bus_speed_mode);
}
static int sd3068_write_reg(uint8_t reg, uint8_t *data_buf, uint8_t length)
{
uint8_t *buf = malloc(length + 1);
buf[0] = reg;
memcpy(buf + 1, data_buf, length);
i2c_send_data(i2c_bus_no, buf, length + 1);
free(buf);
return 0;
}
static int sd3068_write_reg_dma(uint8_t reg, uint8_t *data_buf, uint8_t length)
{
uint8_t *buf = malloc(length + 1);
buf[0] = reg;
memcpy(buf + 1, data_buf, length);
i2c_send_data_dma(DMAC_CHANNEL0, i2c_bus_no, buf, length + 1);
free(buf);
return 0;
}
static int sd3068_read_reg(uint8_t reg, uint8_t *data_buf, uint8_t length)
{
i2c_recv_data(i2c_bus_no, &reg, 1, data_buf, length);
return 0;
}
static int sd3068_read_reg_dma(uint8_t reg, uint8_t *data_buf, uint8_t length)
{
i2c_recv_data_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, i2c_bus_no, &reg, 1, data_buf, length);
return 0;
}
static uint8_t hex2bcd(uint8_t data)
{
return data / 10 * 16 + data % 10;
}
static uint8_t bcd2hex(uint8_t data)
{
return data / 16 * 10 + data % 16;
}
int sd3068_write_enable(void)
{
uint8_t data[2] = {0};
data[0] = 0xFF;
data[1] = 0x80;
sd3068_write_reg(0x10, &data[1], 1);
sd3068_write_reg(0x0F, &data[0], 1);
return 0;
}
int sd3068_write_enable_dma(void)
{
uint8_t data[2] = {0};
data[0] = 0xFF;
data[1] = 0x80;
sd3068_write_reg_dma(0x10, &data[1], 1);
sd3068_write_reg_dma(0x0F, &data[0], 1);
return 0;
}
int sd3068_write_disable(void)
{
uint8_t data[2] = {0};
data[0] = 0x7B;
data[1] = 0;
sd3068_write_reg(0x0F, data, 2);
return 0;
}
int sd3068_write_data(uint8_t addr, uint8_t *data_buf, uint8_t length)
{
addr = ((addr <= 69) ? addr : 69);
length = ((length <= 70 - addr) ? length : 70 - addr);
sd3068_write_reg(0x2C + addr, data_buf, length);
return 0;
}
int sd3068_write_data_dma(uint8_t addr, uint8_t *data_buf, uint8_t length)
{
addr = ((addr <= 69) ? addr : 69);
length = ((length <= 70 - addr) ? length : 70 - addr);
sd3068_write_reg_dma(0x2C + addr, data_buf, length);
return 0;
}
int sd3068_read_data(uint8_t addr, uint8_t *data_buf, uint8_t length)
{
addr = ((addr <= 69) ? addr : 69);
length = ((length <= 70 - addr) ? length : 70 - addr);
sd3068_read_reg(0x2C + addr, data_buf, length);
return 0;
}
int sd3068_read_data_dma(uint8_t addr, uint8_t *data_buf, uint8_t length)
{
addr = ((addr <= 69) ? addr : 69);
length = length <= 70 - addr ? length : 70 - addr;
sd3068_read_reg_dma(0x2C + addr, data_buf, length);
return 0;
}
int sd3068_set_time(sd_time_t time)
{
uint8_t data[7] = {0};
data[0] = hex2bcd(time.sec);
data[1] = hex2bcd(time.min);
data[2] = hex2bcd(time.hour) | 0x80;
data[3] = hex2bcd(5);
data[4] = hex2bcd(time.day);
data[5] = hex2bcd(time.month);
data[6] = hex2bcd(time.year);
sd3068_write_reg(0x00, data, 7);
return 0;
}
int sd3068_set_time_dma(sd_time_t time)
{
uint8_t data[7] = {0};
data[0] = hex2bcd(time.sec);
data[1] = hex2bcd(time.min);
data[2] = hex2bcd(time.hour) | 0x80;
data[3] = hex2bcd(5);
data[4] = hex2bcd(time.day);
data[5] = hex2bcd(time.month);
data[6] = hex2bcd(time.year);
sd3068_write_reg_dma(0x00, data, 7);
return 0;
}
int sd3068_get_time(sd_time_t *time)
{
uint8_t data[7] = {0};
sd3068_read_reg(0x00, data, 7);
time->sec = bcd2hex(data[0]);
time->min = bcd2hex(data[1]);
time->hour = bcd2hex(data[2] & 0x7F);
time->day = bcd2hex(data[4]);
time->month = bcd2hex(data[5]);
time->year = bcd2hex(data[6]);
return 0;
}
int sd3068_get_time_dma(sd_time_t *time)
{
uint8_t data[7] = {0};
sd3068_read_reg_dma(0x00, data, 7);
time->sec = bcd2hex(data[0]);
time->min = bcd2hex(data[1]);
time->hour = bcd2hex(data[2] & 0x7F);
time->day = bcd2hex(data[4]);
time->month = bcd2hex(data[5]);
time->year = bcd2hex(data[6]);
return 0;
}

654
lib/firmware/w25qxx.c
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/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "w25qxx.h"
#include "fpioa.h"
#include "spi.h"
#include "sysctl.h"
#include "dmac.h"
uint32_t spi_bus_no = 0;
uint32_t spi_chip_select = 0;
static volatile spi_t *spi_handle;
w25qxx_status_t (*w25qxx_page_program_fun)(uint32_t addr, uint8_t *data_buf, uint32_t length);
w25qxx_status_t (*w25qxx_read_fun)(uint32_t addr, uint8_t *data_buf, uint32_t length);
static w25qxx_status_t w25qxx_stand_read_data(uint32_t addr, uint8_t *data_buf, uint32_t length);
static w25qxx_status_t w25qxx_quad_read_data(uint32_t addr, uint8_t *data_buf, uint32_t length);
static w25qxx_status_t w25qxx_page_program(uint32_t addr, uint8_t *data_buf, uint32_t length);
static w25qxx_status_t w25qxx_quad_page_program(uint32_t addr, uint8_t *data_buf, uint32_t length);
static w25qxx_status_t w25qxx_page_program_dma(uint32_t addr, uint8_t *data_buf, uint32_t length);
static w25qxx_status_t w25qxx_quad_page_program_dma(uint32_t addr, uint8_t *data_buf, uint32_t length);
static w25qxx_status_t w25qxx_receive_data(uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len)
{
spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH);
spi_receive_data_standard(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len);
return W25QXX_OK;
}
static w25qxx_status_t w25qxx_receive_data_dma(uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len)
{
spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH);
spi_receive_data_standard_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len);
return W25QXX_OK;
}
static w25qxx_status_t w25qxx_send_data(uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len)
{
spi_send_data_standard(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len);
return W25QXX_OK;
}
static w25qxx_status_t w25qxx_send_data_dma(uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len)
{
spi_send_data_standard_dma(DMAC_CHANNEL0, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len);
return W25QXX_OK;
}
static w25qxx_status_t w25qxx_receive_data_enhanced(uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len)
{
spi_receive_data_multiple(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len);
return W25QXX_OK;
}
static w25qxx_status_t w25qxx_receive_data_enhanced_dma(uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len)
{
spi_receive_data_multiple_dma(DMAC_CHANNEL0, DMAC_CHANNEL1, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, rx_buff, rx_len);
return W25QXX_OK;
}
static w25qxx_status_t w25qxx_send_data_enhanced(uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len)
{
spi_send_data_multiple(spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len);
return W25QXX_OK;
}
static w25qxx_status_t w25qxx_send_data_enhanced_dma(uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len)
{
spi_send_data_multiple_dma(DMAC_CHANNEL0, spi_bus_no, spi_chip_select, cmd_buff, cmd_len, tx_buff, tx_len);
return W25QXX_OK;
}
w25qxx_status_t w25qxx_init(uint8_t spi_index, uint8_t spi_ss)
{
spi_bus_no = spi_index;
spi_chip_select = spi_ss;
spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH);
w25qxx_page_program_fun = w25qxx_page_program;
w25qxx_read_fun = w25qxx_stand_read_data;
return W25QXX_OK;
}
w25qxx_status_t w25qxx_init_dma(uint8_t spi_index, uint8_t spi_ss)
{
spi_bus_no = spi_index;
spi_chip_select = spi_ss;
spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH);
w25qxx_page_program_fun = w25qxx_page_program_dma;
w25qxx_read_fun = w25qxx_stand_read_data;
return W25QXX_OK;
}
w25qxx_status_t w25qxx_read_id(uint8_t *manuf_id, uint8_t *device_id)
{
uint8_t cmd[4] = {READ_ID, 0x00, 0x00, 0x00};
uint8_t data[2] = {0};
w25qxx_receive_data(cmd, 4, data, 2);
*manuf_id = data[0];
*device_id = data[1];
return W25QXX_OK;
}
w25qxx_status_t w25qxx_read_id_dma(uint8_t *manuf_id, uint8_t *device_id)
{
uint8_t cmd[4] = {READ_ID, 0x00, 0x00, 0x00};
uint8_t data[2] = {0};
w25qxx_receive_data_dma(cmd, 4, data, 2);
*manuf_id = data[0];
*device_id = data[1];
return W25QXX_OK;
}
static w25qxx_status_t w25qxx_write_enable(void)
{
uint8_t cmd[1] = {WRITE_ENABLE};
w25qxx_send_data(cmd, 1, 0, 0);
return W25QXX_OK;
}
static w25qxx_status_t w25qxx_write_enable_dma(void)
{
uint8_t cmd[1] = {WRITE_ENABLE};
w25qxx_send_data_dma(cmd, 1, 0, 0);
return W25QXX_OK;
}
w25qxx_status_t w25qxx_write_status_reg(uint8_t reg1_data, uint8_t reg2_data)
{
uint8_t cmd[3] = {WRITE_REG1, reg1_data, reg2_data};
w25qxx_write_enable();
w25qxx_send_data(cmd, 3, 0, 0);
return W25QXX_OK;
}
w25qxx_status_t w25qxx_write_status_reg_dma(uint8_t reg1_data, uint8_t reg2_data)
{
uint8_t cmd[3] = {WRITE_REG1, reg1_data, reg2_data};
w25qxx_write_enable_dma();
w25qxx_send_data_dma(cmd, 3, 0, 0);
return W25QXX_OK;
}
w25qxx_status_t w25qxx_read_status_reg1(uint8_t *reg_data)
{
uint8_t cmd[1] = {READ_REG1};
uint8_t data[1] = {0};
w25qxx_receive_data(cmd, 1, data, 1);
*reg_data = data[0];
return W25QXX_OK;
}
w25qxx_status_t w25qxx_read_status_reg1_dma(uint8_t *reg_data)
{
uint8_t cmd[1] = {READ_REG1};
uint8_t data[1] = {0};
w25qxx_receive_data_dma(cmd, 1, data, 1);
*reg_data = data[0];
return W25QXX_OK;
}
w25qxx_status_t w25qxx_read_status_reg2(uint8_t *reg_data)
{
uint8_t cmd[1] = {READ_REG2};
uint8_t data[1] = {0};
w25qxx_receive_data(cmd, 1, data, 1);
*reg_data = data[0];
return W25QXX_OK;
}
w25qxx_status_t w25qxx_read_status_reg2_dma(uint8_t *reg_data)
{
uint8_t cmd[1] = {READ_REG2};
uint8_t data[1] = {0};
w25qxx_receive_data_dma(cmd, 1, data, 1);
*reg_data = data[0];
return W25QXX_OK;
}
w25qxx_status_t w25qxx_is_busy(void)
{
uint8_t status = 0;
w25qxx_read_status_reg1(&status);
if (status & REG1_BUSY_MASK)
return W25QXX_BUSY;
return W25QXX_OK;
}
w25qxx_status_t w25qxx_is_busy_dma(void)
{
uint8_t status = 0;
w25qxx_read_status_reg1_dma(&status);
if (status & REG1_BUSY_MASK)
return W25QXX_BUSY;
return W25QXX_OK;
}
w25qxx_status_t w25qxx_sector_erase(uint32_t addr)
{
uint8_t cmd[4] = {SECTOR_ERASE};
cmd[1] = (uint8_t)(addr >> 16);
cmd[2] = (uint8_t)(addr >> 8);
cmd[3] = (uint8_t)(addr);
w25qxx_write_enable();
w25qxx_send_data(cmd, 4, 0, 0);
return W25QXX_OK;
}
w25qxx_status_t w25qxx_sector_erase_dma(uint32_t addr)
{
uint8_t cmd[4] = {SECTOR_ERASE};
cmd[1] = (uint8_t)(addr >> 16);
cmd[2] = (uint8_t)(addr >> 8);
cmd[3] = (uint8_t)(addr);
w25qxx_write_enable_dma();
w25qxx_send_data_dma(cmd, 4, 0, 0);
return W25QXX_OK;
}
w25qxx_status_t w25qxx_32k_block_erase(uint32_t addr)
{
uint8_t cmd[4] = {BLOCK_32K_ERASE};
cmd[1] = (uint8_t)(addr >> 16);
cmd[2] = (uint8_t)(addr >> 8);
cmd[3] = (uint8_t)(addr);
w25qxx_write_enable();
w25qxx_send_data(cmd, 4, 0, 0);
return W25QXX_OK;
}
w25qxx_status_t w25qxx_64k_block_erase(uint32_t addr)
{
uint8_t cmd[4] = {BLOCK_64K_ERASE};
cmd[1] = (uint8_t)(addr >> 16);
cmd[2] = (uint8_t)(addr >> 8);
cmd[3] = (uint8_t)(addr);
w25qxx_write_enable();
w25qxx_send_data(cmd, 4, 0, 0);
return W25QXX_OK;
}
w25qxx_status_t w25qxx_chip_erase(void)
{
uint8_t cmd[1] = {CHIP_ERASE};
w25qxx_write_enable();
w25qxx_send_data(cmd, 1, 0, 0);
return W25QXX_OK;
}
w25qxx_status_t w25qxx_enable_quad_mode(void)
{
uint8_t reg_data = 0;
w25qxx_read_status_reg2(&reg_data);
if (!(reg_data & REG2_QUAL_MASK))
{
reg_data |= REG2_QUAL_MASK;
w25qxx_write_status_reg(0x00, reg_data);
}
w25qxx_page_program_fun = w25qxx_quad_page_program;
w25qxx_read_fun = w25qxx_quad_read_data;
return W25QXX_OK;
}
w25qxx_status_t w25qxx_enable_quad_mode_dma(void)
{
uint8_t reg_data = 0;
w25qxx_read_status_reg2_dma(&reg_data);
if (!(reg_data & REG2_QUAL_MASK))
{
reg_data |= REG2_QUAL_MASK;
w25qxx_write_status_reg_dma(0x00, reg_data);
}
w25qxx_page_program_fun = w25qxx_quad_page_program_dma;
w25qxx_read_fun = w25qxx_quad_read_data;
return W25QXX_OK;
}
w25qxx_status_t w25qxx_disable_quad_mode(void)
{
uint8_t reg_data = 0;
w25qxx_read_status_reg2(&reg_data);
if (reg_data & REG2_QUAL_MASK)
{
reg_data &= (~REG2_QUAL_MASK);
w25qxx_write_status_reg(0x00, reg_data);
}
w25qxx_page_program_fun = w25qxx_page_program;
w25qxx_read_fun = w25qxx_stand_read_data;
return W25QXX_OK;
}
static w25qxx_status_t w25qxx_page_program(uint32_t addr, uint8_t *data_buf, uint32_t length)
{
uint8_t cmd[4] = {PAGE_PROGRAM};
cmd[1] = (uint8_t)(addr >> 16);
cmd[2] = (uint8_t)(addr >> 8);
cmd[3] = (uint8_t)(addr);
w25qxx_write_enable();
w25qxx_send_data(cmd, 4, data_buf, length);
while (w25qxx_is_busy() == W25QXX_BUSY)
;
return W25QXX_OK;
}
static w25qxx_status_t w25qxx_page_program_dma(uint32_t addr, uint8_t *data_buf, uint32_t length)
{
uint8_t cmd[4] = {PAGE_PROGRAM};
cmd[1] = (uint8_t)(addr >> 16);
cmd[2] = (uint8_t)(addr >> 8);
cmd[3] = (uint8_t)(addr);
w25qxx_write_enable_dma();
w25qxx_send_data_dma(cmd, 4, data_buf, length);
while (w25qxx_is_busy_dma() == W25QXX_BUSY)
;
return W25QXX_OK;
}
static w25qxx_status_t w25qxx_quad_page_program(uint32_t addr, uint8_t *data_buf, uint32_t length)
{
uint32_t cmd[2] = {0};
cmd[0] = QUAD_PAGE_PROGRAM;
cmd[1] = addr;
w25qxx_write_enable();
spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH);
spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 0/*wait cycles*/,
SPI_AITM_STANDARD/*spi address trans mode*/);
w25qxx_send_data_enhanced(cmd, 2, data_buf, length);
while (w25qxx_is_busy() == W25QXX_BUSY)
;
return W25QXX_OK;
}
static w25qxx_status_t w25qxx_quad_page_program_dma(uint32_t addr, uint8_t *data_buf, uint32_t length)
{
uint32_t cmd[2] = {0};
cmd[0] = QUAD_PAGE_PROGRAM;
cmd[1] = addr;
w25qxx_write_enable_dma();
spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH);
spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 0/*wait cycles*/,
SPI_AITM_STANDARD/*spi address trans mode*/);
w25qxx_send_data_enhanced_dma(cmd, 2, data_buf, length);
while (w25qxx_is_busy_dma() == W25QXX_BUSY)
;
return W25QXX_OK;
}
static w25qxx_status_t w25qxx_sector_program(uint32_t addr, uint8_t *data_buf)
{
uint8_t index = 0;
for (index = 0; index < w25qxx_FLASH_PAGE_NUM_PER_SECTOR; index++)
{
w25qxx_page_program_fun(addr, data_buf, w25qxx_FLASH_PAGE_SIZE);
addr += w25qxx_FLASH_PAGE_SIZE;
data_buf += w25qxx_FLASH_PAGE_SIZE;
}
return W25QXX_OK;
}
w25qxx_status_t w25qxx_write_data(uint32_t addr, uint8_t *data_buf, uint32_t length)
{
uint32_t sector_addr = 0;
uint32_t sector_offset = 0;
uint32_t sector_remain = 0;
uint32_t write_len = 0;
uint32_t index = 0;
uint8_t *pread = NULL;
uint8_t *pwrite = NULL;
uint8_t swap_buf[w25qxx_FLASH_SECTOR_SIZE] = {0};
while (length)
{
sector_addr = addr & (~(w25qxx_FLASH_SECTOR_SIZE - 1));
sector_offset = addr & (w25qxx_FLASH_SECTOR_SIZE - 1);
sector_remain = w25qxx_FLASH_SECTOR_SIZE - sector_offset;
write_len = ((length < sector_remain) ? length : sector_remain);
w25qxx_read_fun(sector_addr, swap_buf, w25qxx_FLASH_SECTOR_SIZE);
pread = swap_buf + sector_offset;
pwrite = data_buf;
for (index = 0; index < write_len; index++)
{
if ((*pwrite) != ((*pwrite) & (*pread)))
{
w25qxx_sector_erase(sector_addr);
while (w25qxx_is_busy() == W25QXX_BUSY)
;
break;
}
pwrite++;
pread++;
}
if (write_len == w25qxx_FLASH_SECTOR_SIZE)
{
w25qxx_sector_program(sector_addr, data_buf);
}
else
{
pread = swap_buf + sector_offset;
pwrite = data_buf;
for (index = 0; index < write_len; index++)
*pread++ = *pwrite++;
w25qxx_sector_program(sector_addr, swap_buf);
}
length -= write_len;
addr += write_len;
data_buf += write_len;
}
return W25QXX_OK;
}
w25qxx_status_t w25qxx_write_data_direct(uint32_t addr, uint8_t *data_buf, uint32_t length)
{
uint32_t page_remain = 0;
uint32_t write_len = 0;
while (length)
{
page_remain = w25qxx_FLASH_PAGE_SIZE - (addr & (w25qxx_FLASH_PAGE_SIZE - 1));
write_len = ((length < page_remain) ? length : page_remain);
w25qxx_page_program_fun(addr, data_buf, write_len);
length -= write_len;
addr += write_len;
data_buf += write_len;
}
return W25QXX_OK;
}
w25qxx_status_t w25qxx_write_data_direct_dma(uint32_t addr, uint8_t *data_buf, uint32_t length)
{
uint32_t page_remain = 0;
uint32_t write_len = 0;
while (length)
{
page_remain = w25qxx_FLASH_PAGE_SIZE - (addr & (w25qxx_FLASH_PAGE_SIZE - 1));
write_len = ((length < page_remain) ? length : page_remain);
w25qxx_page_program_fun(addr, data_buf, write_len);
length -= write_len;
addr += write_len;
data_buf += write_len;
}
return W25QXX_OK;
}
static w25qxx_status_t _w25qxx_read_data(uint32_t addr, uint8_t *data_buf, uint32_t length, w25qxx_read_t mode)
{
uint32_t cmd[2] = {0};
switch (mode)
{
case W25QXX_STANDARD:
*(((uint8_t *)cmd) + 0) = READ_DATA;
*(((uint8_t *)cmd) + 1) = (uint8_t)(addr >> 16);
*(((uint8_t *)cmd) + 2) = (uint8_t)(addr >> 8);
*(((uint8_t *)cmd) + 3) = (uint8_t)(addr >> 0);
w25qxx_receive_data((uint8_t *)cmd, 4, data_buf, length);
break;
case W25QXX_STANDARD_FAST:
*(((uint8_t *)cmd) + 0) = FAST_READ;
*(((uint8_t *)cmd) + 1) = (uint8_t)(addr >> 16);
*(((uint8_t *)cmd) + 2) = (uint8_t)(addr >> 8);
*(((uint8_t *)cmd) + 3) = (uint8_t)(addr >> 0);
*(((uint8_t *)cmd) + 4) = 0xFF;
spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_STANDARD, DATALENGTH);
w25qxx_receive_data((uint8_t *)cmd, 5, data_buf, length);
break;
case W25QXX_DUAL:
cmd[0] = FAST_READ_DUAL_OUTPUT;
cmd[1] = addr;
spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH);
spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/,
SPI_AITM_STANDARD/*spi address trans mode*/);
w25qxx_receive_data_enhanced(cmd, 2, data_buf, length);
break;
case W25QXX_DUAL_FAST:
cmd[0] = FAST_READ_DUAL_IO;
cmd[1] = addr << 8;
spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH);
spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 0/*wait cycles*/,
SPI_AITM_ADDR_STANDARD/*spi address trans mode*/);
w25qxx_receive_data_enhanced(cmd, 2, data_buf, length);
break;
case W25QXX_QUAD:
cmd[0] = FAST_READ_QUAL_OUTPUT;
cmd[1] = addr;
spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH);
spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/,
SPI_AITM_STANDARD/*spi address trans mode*/);
w25qxx_receive_data_enhanced(cmd, 2, data_buf, length);
break;
case W25QXX_QUAD_FAST:
cmd[0] = FAST_READ_QUAL_IO;
cmd[1] = addr << 8;
spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH);
spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 4/*wait cycles*/,
SPI_AITM_ADDR_STANDARD/*spi address trans mode*/);
w25qxx_receive_data_enhanced(cmd, 2, data_buf, length);
break;
}
return W25QXX_OK;
}
static w25qxx_status_t w25qxx_read_data_dma_less_1000bytes(uint32_t addr, uint8_t *data_buf, uint32_t length, w25qxx_read_t mode)
{
uint32_t cmd[2] = {0};
switch (mode) {
case W25QXX_STANDARD:
*(((uint8_t *)cmd) + 0) = READ_DATA;
*(((uint8_t *)cmd) + 1) = (uint8_t)(addr >> 16);
*(((uint8_t *)cmd) + 2) = (uint8_t)(addr >> 8);
*(((uint8_t *)cmd) + 3) = (uint8_t)(addr >> 0);
w25qxx_receive_data_dma((uint8_t *)cmd, 4, data_buf, length);
break;
case W25QXX_STANDARD_FAST:
*(((uint8_t *)cmd) + 0) = FAST_READ;
*(((uint8_t *)cmd) + 1) = (uint8_t)(addr >> 16);
*(((uint8_t *)cmd) + 2) = (uint8_t)(addr >> 8);
*(((uint8_t *)cmd) + 3) = (uint8_t)(addr >> 0);
*(((uint8_t *)cmd) + 4) = 0xFF;
w25qxx_receive_data_dma((uint8_t *)cmd, 5, data_buf, length);
break;
case W25QXX_DUAL:
cmd[0] = FAST_READ_DUAL_OUTPUT;
cmd[1] = addr;
spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH);
spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/,
SPI_AITM_STANDARD/*spi address trans mode*/);
w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length);
break;
case W25QXX_DUAL_FAST:
cmd[0] = FAST_READ_DUAL_IO;
cmd[1] = addr << 8;
spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_DUAL, DATALENGTH);
spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 0/*wait cycles*/,
SPI_AITM_ADDR_STANDARD/*spi address trans mode*/);
w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length);
break;
case W25QXX_QUAD:
cmd[0] = FAST_READ_QUAL_OUTPUT;
cmd[1] = addr;
spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH);
spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 24/*address length*/, 8/*wait cycles*/,
SPI_AITM_STANDARD/*spi address trans mode*/);
w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length);
break;
case W25QXX_QUAD_FAST:
cmd[0] = FAST_READ_QUAL_IO;
cmd[1] = addr << 8;
spi_init(spi_bus_no, SPI_WORK_MODE_0, SPI_FF_QUAD, DATALENGTH);
spi_init_non_standard(spi_bus_no, 8/*instrction length*/, 32/*address length*/, 4/*wait cycles*/,
SPI_AITM_ADDR_STANDARD/*spi address trans mode*/);
w25qxx_receive_data_enhanced_dma(cmd, 2, data_buf, length);
break;
}
return W25QXX_OK;
}
w25qxx_status_t w25qxx_read_data(uint32_t addr, uint8_t *data_buf, uint32_t length, w25qxx_read_t mode)
{
uint32_t len = 0;
while (length)
{
len = ((length >= 0x010000) ? 0x010000 : length);
_w25qxx_read_data(addr, data_buf, len, mode);
addr += len;
data_buf += len;
length -= len;
}
return W25QXX_OK;
}
w25qxx_status_t w25qxx_read_data_dma(uint32_t addr, uint8_t *data_buf, uint32_t length, w25qxx_read_t mode)
{
uint32_t len = 0;
while (length)
{
len = ((length >= 0x010000) ? 0x010000 : length);
w25qxx_read_data_dma_less_1000bytes(addr, data_buf, len, mode);
addr += len;
data_buf += len;
length -= len;
}
return W25QXX_OK;
}
static w25qxx_status_t w25qxx_stand_read_data(uint32_t addr, uint8_t *data_buf, uint32_t length)
{
return w25qxx_read_data(addr, data_buf, length, W25QXX_STANDARD_FAST);
}
static w25qxx_status_t w25qxx_quad_read_data(uint32_t addr, uint8_t *data_buf, uint32_t length)
{
return w25qxx_read_data(addr, data_buf, length, W25QXX_QUAD_FAST);
}
w25qxx_status_t w25qxx_enable_xip_mode(void)
{
if (spi_handle != spi[3])
return W25QXX_ERROR;
spi_handle->xip_ctrl = (0x01 << 29) | (0x02 << 26) | (0x01 << 23) | (0x01 << 22) | (0x04 << 13) |
(0x01 << 12) | (0x02 << 9) | (0x06 << 4) | (0x01 << 2) | 0x02;
spi_handle->xip_incr_inst = 0xEB;
spi_handle->xip_mode_bits = 0x00;
spi_handle->xip_ser = 0x01;
spi_handle->ssienr = 0x01;
sysctl->peri.spi3_xip_en = 1;
return W25QXX_OK;
}
w25qxx_status_t w25qxx_disable_xip_mode(void)
{
sysctl->peri.spi3_xip_en = 0;
return W25QXX_OK;
}

29
src/hello_world/main.c
View File

@ -13,21 +13,20 @@
* limitations under the License.
*/
#include <stdio.h>
#include "sleep.h"
#include "encoding.h"
#include "bsp.h"
int core1_function(void *ctx)
{
uint64_t core = current_coreid();
printf("Core %ld Hello world\n", core);
while(1);
}
int main()
{
uint64_t core_id = current_coreid();
if (core_id == 0)
{
printf("Core 0 Hello, world!\n");
}
else
{
msleep(100);
printf("Core 1 Hello, world!\n");
}
while (1)
;
return 0;
uint64_t core = current_coreid();
printf("Core %ld Hello world\n", core);
register_core1(core1_function, NULL);
while(1);
}