461 lines
20 KiB
C
461 lines
20 KiB
C
#include "maprobe.h"
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inline uint64_t generate_rand_address(uint64_t base_addr, uint64_t end_addr, uint64_t align) {
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return (rand() % (end_addr - base_addr) + base_addr) / align * align;
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}
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void generate_rand_address_array(uint64_t* dest, uint64_t base_addr, uint64_t end_addr, uint64_t align, int number) {
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for (int i = 0; i < number; i++) {
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*(dest + i) = generate_rand_address(base_addr, end_addr, align);
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}
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}
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uint64_t generate_pointer_tracing_address(uint64_t base_addr, uint64_t end_addr, uint64_t step) {
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return setup_pointer_tracing_linklist(base_addr, end_addr, step);
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}
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uint64_t setup_pointer_tracing_linklist(uint64_t base_addr, uint64_t end_addr, uint64_t step)
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{
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uint64_t num_valid_node = 0;
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assert(step % 8 == 0);
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assert(step >= 8);
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for (uint64_t cur_addr = base_addr; cur_addr < end_addr;) {
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uint64_t next_addr = cur_addr + step;
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*((uint64_t*)cur_addr) = next_addr;
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cur_addr = next_addr;
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num_valid_node++;
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}
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return num_valid_node;
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}
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uint64_t read_pointer_tracing_linklist(uint64_t base_addr, uint64_t num_valid_node)
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{
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uint64_t cur_addr = base_addr;
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for (int i = 0; i < num_valid_node; i++) {
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cur_addr = (*(uint64_t*)cur_addr);
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}
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return cur_addr;
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}
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void latency_test_warmup(uint64_t base_addr, uint64_t end_addr)
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{
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setup_pointer_tracing_linklist(base_addr, end_addr, _PERF_CACHELINE_SIZE_BYTE);
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}
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float test_pointer_tracing_latency(uint64_t size, int step, int iter, int to_csv)
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{
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// printf("pointer tracing latency test\n");
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// printf("range (B), read latency, iters, samples, cycles\n");
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register uint64_t result = 0; // make sure compiler will not opt read_pointer_tracing_linklist
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_perf_start_timer();
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uint64_t nnode = setup_pointer_tracing_linklist(_PERF_TEST_ADDR_BASE, _PERF_TEST_ADDR_BASE + size, step);
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_perf_end_timer();
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uint64_t total_node = nnode * iter;
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// _perf_print_timer();
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_perf_start_timer();
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for (int i = 0; i < iter; i++) {
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result += read_pointer_tracing_linklist(_PERF_TEST_ADDR_BASE, nnode);
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}
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_perf_end_timer();
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// _perf_print_timer();
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float acpa = (float)perf.cycle / total_node; // average cycle per access
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if (to_csv) {
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printf("%ld, %f, %d, %ld, %ld\n", size, acpa, iter, total_node, perf.cycle);
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} else {
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printf("range %ldKB (%d iters) pointer tracing read latency %f, throughput %f B/cycle (%ld samples, %ld cycles)\n",
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size/KB, iter, acpa, total_node * 8 * BYTE / (float)perf.cycle, total_node, perf.cycle
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);
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}
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_perf_g_total_samples += total_node;
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_perf_blackhole(result);
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return acpa;
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}
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float test_same_address_load_latency(int iter, int to_csv)
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{
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// printf("same address load latency test\n", step);
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// printf("range (B), read latency, iters, samples, cycles\n");
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register uint64_t result = 0;
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// _perf_print_timer();
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_perf_start_timer();
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uint64_t address = _PERF_TEST_ADDR_BASE;
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for (int i = 0; i < iter; i++) {
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result += *((volatile uint64_t*) (address));
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}
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_perf_end_timer();
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// _perf_print_timer();
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uint64_t total_access = iter;
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float acpa = (float)perf.cycle / total_access; // average cycle per access
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if (to_csv) {
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printf("%ld, %f, %d, %ld, %ld\n", 0, acpa, iter, total_access, perf.cycle);
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} else {
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printf("same address read latency %f, throughput %f B/cycle (%ld samples, %ld cycles)\n",
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acpa, total_access * 8 * BYTE / (float)perf.cycle, total_access, perf.cycle
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);
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}
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_perf_g_total_samples += total_access;
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_perf_blackhole(result);
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return acpa;
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}
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float test_read_after_write_latency(int iter, int to_csv)
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{
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// printf("same address store-load latency test\n", step);
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// printf("range (B), read latency, iters, samples, cycles\n");
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volatile uint64_t result = 0; // make sure compiler will store data to memory
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// _perf_print_timer();
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_perf_start_timer();
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for (int i = 0; i < iter; i++) {
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uint64_t address = _PERF_TEST_ADDR_BASE;
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result += *((uint64_t*) (address));
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address += sizeof(uint64_t);
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}
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_perf_end_timer();
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// _perf_print_timer();
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uint64_t total_access = iter;
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float acpa = (float)perf.cycle / total_access; // average cycle per access
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if (to_csv) {
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printf("%ld, %f, %d, %ld, %ld\n", 0, acpa, iter, total_access, perf.cycle);
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} else {
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printf("read after write latency %f, throughput %f B/cycle (%ld samples, %ld cycles)\n",
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acpa, total_access * 8 * BYTE / (float)perf.cycle, total_access, perf.cycle
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);
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}
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_perf_g_total_samples += total_access;
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_perf_blackhole(result);
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return acpa;
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}
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float test_linear_access_latency_simple(uint64_t size, uint64_t step, int iter, int to_csv)
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{
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// printf("stride %d linear access latency test\n", step);
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// printf("range (B), read latency, iters, samples, cycles\n");
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register uint64_t result = 0;
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uint64_t num_access = size / step;
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// _perf_print_timer();
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_perf_start_timer();
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for (int i = 0; i < iter; i++) {
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uint64_t address = _PERF_TEST_ADDR_BASE;
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for (int j = 0; j < num_access; j++) {
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result += *((volatile uint64_t*) (address));
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address += step;
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}
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}
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_perf_end_timer();
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// _perf_print_timer();
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uint64_t total_access = num_access * iter;
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float acpa = (float)perf.cycle / total_access; // average cycle per access
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if (to_csv) {
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printf("%ld, %f, %d, %ld, %ld\n", size, acpa, iter, total_access, perf.cycle);
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} else {
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printf("range %ldKB (%d iters) simple linear read latency %f, throughput %f B/cycle (%ld samples, %ld cycles), stride %dB\n",
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size/KB, iter, acpa, total_access * 8 * BYTE / (float)perf.cycle, total_access, perf.cycle, step
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);
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}
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_perf_g_total_samples += total_access;
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_perf_blackhole(result);
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return acpa;
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}
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float test_linear_access_latency_batch8(uint64_t size, uint64_t step, int iter, int to_csv)
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{
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// printf("stride %d linear access latency test\n", step);
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// printf("range (B), read latency, iters, samples, cycles\n");
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uint64_t num_access = size / step;
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num_access += num_access % 8 ? 8 - num_access % 8 : 0;
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assert(num_access >= 8);
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// prepare access offset
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register uint64_t address_offset_1 = step * 1;
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register uint64_t address_offset_2 = step * 2;
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register uint64_t address_offset_3 = step * 3;
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register uint64_t address_offset_4 = step * 4;
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register uint64_t address_offset_5 = step * 5;
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register uint64_t address_offset_6 = step * 6;
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register uint64_t address_offset_7 = step * 7;
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register uint64_t address_offset_8 = step * 8;
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// _perf_print_timer();
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_perf_start_timer();
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for (int i = 0; i < iter; i++) {
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uint64_t address = _PERF_TEST_ADDR_BASE;
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for (int j = 0; j < num_access; j += 8) {
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__asm__ volatile (
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"mv a1, %[addr]\n"
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"add a2, %[addr], %[offset1]\n"
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"add a3, %[addr], %[offset2]\n"
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"add a4, %[addr], %[offset3]\n"
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"add a5, %[addr], %[offset4]\n"
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"add t0, %[addr], %[offset5]\n"
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"add t1, %[addr], %[offset6]\n"
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"add t2, %[addr], %[offset7]\n"
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"ld a0, 0(a1)\n"
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"ld a0, 0(a2)\n"
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"ld a0, 0(a3)\n"
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"ld a0, 0(a4)\n"
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"ld a0, 0(a5)\n"
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"ld a0, 0(t0)\n"
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"ld a0, 0(t1)\n"
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"ld a0, 0(t2)\n"
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::
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[offset1] "r"(address_offset_1),
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[offset2] "r"(address_offset_2),
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[offset3] "r"(address_offset_3),
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[offset4] "r"(address_offset_4),
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[offset5] "r"(address_offset_5),
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[offset6] "r"(address_offset_6),
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[offset7] "r"(address_offset_7),
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[addr] "r"(address)
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: "a0", "a1", "a2", "a3", "a4", "a5", "t0", "t1", "t2", "t3"
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);
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address += address_offset_8;
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// register uint64_t access_addr_0 = address + address_offset_0;
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// register uint64_t access_addr_1 = address + address_offset_1;
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// register uint64_t access_addr_2 = address + address_offset_2;
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// register uint64_t access_addr_3 = address + address_offset_3;
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// register uint64_t access_addr_4 = address + address_offset_4;
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// register uint64_t access_addr_5 = address + address_offset_5;
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// register uint64_t access_addr_6 = address + address_offset_6;
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// register uint64_t access_addr_7 = address + address_offset_7;
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// address += address_offset_8;
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// __asm__ volatile ("ld a0, 0(%[addr])\n" :: [addr] "r"(access_addr_0) : "a0");
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// __asm__ volatile ("ld a0, 0(%[addr])\n" :: [addr] "r"(access_addr_1) : "a0");
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// __asm__ volatile ("ld a0, 0(%[addr])\n" :: [addr] "r"(access_addr_2) : "a0");
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// __asm__ volatile ("ld a0, 0(%[addr])\n" :: [addr] "r"(access_addr_3) : "a0");
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// __asm__ volatile ("ld a0, 0(%[addr])\n" :: [addr] "r"(access_addr_4) : "a0");
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// __asm__ volatile ("ld a0, 0(%[addr])\n" :: [addr] "r"(access_addr_5) : "a0");
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// __asm__ volatile ("ld a0, 0(%[addr])\n" :: [addr] "r"(access_addr_6) : "a0");
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// __asm__ volatile ("ld a0, 0(%[addr])\n" :: [addr] "r"(access_addr_7) : "a0");
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}
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}
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_perf_end_timer();
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// _perf_print_timer();
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uint64_t total_access = num_access * iter;
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float acpa = (float)perf.cycle / total_access; // average cycle per access
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if (to_csv) {
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printf("%ld, %f, %d, %ld, %ld\n", size, acpa, iter, total_access, perf.cycle);
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} else {
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printf("range %ldKB (%d iters) batch(8) linear read latency %f, throughput %f B/cycle (%ld samples, %ld cycles), stride %dB\n",
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size/KB, iter, acpa, total_access * 8 * BYTE / (float)perf.cycle, total_access, perf.cycle, step
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);
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}
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_perf_g_total_samples += total_access;
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return acpa;
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}
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float test_linear_write_latency_batch8(uint64_t size, uint64_t step, int iter, int to_csv)
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{
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// printf("stride %d linear access latency test\n", step);
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// printf("range (B), read latency, iters, samples, cycles\n");
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uint64_t num_access = size / step;
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num_access += num_access % 8 ? 8 - num_access % 8 : 0;
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assert(num_access >= 8);
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// prepare access offset
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uint64_t address_offset_0 = 0;
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register uint64_t address_offset_1 = step * 1;
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register uint64_t address_offset_2 = step * 2;
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register uint64_t address_offset_3 = step * 3;
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register uint64_t address_offset_4 = step * 4;
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register uint64_t address_offset_5 = step * 5;
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register uint64_t address_offset_6 = step * 6;
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register uint64_t address_offset_7 = step * 7;
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register uint64_t address_offset_8 = step * 8;
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// _perf_print_timer();
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_perf_start_timer();
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for (int i = 0; i < iter; i++) {
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uint64_t address = _PERF_TEST_ADDR_BASE;
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for (int j = 0; j < num_access; j += 8) {
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register uint64_t access_addr_0 = address + address_offset_0;
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register uint64_t access_addr_1 = address + address_offset_1;
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register uint64_t access_addr_2 = address + address_offset_2;
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register uint64_t access_addr_3 = address + address_offset_3;
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register uint64_t access_addr_4 = address + address_offset_4;
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register uint64_t access_addr_5 = address + address_offset_5;
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register uint64_t access_addr_6 = address + address_offset_6;
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register uint64_t access_addr_7 = address + address_offset_7;
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address += address_offset_8;
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__asm__ volatile ("sd a0, 0(%[addr])\n" :: [addr] "r"(access_addr_0) : "a0");
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__asm__ volatile ("sd a0, 0(%[addr])\n" :: [addr] "r"(access_addr_1) : "a0");
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__asm__ volatile ("sd a0, 0(%[addr])\n" :: [addr] "r"(access_addr_2) : "a0");
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__asm__ volatile ("sd a0, 0(%[addr])\n" :: [addr] "r"(access_addr_3) : "a0");
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__asm__ volatile ("sd a0, 0(%[addr])\n" :: [addr] "r"(access_addr_4) : "a0");
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__asm__ volatile ("sd a0, 0(%[addr])\n" :: [addr] "r"(access_addr_5) : "a0");
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__asm__ volatile ("sd a0, 0(%[addr])\n" :: [addr] "r"(access_addr_6) : "a0");
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__asm__ volatile ("sd a0, 0(%[addr])\n" :: [addr] "r"(access_addr_7) : "a0");
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}
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}
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_perf_end_timer();
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// _perf_print_timer();
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uint64_t total_access = num_access * iter;
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float acpa = (float)perf.cycle / total_access; // average cycle per access
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if (to_csv) {
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printf("%ld, %f, %d, %ld, %ld\n", size, acpa, iter, total_access, perf.cycle);
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} else {
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printf("range %ldKB (%d iters) batch(8) linear write latency %f, throughput %f B/cycle (%ld samples, %ld cycles), stride %dB\n",
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size/KB, iter, acpa, total_access * 8 * BYTE / (float)perf.cycle, total_access, perf.cycle, step
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);
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}
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_perf_g_total_samples += total_access;
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return acpa;
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}
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float test_linear_access_latency(uint64_t size, uint64_t step, int iter, int to_csv)
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{
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return test_linear_access_latency_batch8(size, step, iter, to_csv);
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}
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float test_linear_write_latency(uint64_t size, uint64_t step, int iter, int to_csv)
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{
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return test_linear_write_latency_batch8(size, step, iter, to_csv);
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}
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float test_random_access_latency(uint64_t num_access, uint64_t test_range, uint64_t test_align, int pregen_addr, int iter, int to_csv)
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{
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// printf("align %d random access (cache line) latency test, %s\n",
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// test_align, pregen_addr ? "use pregen addr array" : "gen rand addr at run time"
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// );
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// printf("range (B), read latency, iters, samples, cycles\n");
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register uint64_t result = 0;
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// _perf_print_timer();
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uint64_t total_access = num_access * iter;
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if (test_range > total_access*8*_PERF_CACHELINE_SIZE_BYTE) {
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printf("total access size %ldKB less than test range %ldKB, ignored\n",
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total_access*8*_PERF_CACHELINE_SIZE_BYTE/KB,
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test_range/KB
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);
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return 0;
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}
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// alloc memory for random access addr array and data
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assert(test_align >= 8 * BYTE);
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// assert(size >= test_align);
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// uint64_t num_access = size / test_align;
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if (pregen_addr) {
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uint64_t test_array_base_addr = _PERF_TEST_ADDR_BASE + num_access * sizeof(uint64_t*);
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uint64_t address_array_base_addr = _PERF_TEST_ADDR_BASE;
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generate_rand_address_array((uint64_t*)address_array_base_addr, test_array_base_addr, test_array_base_addr + test_range, test_align, num_access);
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_perf_start_timer();
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for (int i = 0; i < iter; i++) {
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for (int j = 0; j < num_access; j++) {
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result += *((uint64_t*) (address_array_base_addr + j * sizeof(uint64_t*)));
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}
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}
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_perf_end_timer();
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} else {
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_perf_start_timer();
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for (int i = 0; i < iter; i++) {
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for (int j = 0; j < num_access; j++) {
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result += *((uint64_t*) (generate_rand_address(_PERF_TEST_ADDR_BASE, _PERF_TEST_ADDR_BASE + test_range, test_align)));
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}
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}
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_perf_end_timer();
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}
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// _perf_print_timer();
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float acpa = (float)perf.cycle / total_access; // average cycle per access
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if (to_csv) {
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printf("%ld, %f, %d, %ld, %ld\n", test_range, acpa, iter, total_access, perf.cycle);
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} else {
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printf("range %ldKB, access %ldKB (cover %ldKB) (%d iters) random read latency %f, throughput %f B/cycle (%ld samples, %ld cycles), align %ldB, %s\n",
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test_range/KB, total_access*8*BYTE/KB, total_access*8*_PERF_CACHELINE_SIZE_BYTE/KB, iter, acpa, total_access * 8 * BYTE / (float)perf.cycle, total_access, perf.cycle, test_align,
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pregen_addr ? "pregen addr" : "runtime addr"
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);
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}
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_perf_g_total_samples += total_access;
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_perf_blackhole(result);
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return acpa;
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}
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void legacy_test_mem_throughput(uint64_t iter)
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{
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uint64_t remain = iter;
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uint64_t result = 0;
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uint64_t access_addr = _PERF_TEST_ADDR_BASE;
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_perf_start_timer();
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while (remain--) {
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result += *(uint64_t*) access_addr;
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access_addr += _PERF_CACHELINE_SIZE_BYTE;
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}
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_perf_end_timer();
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*(uint64_t*) _PERF_BLACKHOLE = result;
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printf("mem band width %f B/cycle (%d samples)\n", (float)iter * _PERF_CACHELINE_SIZE_BYTE / perf.cycle, iter);
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}
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void legacy_test_mem_throughput_same_set(uint64_t iter)
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{
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uint64_t remain = iter;
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uint64_t result = 0;
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uint64_t access_addr = _PERF_TEST_ADDR_BASE;
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_perf_start_timer();
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while (remain--) {
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result += *(uint64_t*) access_addr;
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access_addr += _PERF_ADDR_STRIDE_L1_SAME_SET;
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}
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_perf_end_timer();
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*(uint64_t*) _PERF_BLACKHOLE = result;
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printf("mem band width %f B/cycle (%d samples)\n", (float)iter * _PERF_CACHELINE_SIZE_BYTE / perf.cycle, iter);
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}
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void generate_linear_access_latency_matrix(uint64_t step)
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{
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// step can be _PERF_CACHELINE_SIZE_BYTE or 8*BYTE
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#define LINEAR_ACCESS_MATRIX_SIZE_MAX_POW2_KB 14
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// LINEAR_ACCESS_MATRIX_SIZE_MAX_POW2_KB 14: 14 cases in total, from 1KB to 8MB
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DEFINE_FLOAT_RESULT_MATRIX(linear_access_latency,size_kb_pow2,LINEAR_ACCESS_MATRIX_SIZE_MAX_POW2_KB,iter,3);
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FOR(x,LINEAR_ACCESS_MATRIX_SIZE_MAX_POW2_KB) { linear_access_latency_row_array[x] = x; }
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FOR(x,3) { linear_access_latency_column_array[x] = x; }
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for (int i = 0; i < LINEAR_ACCESS_MATRIX_SIZE_MAX_POW2_KB; i++) {
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int warm_up_iter = i < 6 ? 4 : 1;
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int test_iter = i < 6 ? 4 : 2;
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linear_access_latency_result_array[i][0] = test_linear_access_latency((1<<i)*KB,step,warm_up_iter,0); //warmup
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linear_access_latency_result_array[i][1] = test_linear_access_latency((1<<i)*KB,step,test_iter,0); //test
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linear_access_latency_result_array[i][2] = test_linear_access_latency((1<<i)*KB,step,test_iter,0); //test
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}
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printf("[test step %ld]\n", step);
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print_float_result_matrix(&linear_access_latency_matrix_meta);
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}
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void generate_pointer_tracing_latency_matrix(uint64_t step)
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{
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// step can be _PERF_CACHELINE_SIZE_BYTE or 8*BYTE
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#define POINTER_CHASING_MATRIX_SIZE_MAX_POW2_KB 14
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// POINTER_CHASING_MATRIX_SIZE_MAX_POW2_KB 14: 14 cases in total, from 1KB to 8MB
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DEFINE_FLOAT_RESULT_MATRIX(pointer_tracing_latency,size_kb_pow2,POINTER_CHASING_MATRIX_SIZE_MAX_POW2_KB,iter,3);
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FOR(x,POINTER_CHASING_MATRIX_SIZE_MAX_POW2_KB) { pointer_tracing_latency_row_array[x] = x; }
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FOR(x,3) { pointer_tracing_latency_column_array[x] = x; }
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for (int i = 0; i < POINTER_CHASING_MATRIX_SIZE_MAX_POW2_KB; i++) {
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int warm_up_iter = i < 6 ? 4 : 1;
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int test_iter = i < 6 ? 4 : 2;
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pointer_tracing_latency_result_array[i][0] = test_pointer_tracing_latency((1<<i)*KB,step,warm_up_iter,0); //warmup
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pointer_tracing_latency_result_array[i][1] = test_pointer_tracing_latency((1<<i)*KB,step,test_iter,0); //test
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pointer_tracing_latency_result_array[i][2] = test_pointer_tracing_latency((1<<i)*KB,step,test_iter,0); //test
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}
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printf("[test step %ld]\n", step);
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print_float_result_matrix(&pointer_tracing_latency_matrix_meta);
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}
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void generate_random_access_latency_matrix()
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{
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#define RANDOM_ACCESS_MATRIX_SIZE_MAX_POW2_KB 6
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// RANDOM_ACCESS_MATRIX_SIZE_MAX_POW2_KB 10: from 1KB to 512KB
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#define RANDOM_ACCESS_MATRIX_ACCESS_MAX_POW2_KB 6
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// RANDOM_ACCESS_MATRIX_ACCESS_MAX_POW2_KB 10: from 1KB to 512KB
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DEFINE_FLOAT_RESULT_MATRIX(random_access_latency,test_range_size_kb_pow2,RANDOM_ACCESS_MATRIX_SIZE_MAX_POW2_KB,access_size_kb_pow2,RANDOM_ACCESS_MATRIX_ACCESS_MAX_POW2_KB);
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FOR(x,RANDOM_ACCESS_MATRIX_SIZE_MAX_POW2_KB) { random_access_latency_row_array[x] = x; }
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FOR(x,RANDOM_ACCESS_MATRIX_ACCESS_MAX_POW2_KB) { random_access_latency_column_array[x] = x; }
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for (int i = 0; i < RANDOM_ACCESS_MATRIX_SIZE_MAX_POW2_KB; i++) {
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for (int j = 0; j < RANDOM_ACCESS_MATRIX_ACCESS_MAX_POW2_KB; j++) {
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uint64_t access_size = (1<<j)*KB;
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uint64_t num_access = access_size / sizeof(uint64_t);
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uint64_t test_range = (1<<i)*KB;
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test_random_access_latency(num_access, test_range, sizeof(uint64_t), 1, 1, 0); //warmup
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random_access_latency_result_array[i][j] = test_random_access_latency(num_access, test_range, sizeof(uint64_t), 1, 1, 0); //test
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}
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}
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print_float_result_matrix(&random_access_latency_matrix_meta);
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|
}
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