99 lines
5.0 KiB
C
99 lines
5.0 KiB
C
#include "maprobe.h"
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float test_l1_load_bandwidth(uint64_t size, int iter, int to_csv)
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{
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// printf("stride %d linear access latency test\n", step);
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// printf("range (B), read latency, iters, samples, cycles\n");
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assert(size >= _PERF_CACHELINE_SIZE_BYTE);
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// _perf_print_timer();
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_perf_start_timer();
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for (int i = 0; i < iter; i++) {
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for (uint64_t address = _PERF_TEST_ADDR_BASE; address < _PERF_TEST_ADDR_BASE + size; address += _PERF_CACHELINE_SIZE_BYTE) {
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__asm__ volatile ("ld a0, 0(%[addr])\n" :: [addr] "r"(address) : "a0");
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__asm__ volatile ("ld a0, 8(%[addr])\n" :: [addr] "r"(address) : "a0");
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__asm__ volatile ("ld a0, 16(%[addr])\n" :: [addr] "r"(address) : "a0");
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__asm__ volatile ("ld a0, 24(%[addr])\n" :: [addr] "r"(address) : "a0");
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__asm__ volatile ("ld a0, 32(%[addr])\n" :: [addr] "r"(address) : "a0");
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__asm__ volatile ("ld a0, 40(%[addr])\n" :: [addr] "r"(address) : "a0");
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__asm__ volatile ("ld a0, 48(%[addr])\n" :: [addr] "r"(address) : "a0");
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__asm__ volatile ("ld a0, 56(%[addr])\n" :: [addr] "r"(address) : "a0");
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}
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}
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_perf_end_timer();
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// _perf_print_timer();
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uint64_t total_access = size / _PERF_CACHELINE_SIZE_BYTE * 8 * iter;
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float bandwidth = total_access * 8 * BYTE / (float)perf.cycle;
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if (to_csv) {
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printf("%ld, %f, %d, %ld, %ld\n", size, (float)perf.cycle / total_access, iter, total_access, perf.cycle);
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} else {
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printf("range %ldKB (%d iters) dcache linear (8Byte) read, latency %f, throughput %f B/cycle (%ld samples, %ld cycles), stride %dB\n",
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size/KB, iter, (float)perf.cycle / total_access, bandwidth, total_access, perf.cycle, 8
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);
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}
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_perf_g_total_samples += total_access;
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return bandwidth;
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}
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float test_l1_store_bandwidth(uint64_t size, int iter, int to_csv)
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{
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// printf("stride %d linear access latency test\n", step);
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// printf("range (B), read latency, iters, samples, cycles\n");
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assert(size >= _PERF_CACHELINE_SIZE_BYTE);
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// _perf_print_timer();
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_perf_start_timer();
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for (int i = 0; i < iter; i++) {
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for (uint64_t address = _PERF_TEST_ADDR_BASE; address < _PERF_TEST_ADDR_BASE + size; address += _PERF_CACHELINE_SIZE_BYTE) {
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__asm__ volatile ("sd a0, 0(%[addr])\n" :: [addr] "r"(address) : "a0");
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__asm__ volatile ("sd a0, 8(%[addr])\n" :: [addr] "r"(address) : "a0");
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__asm__ volatile ("sd a0, 16(%[addr])\n" :: [addr] "r"(address) : "a0");
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__asm__ volatile ("sd a0, 24(%[addr])\n" :: [addr] "r"(address) : "a0");
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__asm__ volatile ("sd a0, 32(%[addr])\n" :: [addr] "r"(address) : "a0");
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__asm__ volatile ("sd a0, 40(%[addr])\n" :: [addr] "r"(address) : "a0");
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__asm__ volatile ("sd a0, 48(%[addr])\n" :: [addr] "r"(address) : "a0");
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__asm__ volatile ("sd a0, 56(%[addr])\n" :: [addr] "r"(address) : "a0");
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}
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}
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_perf_end_timer();
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// _perf_print_timer();
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uint64_t total_access = size / _PERF_CACHELINE_SIZE_BYTE * 8 * iter;
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float bandwidth = total_access * 8 * BYTE / (float)perf.cycle;
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if (to_csv) {
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printf("%ld, %f, %d, %ld, %ld\n", size, (float)perf.cycle / total_access, iter, total_access, perf.cycle);
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} else {
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printf("range %ldKB (%d iters) dcache linear (8Byte) store latency %f, throughput %f B/cycle (%ld samples, %ld cycles), stride %dB\n",
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size/KB, iter, (float)perf.cycle / total_access, bandwidth, total_access, perf.cycle, 8
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);
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}
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_perf_g_total_samples += total_access;
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return bandwidth;
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}
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float test_l1_store_wcb_bandwidth(uint64_t size, int iter, int to_csv)
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{
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// printf("stride %d linear access latency test\n", step);
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// printf("range (B), read latency, iters, samples, cycles\n");
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assert(size >= _PERF_CACHELINE_SIZE_BYTE);
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// _perf_print_timer();
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_perf_start_timer();
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for (int i = 0; i < iter; i++) {
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for (uint64_t address = _PERF_TEST_ADDR_BASE; address < _PERF_TEST_ADDR_BASE + size; address += _PERF_CACHELINE_SIZE_BYTE) {
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__asm__ volatile ("sd a0, 0(%[addr])\n" :: [addr] "r"(address) : "a0");
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}
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}
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_perf_end_timer();
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// _perf_print_timer();
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uint64_t total_access = size / _PERF_CACHELINE_SIZE_BYTE * iter;
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float bandwidth = total_access * _PERF_CACHELINE_SIZE_BYTE / (float)perf.cycle;
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if (to_csv) {
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printf("%ld, %f, %d, %ld, %ld\n", size, (float)perf.cycle / total_access, iter, total_access, perf.cycle);
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} else {
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printf("range %ldKB (%d iters) dcache linear (8Byte) store latency %f, throughput %f B/cycle (L1-L2 %f B/cycle) (%ld samples, %ld cycles), stride %dB\n",
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size/KB, iter, (float)perf.cycle / total_access, total_access * 8 * BYTE / (float)perf.cycle, total_access * _PERF_CACHELINE_SIZE_BYTE / (float)perf.cycle, total_access, perf.cycle, _PERF_CACHELINE_SIZE_BYTE
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);
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}
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_perf_g_total_samples += total_access;
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return bandwidth;
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} |