Yanyan Jiang
00cabf5d98
add full callback support
2018-08-10 17:16:42 +00:00
Yanyan Jiang
b1f87c61fd
refactors
2018-08-10 16:50:16 +00:00
Yanyan Jiang
5c5d3ad03f
a much better tracing code
2018-08-10 16:44:11 +00:00
Yanyan Jiang
87ea80951b
make macros better
2018-08-10 16:15:06 +00:00
Yanyan Jiang
1033cbd159
cleanups
2018-08-10 22:54:47 +08:00
Yanyan Jiang
1066f5a63b
add more trace facilities
2018-08-10 22:49:37 +08:00
Yanyan Jiang
fdf7a82ad5
add experimental trace facilities
2018-08-10 22:06:07 +08:00
Yanyan Jiang
74ac665b6e
add tracing
2018-08-10 17:08:56 +08:00
Yanyan Jiang
d1d3f8e8e3
add trace framework
2018-08-10 06:51:37 +00:00
Yanyan Jiang
d41a3656aa
add some trace apis
2018-08-10 05:15:06 +00:00
Yanyan Jiang
20249fdcf1
refactor, add trace api
2018-08-10 02:29:48 +00:00
Yanyan Jiang
397c288fb5
refactors
2018-08-10 01:30:05 +00:00
Yanyan Jiang
15e5ac27c2
Merge branch 'jyy' into 'master'
...
Refactor x86-qemu reference implementation
See merge request !164
2018-08-09 16:16:27 +08:00
Yanyan Jiang
3365c92c4b
x86-qemu mpe cleanup
2018-08-09 08:02:39 +00:00
Yanyan Jiang
65e2c2c5dd
refactor mp stack
2018-08-09 07:26:01 +00:00
Yanyan Jiang
b3f9e593bd
x86-qemu: code cleanup and refactor
2018-08-09 06:55:11 +00:00
Yanyan Jiang
bc1a5588c4
code refactors
2018-08-09 06:21:37 +00:00
Yanyan Jiang
3588d60f7f
style fixes
2018-08-09 03:46:33 +00:00
Yanyan Jiang
0ab93ce23a
further cleanup of code
2018-08-09 02:34:48 +00:00
Yanyan Jiang
6f1ed8807a
make asye.c look better
2018-08-09 02:13:07 +00:00
Yanyan Jiang
3f1582b009
revise asye impl
2018-08-09 01:22:15 +00:00
Yanyan Jiang
42c41eb1ec
clean up code
2018-08-08 15:08:51 +00:00
Yanyan Jiang
9d9187dbc8
add message in _Event
2018-08-08 15:06:09 +00:00
Yanyan Jiang
1e8eeff1c3
rename regs to ctx
2018-08-08 14:44:54 +00:00
Yanyan Jiang
40c207a68d
change _RegSet to _Context
2018-08-08 14:38:35 +00:00
Yanyan Jiang
15b74681e3
Merge branch 'jyy' into 'master'
...
asye,pte,mpe: update x86-qemu implementations
See merge request !163
2018-08-08 21:38:59 +08:00
Yanyan Jiang
5d20c32b45
api revisions
2018-08-08 13:35:36 +00:00
Yanyan Jiang
8c344874b3
code refactor, add some todos
2018-08-08 13:23:08 +00:00
Yanyan Jiang
b610dcebf7
refactors
2018-08-08 12:32:47 +00:00
Yanyan Jiang
52413b67ef
ring3 proc works
2018-08-08 11:58:38 +00:00
Yanyan Jiang
b1d192d69b
impl pte
2018-08-08 07:12:31 +00:00
Yanyan Jiang
7fc31929fd
add pte _protect, _switch, _map impl, with partial _unprotect
2018-08-08 06:12:32 +00:00
Yanyan Jiang
a5048b3fa3
start pte refactor
2018-08-07 14:29:49 +00:00
Yanyan Jiang
8d252dd744
fallback asyetest
2018-08-07 13:55:00 +00:00
Yanyan Jiang
ec3b705f13
Revert am-native timer changes
2018-08-07 08:59:29 +00:00
Yanyan Jiang
c52d2b767f
make gcc7 compile
2018-08-07 08:27:33 +00:00
Yanyan Jiang
447b80a6c5
revise pte api
2018-07-27 14:26:23 +08:00
Yanyan Jiang
22b61c2ab3
Merge branch 'syslab18.wtcc' into 'master'
...
Syslab18.wtcc
See merge request !162
2018-07-27 14:00:51 +08:00
Yanyan Jiang
8c536aade8
Merge branch 'native' into 'master'
...
Native
See merge request !160
2018-07-27 14:00:11 +08:00
141242068-ouxianfei
a3b104322a
Added clz testcase, add nop before and after cp0 instructions
2018-07-21 19:50:55 +08:00
141242068-ouxianfei
9e46fc035e
Merge branch 'syslab18.wtcc' of https://git.njuics.cn/syslab17/nexus-am into syslab18.wtcc
2018-07-16 19:19:06 +08:00
141242068-ouxianfei
d6cf840ac6
Add nop after mtc0
2018-07-16 19:16:06 +08:00
141242068-ouxianfei
5b5f25647e
Add interrupt, add t0 ~ t9 in irq_handle
2018-07-16 17:56:28 +08:00
Allen
9cd6e2c8fc
Rewrite cache-flush.c.
...
When switching from gcc5 to gcc7, we failed cache-flush.
After rewriting it, we passed it, I think it has something to do with
the operand evaluation ordering.
To be specefic, these two sentence:
* arr[fast_rand() & lengthMod] = fast_rand();
* nemu_assert(arr[fast_rand() & lengthMod] == fast_rand());
* The first fast_rand does not necessarily evaluate before the second
one, there may be some undefined or implementation defined behavior
here. I do not know for sure.
Rewrite it to be:
int idx = fast_rand() & lengthMod;
int result = fast_rand();
Now the first fast_rand will execute before the second one as fast_rand
has side effects, according to program order, the first one will be
evaluated first.
2018-07-10 09:45:40 +00:00
Allen
d2cfb30899
Modified cache-flush and added access-cache test.
2018-07-09 13:14:45 +00:00
Allen
ac2b069106
Added several tests to cputest to test:div and cache.
2018-07-09 13:14:02 +00:00
Allen
6bcbe286a6
Fixed bit in cputest: do not read uninitialized memory.
2018-07-09 13:13:12 +00:00
Allen
e3d8e8231f
Fixed the access violation.
...
Access violation caused gcc to generate lw for misaligned access.
2018-07-09 13:11:00 +00:00
141242068-ouxianfei
e4eb47451f
Add ps/2 keyboard
2018-07-09 17:24:47 +08:00
141242068-ouxianfei
2d93a2928e
AM-mips32-npc with cp0_base
2018-07-05 11:34:42 +08:00