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apps,litenes: clean up

This commit is contained in:
Zihao Yu 2019-04-29 02:10:41 +08:00
parent b6ccd9e998
commit a3a875bb7a
8 changed files with 25 additions and 312 deletions
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7
apps/litenes/include/common.h
View File

@ -15,13 +15,6 @@ typedef int bool;
// #define log(fmt, ...) printk("%s:%d: " fmt, __func__, __LINE__, ## __VA_ARGS__)
#define log(fmt, ...)
static inline uint32_t pixel(uint8_t r, uint8_t g, uint8_t b) {
return (r << 16) | (g << 8) | b;
}
static inline uint8_t R(uint32_t p) { return p >> 16; }
static inline uint8_t G(uint32_t p) { return p >> 8; }
static inline uint8_t B(uint32_t p) { return p; }
// Byte Bit Operations
void common_set_bitb(byte *variable, byte position);
void common_unset_bitb(byte *variable, byte position);

4
apps/litenes/include/cpu.h
View File

@ -44,8 +44,4 @@ typedef struct {
int P[8]; // Expended Flag Register
} CPU_STATE;
extern CPU_STATE cpu;
extern byte CPU_RAM[0x8000];
#endif

7
apps/litenes/include/memory.h
View File

@ -32,11 +32,8 @@ static inline void memory_writeb(uint32_t address, uint32_t byte_data) {
else if (idx == 1) { ppu_io_write(address, byte_data); }
else if (idx == 2) {
if (address == 0x4014) {
// DMA transfer
int i;
for (i = 0; i < 256; i++) {
ppu_sprram_write(cpu_ram_read((0x100 * (byte_data & 0xff)) + i));
}
extern void W4014(uint32_t address, byte data);
W4014(address, byte_data);
}
else psg_io_write(address, byte_data);
}

28
apps/litenes/include/ppu.h
View File

@ -3,10 +3,7 @@
#ifndef PPU_H
#define PPU_H
extern byte PPU_RAM[0x4000];
void ppu_init();
void ppu_finish();
int ppu_read_idx(void);
@ -14,16 +11,10 @@ byte ppu_io_read(word address);
void ppu_io_write(word address, byte data);
bool ppu_generates_nmi();
void ppu_set_generates_nmi(bool yesno);
void ppu_set_mirroring(byte mirroring);
//void ppu_run(int cycles);
void ppu_cycle();
int ppu_scanline();
void ppu_set_scanline(int s);
void ppu_copy(word address, byte *source, int length);
void ppu_sprram_write(byte data);
// PPU Memory and State
typedef struct {
@ -46,23 +37,4 @@ typedef struct {
int x, scanline;
} PPU_STATE;
extern PPU_STATE ppu;
extern byte ppu_latch;
extern bool ppu_sprite_hit_occured;
// Screen State and Rendering
static inline byte ppu_l_h_addition(int h, int l, int x) {
return (((h >> (7 - x)) & 1) << 1) | ((l >> (7 - x)) & 1);
}
static inline byte ppu_l_h_addition_flip(int l, int h, int x) {
return (((h >> x) & 1) << 1) | ((l >> x) & 1);
}
// Draws current screen pixels in ppu_background_pixels & ppu_sprite_pixels and clears them
void ppu_render_screen();
void ppu_set_background_color(byte color);
#endif

2
apps/litenes/include/psg.h
View File

@ -6,8 +6,6 @@
#ifndef PSG_H
#define PSG_H
extern unsigned char psg_joy1[8];
byte psg_io_read(word address);
void psg_io_write(word address, byte data);

246
apps/litenes/src/cpu.c
View File

@ -5,7 +5,7 @@
//#define STATISTIC
CPU_STATE cpu;
static CPU_STATE cpu;
//int op_cycles; // Additional instruction cycles used (e.g. when paging occurs)
@ -30,16 +30,6 @@ static int cycle_table[256] = {
/*0xF0*/ 2,5,2,8,4,4,6,6,2,4,2,7,4,4,7,7,
};
//static void (*cpu_op_address_mode[256])(); // Array of address modes
//static void (*cpu_op_handler[256])(); // Array of instruction function pointers
//bool cpu_op_in_base_instruction_set[256]; // true if instruction is in base 6502 instruction set
//char *cpu_op_name[256]; // Instruction names
//static int cpu_op_cycles[256]; // CPU cycles used by instructions
// If OP_TRACE, print current instruction with all registers into the console
void cpu_trace_instruction();
// CPU Adressing Modes
#define cpu_address_implied(exec) { exec(true); }
@ -615,240 +605,6 @@ static inline void ____FE____() { /* Instruction for future Extension */ }
void cpu_init()
{
/*
CPU_OP_BIS(00, 7, brk, "BRK", implied)
CPU_OP_BIS(01, 6, ora, "ORA", indirect_x)
CPU_OP_BIS(05, 3, ora, "ORA", zero_page)
CPU_OP_BIS(06, 5, asl, "ASL", zero_page)
CPU_OP_BIS(08, 3, php, "PHP", implied)
CPU_OP_BIS(09, 2, ora, "ORA", immediate)
CPU_OP_BIS(0A, 2, asla,"ASL", implied)
CPU_OP_BIS(0D, 4, ora, "ORA", absolute)
CPU_OP_BIS(0E, 6, asl, "ASL", absolute)
CPU_OP_BIS(10, 2, bpl, "BPL", relative)
CPU_OP_BIS(11, 5, ora, "ORA", indirect_y)
CPU_OP_BIS(15, 4, ora, "ORA", zero_page_x)
CPU_OP_BIS(16, 6, asl, "ASL", zero_page_x)
CPU_OP_BIS(18, 2, clc, "CLC", implied)
CPU_OP_BIS(19, 4, ora, "ORA", absolute_y)
CPU_OP_BIS(1D, 4, ora, "ORA", absolute_x)
CPU_OP_BIS(1E, 7, asl, "ASL", absolute_x)
CPU_OP_BIS(20, 6, jsr, "JSR", absolute)
CPU_OP_BIS(21, 6, and, "AND", indirect_x)
CPU_OP_BIS(24, 3, bit, "BIT", zero_page)
CPU_OP_BIS(25, 3, and, "AND", zero_page)
CPU_OP_BIS(26, 5, rol, "ROL", zero_page)
CPU_OP_BIS(28, 4, plp, "PLP", implied)
CPU_OP_BIS(29, 2, and, "AND", immediate)
CPU_OP_BIS(2A, 2, rola,"ROL", implied)
CPU_OP_BIS(2C, 4, bit, "BIT", absolute)
CPU_OP_BIS(2D, 2, and, "AND", absolute)
CPU_OP_BIS(2E, 6, rol, "ROL", absolute)
CPU_OP_BIS(30, 2, bmi, "BMI", relative)
CPU_OP_BIS(31, 5, and, "AND", indirect_y)
CPU_OP_BIS(35, 4, and, "AND", zero_page_x)
CPU_OP_BIS(36, 6, rol, "ROL", zero_page_x)
CPU_OP_BIS(38, 2, sec, "SEC", implied)
CPU_OP_BIS(39, 4, and, "AND", absolute_y)
CPU_OP_BIS(3D, 4, and, "AND", absolute_x)
CPU_OP_BIS(3E, 7, rol, "ROL", absolute_x)
CPU_OP_BIS(40, 6, rti, "RTI", implied)
CPU_OP_BIS(41, 6, eor, "EOR", indirect_x)
CPU_OP_BIS(45, 3, eor, "EOR", zero_page)
CPU_OP_BIS(46, 5, lsr, "LSR", zero_page)
CPU_OP_BIS(48, 3, pha, "PHA", implied)
CPU_OP_BIS(49, 2, eor, "EOR", immediate)
CPU_OP_BIS(4A, 2, lsra,"LSR", implied)
CPU_OP_BIS(4C, 3, jmp, "JMP", absolute)
CPU_OP_BIS(4D, 4, eor, "EOR", absolute)
CPU_OP_BIS(4E, 6, lsr, "LSR", absolute)
CPU_OP_BIS(50, 2, bvc, "BVC", relative)
CPU_OP_BIS(51, 5, eor, "EOR", indirect_y)
CPU_OP_BIS(55, 4, eor, "EOR", zero_page_x)
CPU_OP_BIS(56, 6, lsr, "LSR", zero_page_x)
CPU_OP_BIS(58, 2, cli, "CLI", implied)
CPU_OP_BIS(59, 4, eor, "EOR", absolute_y)
CPU_OP_BIS(5D, 4, eor, "EOR", absolute_x)
CPU_OP_BIS(5E, 7, lsr, "LSR", absolute_x)
CPU_OP_BIS(60, 6, rts, "RTS", implied)
CPU_OP_BIS(61, 6, adc, "ADC", indirect_x)
CPU_OP_BIS(65, 3, adc, "ADC", zero_page)
CPU_OP_BIS(66, 5, ror, "ROR", zero_page)
CPU_OP_BIS(68, 4, pla, "PLA", implied)
CPU_OP_BIS(69, 2, adc, "ADC", immediate)
CPU_OP_BIS(6A, 2, rora,"ROR", implied)
CPU_OP_BIS(6C, 5, jmp, "JMP", indirect)
CPU_OP_BIS(6D, 4, adc, "ADC", absolute)
CPU_OP_BIS(6E, 6, ror, "ROR", absolute)
CPU_OP_BIS(70, 2, bvs, "BVS", relative)
CPU_OP_BIS(71, 5, adc, "ADC", indirect_y)
CPU_OP_BIS(75, 4, adc, "ADC", zero_page_x)
CPU_OP_BIS(76, 6, ror, "ROR", zero_page_x)
CPU_OP_BIS(78, 2, sei, "SEI", implied)
CPU_OP_BIS(79, 4, adc, "ADC", absolute_y)
CPU_OP_BIS(7D, 4, adc, "ADC", absolute_x)
CPU_OP_BIS(7E, 7, ror, "ROR", absolute_x)
CPU_OP_BIS(81, 6, sta, "STA", indirect_x)
CPU_OP_BIS(84, 3, sty, "STY", zero_page)
CPU_OP_BIS(85, 3, sta, "STA", zero_page)
CPU_OP_BIS(86, 3, stx, "STX", zero_page)
CPU_OP_BIS(88, 2, dey, "DEY", implied)
CPU_OP_BIS(8A, 2, txa, "TXA", implied)
CPU_OP_BIS(8C, 4, sty, "STY", absolute)
CPU_OP_BIS(8D, 4, sta, "STA", absolute)
CPU_OP_BIS(8E, 4, stx, "STX", absolute)
CPU_OP_BIS(90, 2, bcc, "BCC", relative)
CPU_OP_BIS(91, 6, sta, "STA", indirect_y)
CPU_OP_BIS(94, 4, sty, "STY", zero_page_x)
CPU_OP_BIS(95, 4, sta, "STA", zero_page_x)
CPU_OP_BIS(96, 4, stx, "STX", zero_page_y)
CPU_OP_BIS(98, 2, tya, "TYA", implied)
CPU_OP_BIS(99, 5, sta, "STA", absolute_y)
CPU_OP_BIS(9A, 2, txs, "TXS", implied)
CPU_OP_BIS(9D, 5, sta, "STA", absolute_x)
CPU_OP_BIS(A0, 2, ldy, "LDY", immediate)
CPU_OP_BIS(A1, 6, lda, "LDA", indirect_x)
CPU_OP_BIS(A2, 2, ldx, "LDX", immediate)
CPU_OP_BIS(A4, 3, ldy, "LDY", zero_page)
CPU_OP_BIS(A5, 3, lda, "LDA", zero_page)
CPU_OP_BIS(A6, 3, ldx, "LDX", zero_page)
CPU_OP_BIS(A8, 2, tay, "TAY", implied)
CPU_OP_BIS(A9, 2, lda, "LDA", immediate)
CPU_OP_BIS(AA, 2, tax, "TAX", implied)
CPU_OP_BIS(AC, 4, ldy, "LDY", absolute)
CPU_OP_BIS(AD, 4, lda, "LDA", absolute)
CPU_OP_BIS(AE, 4, ldx, "LDX", absolute)
CPU_OP_BIS(B0, 2, bcs, "BCS", relative)
CPU_OP_BIS(B1, 5, lda, "LDA", indirect_y)
CPU_OP_BIS(B4, 4, ldy, "LDY", zero_page_x)
CPU_OP_BIS(B5, 4, lda, "LDA", zero_page_x)
CPU_OP_BIS(B6, 4, ldx, "LDX", zero_page_y)
CPU_OP_BIS(B8, 2, clv, "CLV", implied)
CPU_OP_BIS(B9, 4, lda, "LDA", absolute_y)
CPU_OP_BIS(BA, 2, tsx, "TSX", implied)
CPU_OP_BIS(BC, 4, ldy, "LDY", absolute_x)
CPU_OP_BIS(BD, 4, lda, "LDA", absolute_x)
CPU_OP_BIS(BE, 4, ldx, "LDX", absolute_y)
CPU_OP_BIS(C0, 2, cpy, "CPY", immediate)
CPU_OP_BIS(C1, 6, cmp, "CMP", indirect_x)
CPU_OP_BIS(C4, 3, cpy, "CPY", zero_page)
CPU_OP_BIS(C5, 3, cmp, "CMP", zero_page)
CPU_OP_BIS(C6, 5, dec, "DEC", zero_page)
CPU_OP_BIS(C8, 2, iny, "INY", implied)
CPU_OP_BIS(C9, 2, cmp, "CMP", immediate)
CPU_OP_BIS(CA, 2, dex, "DEX", implied)
CPU_OP_BIS(CC, 4, cpy, "CPY", absolute)
CPU_OP_BIS(CD, 4, cmp, "CMP", absolute)
CPU_OP_BIS(CE, 6, dec, "DEC", absolute)
CPU_OP_BIS(D0, 2, bne, "BNE", relative)
CPU_OP_BIS(D1, 5, cmp, "CMP", indirect_y)
CPU_OP_BIS(D5, 4, cmp, "CMP", zero_page_x)
CPU_OP_BIS(D6, 6, dec, "DEC", zero_page_x)
CPU_OP_BIS(D8, 2, cld, "CLD", implied)
CPU_OP_BIS(D9, 4, cmp, "CMP", absolute_y)
CPU_OP_BIS(DD, 4, cmp, "CMP", absolute_x)
CPU_OP_BIS(DE, 7, dec, "DEC", absolute_x)
CPU_OP_BIS(E0, 2, cpx, "CPX", immediate)
CPU_OP_BIS(E1, 6, sbc, "SBC", indirect_x)
CPU_OP_BIS(E4, 3, cpx, "CPX", zero_page)
CPU_OP_BIS(E5, 3, sbc, "SBC", zero_page)
CPU_OP_BIS(E6, 5, inc, "INC", zero_page)
CPU_OP_BIS(E8, 2, inx, "INX", implied)
CPU_OP_BIS(E9, 2, sbc, "SBC", immediate)
CPU_OP_BIS(EA, 2, nop, "NOP", implied)
CPU_OP_BIS(EC, 4, cpx, "CPX", absolute)
CPU_OP_BIS(ED, 4, sbc, "SBC", absolute)
CPU_OP_BIS(EE, 6, inc, "INC", absolute)
CPU_OP_BIS(F0, 2, beq, "BEQ", relative)
CPU_OP_BIS(F1, 5, sbc, "SBC", indirect_y)
CPU_OP_BIS(F5, 4, sbc, "SBC", zero_page_x)
CPU_OP_BIS(F6, 6, inc, "INC", zero_page_x)
CPU_OP_BIS(F8, 2, sed, "SED", implied)
CPU_OP_BIS(F9, 4, sbc, "SBC", absolute_y)
CPU_OP_BIS(FD, 4, sbc, "SBC", absolute_x)
CPU_OP_BIS(FE, 7, inc, "INC", absolute_x)
CPU_OP_EIS(03, 8, aso, "SLO", indirect_x)
CPU_OP_EIS(07, 5, aso, "SLO", zero_page)
CPU_OP_EIS(0F, 6, aso, "SLO", absolute)
CPU_OP_EIS(13, 8, aso, "SLO", indirect_y)
CPU_OP_EIS(17, 6, aso, "SLO", zero_page_x)
CPU_OP_EIS(1B, 7, aso, "SLO", absolute_y)
CPU_OP_EIS(1F, 7, aso, "SLO", absolute_x)
CPU_OP_EIS(23, 8, rla, "RLA", indirect_x)
CPU_OP_EIS(27, 5, rla, "RLA", zero_page)
CPU_OP_EIS(2F, 6, rla, "RLA", absolute)
CPU_OP_EIS(33, 8, rla, "RLA", indirect_y)
CPU_OP_EIS(37, 6, rla, "RLA", zero_page_x)
CPU_OP_EIS(3B, 7, rla, "RLA", absolute_y)
CPU_OP_EIS(3F, 7, rla, "RLA", absolute_x)
CPU_OP_EIS(43, 8, lse, "SRE", indirect_x)
CPU_OP_EIS(47, 5, lse, "SRE", zero_page)
CPU_OP_EIS(4F, 6, lse, "SRE", absolute)
CPU_OP_EIS(53, 8, lse, "SRE", indirect_y)
CPU_OP_EIS(57, 6, lse, "SRE", zero_page_x)
CPU_OP_EIS(5B, 7, lse, "SRE", absolute_y)
CPU_OP_EIS(5F, 7, lse, "SRE", absolute_x)
CPU_OP_EIS(63, 8, rra, "RRA", indirect_x)
CPU_OP_EIS(67, 5, rra, "RRA", zero_page)
CPU_OP_EIS(6F, 6, rra, "RRA", absolute)
CPU_OP_EIS(73, 8, rra, "RRA", indirect_y)
CPU_OP_EIS(77, 6, rra, "RRA", zero_page_x)
CPU_OP_EIS(7B, 7, rra, "RRA", absolute_y)
CPU_OP_EIS(7F, 7, rra, "RRA", absolute_x)
CPU_OP_EIS(83, 6, axs, "SAX", indirect_x)
CPU_OP_EIS(87, 3, axs, "SAX", zero_page)
CPU_OP_EIS(8F, 4, axs, "SAX", absolute)
CPU_OP_EIS(93, 6, axa, "SAX", indirect_y)
CPU_OP_EIS(97, 4, axs, "SAX", zero_page_y)
CPU_OP_EIS(9F, 5, axa, "SAX", absolute_y)
CPU_OP_EIS(A3, 6, lax, "LAX", indirect_x)
CPU_OP_EIS(A7, 3, lax, "LAX", zero_page)
CPU_OP_EIS(AF, 4, lax, "LAX", absolute)
CPU_OP_EIS(B3, 5, lax, "LAX", indirect_y)
CPU_OP_EIS(B7, 4, lax, "LAX", zero_page_y)
CPU_OP_EIS(BF, 4, lax, "LAX", absolute_y)
CPU_OP_EIS(C3, 8, dcm, "DCP", indirect_x)
CPU_OP_EIS(C7, 5, dcm, "DCP", zero_page)
CPU_OP_EIS(CF, 6, dcm, "DCP", absolute)
CPU_OP_EIS(D3, 8, dcm, "DCP", indirect_y)
CPU_OP_EIS(D7, 6, dcm, "DCP", zero_page_x)
CPU_OP_EIS(DB, 7, dcm, "DCP", absolute_y)
CPU_OP_EIS(DF, 7, dcm, "DCP", absolute_x)
CPU_OP_EIS(E3, 8, ins, "ISB", indirect_x)
CPU_OP_EIS(E7, 5, ins, "ISB", zero_page)
CPU_OP_EIS(EB, 2, sbc, "SBC", immediate)
CPU_OP_EIS(EF, 6, ins, "ISB", absolute)
CPU_OP_EIS(F3, 8, ins, "ISB", indirect_y)
CPU_OP_EIS(F7, 6, ins, "ISB", zero_page_x)
CPU_OP_EIS(FB, 7, ins, "ISB", absolute_y)
CPU_OP_EIS(FF, 7, ins, "ISB", absolute_x)
CPU_OP_NII(04, zero_page)
CPU_OP_NII(0C, absolute)
CPU_OP_NII(14, zero_page_x)
CPU_OP_NII(1A, implied)
CPU_OP_NII(1C, absolute_x)
CPU_OP_NII(34, zero_page_x)
CPU_OP_NII(3A, implied)
CPU_OP_NII(3C, absolute_x)
CPU_OP_NII(44, zero_page)
CPU_OP_NII(54, zero_page_x)
CPU_OP_NII(5A, implied)
CPU_OP_NII(5C, absolute_x)
CPU_OP_NII(64, zero_page)
CPU_OP_NII(74, zero_page_x)
CPU_OP_NII(7A, implied)
CPU_OP_NII(7C, absolute_x)
CPU_OP_NII(80, immediate)
CPU_OP_NII(D4, zero_page_x)
CPU_OP_NII(DA, implied)
CPU_OP_NII(DC, absolute_x)
CPU_OP_NII(F4, zero_page_x)
CPU_OP_NII(FA, implied)
CPU_OP_NII(FC, absolute_x)
*/
//cpu.P = 0x24;
cpu.P[interrupt_bp] = 1;
cpu.P[unused_bp] = 1;

4
apps/litenes/src/mmc.c
View File

@ -6,8 +6,8 @@
byte mmc_id;
byte mmc_chr_pages[MMC_MAX_PAGE_COUNT][0x2000];
int mmc_chr_pages_number;
static byte mmc_chr_pages[MMC_MAX_PAGE_COUNT][0x2000];
static int mmc_chr_pages_number;
byte memory[0x10000];

39
apps/litenes/src/ppu.c
View File

@ -7,6 +7,13 @@
#define PROFILE
static PPU_STATE ppu;
static byte PPU_RAM[0x4000];
static bool ppu_2007_first_read;
static byte ppu_addr_latch;
static bool ppu_sprite_hit_occured = false;
static uint16_t ppu_screen_background[264][264 / 8];
static const word ppu_base_nametable_addresses[4] = { 0x2000, 0x2400, 0x2800, 0x2C00 };
// sprite
@ -16,19 +23,22 @@ typedef struct {
} SPR;
static const SPR *spr_array = (void *)PPU_SPRRAM;
byte PPU_RAM[0x4000];
bool ppu_2007_first_read;
byte ppu_addr_latch;
PPU_STATE ppu;
byte ppu_latch;
bool ppu_sprite_hit_occured = false;
uint16_t ppu_screen_background[264][264 / 8];
static inline void ppu_sprram_write(byte data) {
PPU_SPRRAM[ppu.OAMADDR++] = data;
}
void W4014(uint32_t address, byte data) {
// DMA transfer
extern byte CPU_RAM[0x8000];
int i;
for (i = 0; i < 256; i++) {
ppu_sprram_write(CPU_RAM[(0x100 * data) + i]);
}
}
// preprocess tables
static byte XHL[256 * 256][8]; // each valus is 0~3
static uint32_t ppu_ram_map[0x4000];
static uint16_t XHL16[256 * 256];
static uint16_t XHLmask16[256 * 256];
@ -427,22 +437,20 @@ inline byte ppu_io_read(word address)
ppu.scroll_received_x = 0;
ppu.PPUSCROLL = 0;
ppu.addr_received_high_byte = 0;
ppu_latch = value;
ppu_addr_latch = 0;
ppu_2007_first_read = true;
return value;
}
case 4: return ppu_latch = PPU_SPRRAM[ppu.OAMADDR];
case 4: return PPU_SPRRAM[ppu.OAMADDR];
case 7:
{
byte data;
if (ppu.PPUADDR < 0x3F00) {
data = ppu_latch = ppu_ram_read_fast(ppu.PPUADDR);
data = ppu_ram_read_fast(ppu.PPUADDR);
}
else {
data = ppu_ram_read(ppu.PPUADDR);
ppu_latch = 0;
}
if (ppu_2007_first_read) {
@ -462,7 +470,6 @@ inline byte ppu_io_read(word address)
inline void ppu_io_write(word address, byte data)
{
address &= 7;
ppu_latch = data;
switch(address) {
case 0: if (ppu.ready) ppu_update_PPUCTRL_internal(data); break;
case 1: if (ppu.ready) byte_unpack(ppu.PPUMASK, data);
@ -512,7 +519,6 @@ inline void ppu_io_write(word address, byte data)
ppu.PPUADDR &= 0x3FFF;
}
}
ppu_latch = data;
}
void ppu_init()
@ -526,11 +532,6 @@ void ppu_init()
table_init();
}
void ppu_sprram_write(byte data)
{
PPU_SPRRAM[ppu.OAMADDR++] = data;
}
void ppu_set_background_color(byte color)
{
}