Add bitmanip and crypto test

tests/bitmanip/Makefile

@@ -0,0 +1,3 @@
+NAME = Bitasm
+SRCS = $(shell find -L ./src/ -name "*.S")
+include $(AM_HOME)/Makefile.app

tests/bitmanip/include/extB.S.include

@@ -0,0 +1,554 @@
+# Macro Assembler
+# RD  @7
+# RS1 @15
+# RS2 @20
+# CU5 @20
+# CU7 @20
+
+# DECODE_ENTRY(0, XPERMN,     "|0010100|.....|.....|010|.....|0110011|"); 
+.macro XPERMN rd rs1 rs2
+    .int 0x28002033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, XPERMB,     "|0010100|.....|.....|100|.....|0110011|"); 
+.macro XPERMB rd rs1 rs2
+    .int 0x28004033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, CLZ,     "|0110000|00000|.....|001|.....|0010011|"); // OP-IMM (no space)
+.macro CLZ rd rs1
+    .int 0x60001013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15)
+.endm
+
+# DECODE_ENTRY(0, CTZ,     "|0110000|00001|.....|001|.....|0010011|"); // OP-IMM (no space)
+.macro CTZ rd rs1
+    .int 0x60101013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15)
+.endm
+
+# DECODE_ENTRY(0, PCNT,    "|0110000|00010|.....|001|.....|0010011|"); // OP-IMM (no space)
+.macro PCNT rd rs1
+    .int 0x60201013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15)
+.endm
+
+# DECODE_ENTRY(0, SEXTB,    "|0110000|00100|.....|001|.....|0010011|");  // R-type
+.macro SEXTB rd rs1
+    .int 0x60401013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) 
+.endm
+
+# DECODE_ENTRY(0, SEXTH,    "|0110000|00101|.....|001|.....|0010011|");  // R-type
+.macro SEXTH rd rs1
+    .int 0x60501013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) 
+.endm
+
+# DECODE_ENTRY(0, ANDN,    "|0100000|.....|.....|111|.....|0110011|"); // OP
+.macro ANDN rd rs1 rs2
+    .int 0x40007033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SLO,     "|0010000|.....|.....|001|.....|0110011|"); // OP
+.macro SLO rd rs1 rs2
+    .int 0x20001033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SRO,     "|0010000|.....|.....|101|.....|0110011|"); // OP
+.macro SRO rd rs1 rs2
+    .int 0x20005033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SLOI,    "|10...|.......|.....|000|.....|0001011|"); // OP-IMM
+.macro SLOI rd rs1 imm
+    .int 0x20001013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x3F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SROI,    "|00100|.......|.....|101|.....|0010011|"); // OP-IMM
+.macro SROI rd rs1 imm
+    .int 0x20005013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x3F)<<20)
+.endm
+
+# DECODE_ENTRY(0, ROL,      "|0110000|.....|.....|001|.....|0110011|");  // R-type
+.macro ROL rd rs1 rs2
+    .int 0x60001033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, ROR,     "|0110000|.....|.....|101|.....|0110011|"); // OP
+.macro ROR rd rs1 rs2
+    .int 0x60005033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, RORI,    "|01100|.......|.....|101|.....|0010011|"); // OP-IMM
+.macro RORI rd rs1 imm
+    .int 0x60005013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x3F)<<20)
+.endm
+
+# DECODE_ENTRY(0, GREV,    "|0110100|.....|.....|101|.....|0110011|");  // R-type
+.macro GREV rd rs1 rs2
+    .int 0x68005033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm    
+
+# DECODE32_ENTRY(0, GORC,  "|0010100|.....|.....|101|.....|0110011|"),
+.macro GORC rd rs1 rs2
+    .int 0x28005033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm    
+
+# DECODE_ENTRY(0, GREVI,   "|01101|.......|.....|101|.....|0010011|");  // I-type
+.macro GREVI rd rs1 imm
+    .int 0x68005013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x3F)<<20)
+.endm
+
+# DECODE32_ENTRY(0, GORCI, "|00101|0......|.....|101|.....|0010011|")
+.macro GORCI rd rs1 imm
+    .int 0x28005013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x3F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SHFL,    "|0000100|.....|.....|001|.....|0110011|"); // OP
+.macro SHFL rd rs1 rs2
+    .int 0x08001033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm    
+
+# DECODE_ENTRY(0, UNSHFL,  "|0000100|.....|.....|101|.....|0110011|"); // OP
+.macro UNSHFL rd rs1 rs2
+    .int 0x08005033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm 
+
+# DECODE_ENTRY(0, SHFLI,   "|000010|......|.....|001|.....|0010011|"); // OP-IMM
+.macro SHFLI rd rs1 imm
+    .int 0x08001013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x3F)<<20)
+.endm
+
+# DECODE_ENTRY(0, UNSHFLI,  "|000010|......|.....|101|.....|0010011|"); // I-type (UNDEF)
+.macro UNSHFLI rd rs1 imm
+    .int 0x08005013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x3F)<<20)
+.endm
+
+# DECODE_ENTRY(0, BEXT,     "|0000100|.....|.....|110|.....|0110011|");  // R-type
+.macro BEXT rd rs1 rs2
+    .int 0x08006033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm    
+
+# DECODE_ENTRY(0, BDEP,    "|0100100|.....|.....|110|.....|0110011|");  // R-type
+.macro BDEP rd rs1 rs2
+    .int 0x48006033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, CMIX,     "|.....|11|.....|.....|001|.....|0110011|"); // R4-type
+.macro CMIX rd rs1 rs2 rs3
+    .int 0x06001033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20) | ((\rs3&0x1F)<<27)
+.endm
+
+# DECODE_ENTRY(0, CMOV,     "|.....|11|.....|.....|101|.....|0110011|"); // R4-type
+.macro CMOV rd rs1 rs2 rs3
+    .int 0x06005033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20) | ((\rs3&0x1F)<<27)
+.endm
+
+# DECODE_ENTRY(0, CLMUL,    "|0000101|.....|.....|001|.....|0110011|"); // OP
+.macro CLMUL rd rs1 rs2
+    .int 0x0A001033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, CLMULR,   "|0000101|.....|.....|010|.....|0110011|"); // OP
+.macro CLMULR rd rs1 rs2
+    .int 0x0A002033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, CLMULH,   "|0000101|.....|.....|011|.....|0110011|");  // R-type
+.macro CLMULH rd rs1 rs2
+    .int 0x0A003033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, FSL,     "|.....|10|.....|.....|001|.....|0110011|"); // R4-type
+.macro FSL rd rs1 rs2 rs3
+    .int 0x04001033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20) | ((\rs3&0x1F)<<27)
+.endm
+
+# DECODE_ENTRY(0, FSRI,     "|.....1.|.....|.....|101|.....|0010011|"); // R4-type
+.macro FSRI rd rs1 imm rs3
+    .int 0x04005013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x3F)<<20) | ((\rs3&0x1F)<<27)
+.endm
+
+# DECODE_ENTRY(0, FSR,     "|.....|10|.....|.....|101|.....|0110011|"); // R4-type
+.macro FSR rd rs1 rs2 rs3
+    .int 0x04005033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20) | ((\rs3&0x1F)<<27)
+.endm
+
+# DECODE_ENTRY(0, MIN,    "|0000101|.....|.....|100|.....|0110011|"); // OP
+.macro MIN rd rs1 rs2
+    .int 0x0A004033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, MAX,    "|0000101|.....|.....|110|.....|0110011|"); // OP
+.macro MAX rd rs1 rs2
+    .int 0x0A006033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, MINU,   "|0000101|.....|.....|101|.....|0110011|"); // OP
+.macro MINU rd rs1 rs2
+    .int 0x0A005033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, MAXU,   "|0000101|.....|.....|111|.....|0110011|"); // OP
+.macro MAXU rd rs1 rs2
+    .int 0x0A007033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, CRC32_B,  "|0110000|10000|.....|001|.....|0010011|"); // R-type
+.macro CRC32_B rd rs1
+    .int 0x61001013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15)
+.endm
+
+# DECODE_ENTRY(0, CRC32_H,  "|0110000|10001|.....|001|.....|0010011|"); // R-type
+.macro CRC32_H rd rs1
+    .int 0x61101013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15)
+.endm
+
+# DECODE_ENTRY(0, CRC32_W,  "|0110000|10010|.....|001|.....|0010011|"); // R-type
+.macro CRC32_W rd rs1
+    .int 0x61201013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15)
+.endm
+
+# DECODE_ENTRY(0, CRC32_D,  "|0110000|10011|.....|001|.....|0010011|");  // R-type
+.macro CRC32_D rd rs1
+    .int 0x61301013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15)
+.endm
+
+# DECODE_ENTRY(0, CRC32C_B, "|0110000|11000|.....|001|.....|0010011|"); // R-type
+.macro CRC32C_B rd rs1
+    .int 0x61801013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15)
+.endm
+
+# DECODE_ENTRY(0, CRC32C_H, "|0110000|11001|.....|001|.....|0010011|"); // R-type
+.macro CRC32C_H rd rs1
+    .int 0x61901013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15)
+.endm
+
+# DECODE_ENTRY(0, CRC32C_W, "|0110000|11010|.....|001|.....|0010011|"); // R-type
+.macro CRC32C_W rd rs1
+    .int 0x61A01013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15)
+.endm
+
+# DECODE_ENTRY(0, CRC32C_D, "|0110000|11011|.....|001|.....|0010011|");  // R-type
+.macro CRC32C_D rd rs1
+    .int 0x61B01013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15)
+.endm
+
+# DECODE_ENTRY(0, BMATXOR,  "|0100100|.....|.....|011|.....|0110011|");  // R-type
+.macro BMATXOR rd rs1 rs2
+    .int 0x48003033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, BMATOR,     "|0000100|.....|.....|011|.....|0110011|"); // OP
+.macro BMATOR rd rs1 rs2
+    .int 0x08003033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, BMATFLIP, "|0110000|00011|.....|001|.....|0010011|"); // R-type
+.macro BMATFLIP rd rs1
+    .int 0x60301013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15)
+.endm
+
+# DECODE_ENTRY(0, CRC32C_D, "|0110000|11011|.....|001|.....|0010011|"); // R-type
+
+# DECODE_ENTRY(0, NOT,  "|011|001|...|00000|01|");
+.macro CNOT rd
+    .short 0x6401 | ((\rd&0x7)<<7)
+.endm
+
+# DECODE_ENTRY(0, ORN,      "|0100000|.....|.....|110|.....|0110011|");  // R-type
+.macro ORN rd rs1 rs2
+    .int 0x40006033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, XNOR,     "|0100000|.....|.....|100|.....|0110011|");  // R-type
+.macro XNOR rd rs1 rs2
+    .int 0x40004033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SBSET,    "|0010100|.....|.....|001|.....|0110011|");  // R-type
+.macro SBSET rd rs1 rs2
+    .int 0x28001033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SBCLR,    "|0100100|.....|.....|001|.....|0110011|");  // R-type
+.macro SBCLR rd rs1 rs2
+    .int 0x48001033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SBINV,    "|0110100|.....|.....|001|.....|0110011|");  // R-type
+.macro SBINV rd rs1 rs2
+    .int 0x68001033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SBEXT,    "|0100100|.....|.....|101|.....|0110011|");  // R-type
+.macro SBEXT rd rs1 rs2
+    .int 0x48005033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SBSETI,   "|00101|.......|.....|001|.....|0010011|");  // I-type
+.macro SBSETI rd rs1 imm
+    .int 0x28001013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x3F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SBCLRI,   "|01001|.......|.....|001|.....|0010011|");  // I-type
+.macro SBCLRI rd rs1 imm
+    .int 0x48001013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x3F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SBINVI,   "|01101|.......|.....|001|.....|0010011|");  // I-type
+.macro SBINVI rd rs1 imm
+    .int 0x68001013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x3F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SBEXTI,   "|01001|.......|.....|101|.....|0010011|");  // I-type
+.macro SBEXTI rd rs1 imm
+    .int 0x48005013 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x3F)<<20)
+.endm
+
+# DECODE_ENTRY(0, ADDIWU,   "|............|.....|100|.....|0011011|");  // I-type
+.macro ADDIWU rd rs1 imm
+    .int 0x0000401B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x3FF)<<20)
+.endm
+
+# DECODE_ENTRY(0, SLLIU_W,  "|00001|.......|.....|001|.....|0011011|");  // I-type
+.macro SLLIU_W rd rs1 imm
+    .int 0x0800101B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x3F)<<20)
+.endm
+
+# DECODE_ENTRY(0, ADDU_W,   "|0000100|.....|.....|000|.....|0111011|");  // R-type
+.macro ADDUW rd rs1 rs2
+    .int 0x0800003B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SUBU_W,   "|0100100|.....|.....|000|.....|0111011|");  // R-type
+.macro SUBUW rd rs1 rs2
+    .int 0x4800003B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, ADDWU,    "|0000101|.....|.....|000|.....|0111011|");  // R-type
+.macro ADDWU rd rs1 rs2
+    .int 0x0A00003B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SH1ADD,    "|0010000|.....|.....|010|.....|0110011|");  // R-type
+.macro SH1ADD rd rs1 rs2
+    .int 0x20002033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SH1ADDWU,    "|0010000|.....|.....|010|.....|0111011|");  // R-type
+.macro SH1ADDUW rd rs1 rs2
+    .int 0x2000203B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SH2ADD,    "|0000101|.....|.....|100|.....|0110011|");  // R-type
+.macro SH2ADD rd rs1 rs2
+    .int 0x20004033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SH2ADDUW,    "|0000101|.....|.....|100|.....|0111011|");  // R-type
+.macro SH2ADDUW rd rs1 rs2
+    .int 0x2000403B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SH3ADD,    "|0000101|.....|.....|110|.....|0110011|");  // R-type
+.macro SH3ADD rd rs1 rs2
+    .int 0x20006033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SH3ADDUW,    "|0000101|.....|.....|110|.....|0111011|");  // R-type
+.macro SH3ADDUW rd rs1 rs2
+    .int 0x2000603B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+
+# DECODE_ENTRY(0, SUBWU,    "|0100101|.....|.....|000|.....|0111011|");  // R-type
+.macro SUBWU rd rs1 rs2
+    .int 0x4A00003B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, PACK,     "|0000100|.....|.....|100|.....|0110011|");  // R-type
+.macro PACK rd rs1 rs2
+    .int 0x08004033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, BFP,     "|0100100|.....|.....|111|.....|0110011|");  // R-type
+.macro BFP rd rs1 rs2
+    .int 0x48007033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, BFPW,     "|0100100|.....|.....|111|.....|0111011|");  // R-type
+.macro BFPW rd rs1 rs2
+    .int 0x4800703B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, GREVW,    "|0110100|.....|.....|101|.....|0111011|");  // R-type
+.macro GREVW rd rs1 rs2
+    .int 0x6800503B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE32_ENTRY(0, GORCW,  "|0010100|.....|.....|101|.....|0111011|");  // R-type
+.macro GORCW rd rs1 rs2
+    .int 0x2800503B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SLOW,     "|0010000|.....|.....|001|.....|0111011|");  // R-type
+.macro SLOW rd rs1 rs2
+    .int 0x2000103B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+    
+ # DECODE_ENTRY(0, SROW,    "|0010000|.....|.....|101|.....|0111011|");  // R-type
+.macro SROW rd rs1 rs2
+    .int 0x2000503B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+    
+# DECODE_ENTRY(0, ROLW,     "|0110000|.....|.....|001|.....|0111011|");  // R-type
+.macro ROLW rd rs1 rs2
+    .int 0x6000103B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, RORW,     "|0110000|.....|.....|101|.....|0111011|");  // R-type
+.macro RORW rd rs1 rs2
+    .int 0x6000503B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SBSETW,   "|0010100|.....|.....|001|.....|0111011|");  // R-type
+.macro SBSETW rd rs1 rs2
+    .int 0x2800103B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SBCLRW,   "|0100100|.....|.....|001|.....|0111011|");  // R-type
+.macro SBCLRW rd rs1 rs2
+    .int 0x4800103B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SBINVW,   "|0110100|.....|.....|001|.....|0111011|");  // R-type
+.macro SBINVW rd rs1 rs2
+    .int 0x6800103B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SBEXTW,   "|0100100|.....|.....|101|.....|0111011|");  // R-type
+.macro SBEXTW rd rs1 rs2
+    .int 0x4800503B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, GREVIW,   "|0110100|.....|.....|101|.....|0011011|");  // R-type
+.macro GREVIW rd rs1 imm
+    .int 0x6800501B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x1F)<<20)
+.endm
+
+# DECODE32_ENTRY(0, GORCIW, "|0010100|.....|.....|101|.....|0011011|");  // R-type
+.macro GORCIW rd rs1 imm
+    .int 0x2800501B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SLOIW,    "|0010000|.....|.....|001|.....|0011011|");  // R-type
+.macro SLOIW rd rs1 imm
+    .int 0x2000101B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SROIW,    "|0010000|.....|.....|101|.....|0011011|");  // R-type
+.macro SROIW rd rs1 imm
+    .int 0x2000501B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, RORIW,    "|0110000|.....|.....|101|.....|0011011|");  // R-type
+.macro RORIW rd rs1 imm
+    .int 0x6000501B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SBSETIW,  "|0010100|.....|.....|001|.....|0011011|");  // R-type
+.macro SBSETIW rd rs1 imm
+    .int 0x2800101B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SBCLRIW,  "|0100100|.....|.....|001|.....|0011011|");  // R-type
+.macro SBCLRIW rd rs1 imm
+    .int 0x4800101B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SBINVIW,  "|0110100|.....|.....|001|.....|0011011|");  // R-type
+.macro SBINVIW rd rs1 imm
+    .int 0x6800101B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, FSLW,     "|.....10|.....|.....|001|.....|0111011|"); // R4-type
+.macro FSLW rd rs1 rs2 rs3
+    .int 0x0400103B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20) | ((\rs3&0x1F)<<27)
+.endm
+
+# DECODE_ENTRY(0, FSRW,     "|.....10|.....|.....|101|.....|0111011|"); // R4-type
+.macro FSRW rd rs1 rs2 rs3
+    .int 0x0400503B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20) | ((\rs3&0x1F)<<27)
+.endm
+    
+# DECODE_ENTRY(0, FSRIW,    "|.....10|.....|.....|101|.....|0011011|"); // R4-type
+.macro FSRIW rd rs1 imm rs3
+    .int 0x0400501B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\imm&0x1F)<<20) | ((\rs3&0x1F)<<27)
+.endm
+
+# DECODE_ENTRY(0, CLZW,     "|0110000|00000|.....|001|.....|0011011|");  // R-type
+.macro CLZW rd rs1
+    .int 0x6000101B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15)
+.endm
+
+# DECODE_ENTRY(0, CTZW,     "|0110000|00001|.....|001|.....|0011011|");  // R-type
+.macro CTZW rd rs1
+    .int 0x6010101B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15)
+.endm
+
+# DECODE_ENTRY(0, PCNTW,    "|0110000|00010|.....|001|.....|0011011|");  // R-type
+.macro PCNTW rd rs1
+    .int 0x6020101B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15)
+.endm
+
+# DECODE_ENTRY(0, CLMULW,   "|0000101|.....|.....|001|.....|0111011|");  // R-type
+.macro CLMULW rd rs1 rs2
+    .int 0x0A00103B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, CLMULHW,  "|0000101|.....|.....|011|.....|0111011|");  // R-type
+.macro CLMULHW rd rs1 rs2
+    .int 0x0A00303B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, CLMULRW,  "|0000101|.....|.....|010|.....|0111011|");  // R-type
+.macro CLMULRW rd rs1 rs2
+    .int 0x0A00203B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, SHFLW,   "|0000100|.....|.....|001|.....|0111011|");  // R-type
+.macro SHFLW rd rs1 rs2
+    .int 0x0800103B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm    
+
+# DECODE_ENTRY(0, UNSHFLW, "|0000100|.....|.....|101|.....|0111011|");  // R-type
+.macro UNSHFLW rd rs1 rs2
+    .int 0x0800503B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm 
+
+# DECODE_ENTRY(0, BEXTW,    "|0000100|.....|.....|110|.....|0111011|");  // R-type
+.macro BEXTW rd rs1 rs2
+    .int 0x0800603B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm    
+
+# DECODE_ENTRY(0, BDEPW,   "|0100100|.....|.....|110|.....|0111011|");  // R-type
+.macro BDEPW rd rs1 rs2
+    .int 0x4800603B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, PACKW,    "|0000100|.....|.....|100|.....|0111011|");  // R-type
+.macro PACKW rd rs1 rs2
+    .int 0x0800403B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, PACKU,    "|0100100|.....|.....|100|.....|0110011|");  // R-type
+.macro PACKU rd rs1 rs2
+    .int 0x48004033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+
+# DECODE_ENTRY(0, PACKUW,    "|0100100|.....|.....|100|.....|0111011|");  // R-type
+.macro PACKUW rd rs1 rs2
+    .int 0x4800403B | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm
+   
+# DECODE_ENTRY(0, PACKH,    "|0000100|.....|.....|111|.....|0110011|");  // R-type
+.macro PACKH rd rs1 rs2
+    .int 0x08007033 | ((\rd&0x1F)<<7) | ((\rs1&0x1F)<<15) | ((\rs2&0x1F)<<20)
+.endm

tests/bitmanip/include/log.S

@@ -0,0 +1,883 @@
+# RISC-V Bit Manipulation Instruction Support
+#
+# Copyright (c) 2019, Imperas Software Ltd. Additions
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * the name of Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// -------------------------------------
+// COMMON FRAMEWORK FOR VALIDATION TESTS
+// -------------------------------------
+//
+// NOTES ON REGISTER USAGE
+// -----------------------
+// In accordance with the RISC-V ABI, registers are used as follows:
+//
+// Function Arguments (a0-a7)
+// --------------------------
+// Caller must save these if required.
+//
+// Function Return Values
+// ----------------------
+// Results are returned in a0 and a1 (if required).
+//
+// Temporaries
+// -----------
+// t0-t6 are available for use within a function. Caller must save these if
+// required.
+//
+// Preserved
+// ---------
+// s0-s11 are preserved within a function. Callee must save these if required.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+////////////////////////////////////////////////////////////////////////////////
+// INITIALIZE I/O
+////////////////////////////////////////////////////////////////////////////////
+
+.macro IO_INIT
+
+#if (USE_FU540_LOG==1)
+
+    #ifdef SIFIVE_FU540
+
+        // executing on board
+        csrr    t0, mhartid     // 4-byte op
+        li      t1, 4           // 2-byte op
+1:      bne     t1, t0, 1b      // 4-byte op
+        lui     t5, 0x10010     // 4-byte op
+        li      a0, 0x1         // 2-byte op
+        sw      a0, 8(t5)       // 4-byte op
+
+    #else
+
+        // board-compatible simulation
+        .word 0x00000013        // 4-byte nop (match board code size)
+        .word 0x00000013        // 4-byte nop (match board code size)
+        .word 0x00000013        // 4-byte nop (match board code size)
+        .word 0x00000013        // 4-byte nop (match board code size)
+        .word 0x00000013        // 4-byte nop (match board code size)
+
+    #endif
+
+#endif
+
+.endm
+
+////////////////////////////////////////////////////////////////////////////////
+// WRITE CHARACTER
+////////////////////////////////////////////////////////////////////////////////
+
+.macro IO_PUTC _R
+
+#if (USE_FU540_LOG!=1)
+
+        // normal test case simulation
+        .word 0x0005200B
+
+#else
+
+    #ifdef SIFIVE_FU540
+
+        // executing on board
+        lui         t5, 0x10010
+        L1\@:
+        lw          t6, (t5)
+        bnez        t6, L1\@
+        sw          \_R, (t5)
+
+    #else
+
+        // board-compatible simulation
+        lui         t5, 0x10010
+        lw          t6, (t5)
+        .word 0x00000013    // 4-byte nop (match board code size)
+        sw          \_R, (t5)
+//      .word 0x00000013    // 4-byte nop (match board code size)
+//      .word 0x00000013    // 4-byte nop (match board code size)
+//      .word 0x00000013    // 4-byte nop (match board code size)
+//      .word 0x0005200B
+
+    #endif
+
+#endif
+.endm
+
+        .globl  _start
+
+////////////////////////////////////////////////////////////////////////////////
+// JUMP TO START OF TEST
+////////////////////////////////////////////////////////////////////////////////
+
+_start:
+        IO_INIT
+        j       START_TEST
+
+////////////////////////////////////////////////////////////////////////////////
+// EXIT_TEST: terminate test (destroys a0)
+// NOTE: t5 and t6 may be used here as scratch registers if required
+////////////////////////////////////////////////////////////////////////////////
+
+#if (USE_FU540_LOG==1)
+
+    exit_test:
+    #ifdef SIFIVE_FU540
+
+        // executing on board
+        j exit_test         // 2-byte op
+        .word 0x00000013    // 4-byte nop (match simulator code size)
+
+    #else
+
+        // board-compatible simulation
+        li          a0,0    // 2-byte op
+        .word 0x0005200B    // 4-byte op
+
+    #endif
+
+#endif
+
+.macro EXIT_TEST
+#if (USE_FU540_LOG==1)
+
+        // executing on board or simulation of board
+        j exit_test
+#else
+
+        // normal test case simulation
+        li          a0,0
+        .word 0x0005200B
+
+#endif
+.endm
+
+////////////////////////////////////////////////////////////////////////////////
+// WRITE_A0: write character in a0
+// NOTE: t5 and t6 may be used here as scratch registers if required
+////////////////////////////////////////////////////////////////////////////////
+
+.macro WRITE_A0
+#ifdef SYS_QUIET
+        // Do nothing
+#else
+    IO_PUTC a0
+#endif
+.endm
+
+////////////////////////////////////////////////////////////////////////////////
+// WRITE_NL: write newline (destroys a0)
+////////////////////////////////////////////////////////////////////////////////
+
+.macro WRITE_NL
+        li          a0,10
+        WRITE_A0
+.endm
+
+////////////////////////////////////////////////////////////////////////////////
+// WRITE_RAW <gpr>: write raw register (destroys a0, t0-t2, lr)
+////////////////////////////////////////////////////////////////////////////////
+
+.macro WRITE_RAW _R
+#ifndef SYS_QUIET
+        mv          a0, \_R
+        jal         writeA0
+#endif
+.endm
+
+////////////////////////////////////////////////////////////////////////////////
+// WRITE_RAWS <gpr>: write raw register, short form with no leading zeros
+// (destroys a0, a1, a2, a3, lr)
+////////////////////////////////////////////////////////////////////////////////
+
+.macro WRITE_RAWS _R
+#ifndef SYS_QUIET
+        mv          a0, \_R
+        jal         writeA0Short
+#endif
+.endm
+
+////////////////////////////////////////////////////////////////////////////////
+// WRITE_S <string>: write string (destroys a0, t0, lr)
+////////////////////////////////////////////////////////////////////////////////
+
+.macro WRITE_S _R
+#ifndef SYS_QUIET
+        la          a0, \_R
+        jal         writeS
+#endif
+.endm
+
+////////////////////////////////////////////////////////////////////////////////
+// WRITE_LOG_N <string>: write log message without newline (destroys a0, t0, lr)
+////////////////////////////////////////////////////////////////////////////////
+
+.macro WRITE_LOG_N _M
+        WRITE_S     logM
+        WRITE_S     \_M
+.endm
+
+////////////////////////////////////////////////////////////////////////////////
+// WRITE_LOG <string>: write log message with newline (destroys a0, t0, lr)
+////////////////////////////////////////////////////////////////////////////////
+
+.macro WRITE_LOG _M
+        WRITE_LOG_N \_M
+        WRITE_NL
+.endm
+
+////////////////////////////////////////////////////////////////////////////////
+// GPR_LOG <gpr>: log gpr value with newline (destroys a0, t0-t2, lr)
+////////////////////////////////////////////////////////////////////////////////
+
+.macro GPR_LOG _GPR
+        mv          t2, \_GPR
+        WRITE_S     logM
+        WRITE_S     LABEL_\_GPR
+        WRITE_S     equalsXL
+        WRITE_RAW   t2
+        WRITE_NL
+.endm
+
+////////////////////////////////////////////////////////////////////////////////
+// FPR_LOG_S <gpr>: log SP fpr value with newline (destroys a0, t0-t2, lr)
+////////////////////////////////////////////////////////////////////////////////
+
+.macro FPR_LOG_S _FPR
+        fmv.x.s     t2, \_FPR
+        WRITE_S     logM
+        WRITE_S     LABEL_\_FPR
+        WRITE_S     equalsXL
+        WRITE_RAW   t2
+        WRITE_NL
+.endm
+
+////////////////////////////////////////////////////////////////////////////////
+// FPR_LOG_D <gpr>: log DP fpr value with newline (destroys a0, t0-t2, lr)
+////////////////////////////////////////////////////////////////////////////////
+
+.macro FPR_LOG_D _FPR
+        fmv.x.d     t2, \_FPR
+        WRITE_S     logM
+        WRITE_S     LABEL_\_FPR
+        WRITE_S     equalsXL
+        WRITE_RAW   t2
+        WRITE_NL
+.endm
+
+////////////////////////////////////////////////////////////////////////////////
+// CSR_R <gpr>, <csr>: log csr read to gpr (destroys a0, t0-t2, lr)
+////////////////////////////////////////////////////////////////////////////////
+
+.macro CSR_R _GPR, _CSR
+        csrr        \_GPR, \_CSR
+        WRITE_S     LABEL_\_CSR
+        WRITE_S     rarrowXL
+        WRITE_RAW   \_GPR
+.endm
+
+////////////////////////////////////////////////////////////////////////////////
+// CSR_R_LOG <gpr>, <csr>: log csr read to gpr (destroys a0, t0-t2, lr)
+////////////////////////////////////////////////////////////////////////////////
+
+.macro CSR_R_LOG_N _GPR, _CSR
+        csrr        \_GPR, \_CSR
+        WRITE_S     logM
+        WRITE_S     LABEL_\_CSR
+        WRITE_S     rarrowXL
+        WRITE_RAW   \_GPR
+.endm
+
+////////////////////////////////////////////////////////////////////////////////
+// CSR_R_LOG <gpr>, <csr>: log csr read to gpr (destroys a0, t0-t2, lr)
+////////////////////////////////////////////////////////////////////////////////
+
+.macro CSR_R_LOG _GPR, _CSR
+        CSR_R_LOG_N \_GPR, \_CSR
+        WRITE_NL
+.endm
+
+////////////////////////////////////////////////////////////////////////////////
+// CSR_W_LOG <csr>, <gpr>: log csr write from gpr (destroys a0, t0-t2, lr)
+////////////////////////////////////////////////////////////////////////////////
+
+.macro CSR_W_LOG _CSR, _GPR
+        csrw        \_CSR, \_GPR
+#ifndef SYS_QUIET
+        li          t1, -1
+        csrr        t1, \_CSR
+#endif
+        WRITE_S     logM
+        WRITE_S     LABEL_\_CSR
+        WRITE_S     larrowXL
+        WRITE_RAW   t1
+        WRITE_NL
+.endm
+
+////////////////////////////////////////////////////////////////////////////////
+// writeS: write string in a0 (destroys a0, t0)
+////////////////////////////////////////////////////////////////////////////////
+
+writeS:
+
+#ifndef SYS_QUIET
+
+        mv          t0, a0
+10000:
+        lbu         a0, (t0)
+        addi        t0, t0, 1
+        beq         a0, zero, 10000f
+        WRITE_A0
+        j           10000b
+
+#endif
+10000:  ret
+
+// stabilize function size (WRITE_A0 implementation may change)
+.align 7
+
+////////////////////////////////////////////////////////////////////////////////
+// writeA0: write register a0 (destroys a0, t0-t2)
+////////////////////////////////////////////////////////////////////////////////
+
+writeA0:
+
+#ifndef SYS_QUIET
+
+        mv          t0, a0
+
+        // determine architectural register width
+        li          a0, -1
+        srli        a0, a0, 31
+        srli        a0, a0, 1
+        bnez        a0, writeA0_64
+
+writeA0_32:
+
+        // reverse register when xlen is 32
+        li          t1, 8
+10000:  slli        t2, t2, 4
+        andi        a0, t0, 0xf
+        srli        t0, t0, 4
+        or          t2, t2, a0
+        addi        t1, t1, -1
+        bnez        t1, 10000b
+        li          t1, 8
+        j           writeA0_common
+
+writeA0_64:
+
+        // reverse register when xlen is 64
+        li          t1, 16
+10000:  slli        t2, t2, 4
+        andi        a0, t0, 0xf
+        srli        t0, t0, 4
+        or          t2, t2, a0
+        addi        t1, t1, -1
+        bnez        t1, 10000b
+        li          t1, 16
+
+writeA0_common:
+
+        // write reversed characters
+        li          t0, 10
+10000:  andi        a0, t2, 0xf
+        blt         a0, t0, 10001f
+        addi        a0, a0, 'a'-10
+        j           10002f
+10001:  addi        a0, a0, '0'
+10002:  WRITE_A0
+        srli        t2, t2, 4
+        addi        t1, t1, -1
+        bnez        t1, 10000b
+
+#endif
+
+        ret
+
+// stabilize function size (WRITE_A0 implementation may change)
+.align 7
+
+////////////////////////////////////////////////////////////////////////////////
+// writeA0Short: write register a0 with no leading zeros (destroys a0, t0-t2)
+////////////////////////////////////////////////////////////////////////////////
+
+writeA0Short:
+
+#ifndef SYS_QUIET
+
+        mv          t0, a0
+
+        // reverse register
+        mv          t2, zero
+10000:  slli        t2, t2, 4
+        andi        a0, t0, 0xf
+        srli        t0, t0, 4
+        or          t2, t2, a0
+        bnez        t0, 10000b
+
+        // write reversed characters
+        li          t0, 10
+10000:  andi        a0, t2, 0xf
+        blt         a0, t0, 10001f
+        addi        a0, a0, 'a'-10
+        j           10002f
+10001:  addi        a0, a0, '0'
+10002:  WRITE_A0
+        srli        t2, t2, 4
+        bnez        t2, 10000b
+
+#endif
+
+        ret
+
+// stabilize function size (WRITE_A0 implementation may change)
+.align 7
+
+////////////////////////////////////////////////////////////////////////////////
+// shutDown: terminate test abnormally
+////////////////////////////////////////////////////////////////////////////////
+
+shutDown:
+
+        WRITE_LOG   abortMessage
+        EXIT_TEST
+
+// stabilize function size (WRITE_A0 implementation may change)
+.align 7
+
+////////////////////////////////////////////////////////////////////////////////
+// ABORT <msg>: terminate test on abnormal state
+////////////////////////////////////////////////////////////////////////////////
+
+.macro ABORT _MSG
+        WRITE_LOG   \_MSG
+        j           shutDown
+.endm
+
+////////////////////////////////////////////////////////////////////////////////
+// STRINGS
+////////////////////////////////////////////////////////////////////////////////
+
+equalsXL:
+        .string " = 0x"
+rarrowXL:
+        .string " => 0x"
+larrowXL:
+        .string " <= 0x"
+logM:
+        .string "LOG: "
+exitM:
+        .string "TEST ENDED"
+abortMessage:
+        .string "*** TEST ABORTED ****"
+
+////////////////////////////////////////////////////////////////////////////////
+// DEFINE_REG_LABEL: define register name string
+////////////////////////////////////////////////////////////////////////////////
+
+.macro DEFINE_REG_LABEL _L
+        LABEL_\_L : .string "\_L"
+.endm
+
+////////////////////////////////////////////////////////////////////////////////
+// GPR LABELS
+////////////////////////////////////////////////////////////////////////////////
+
+DEFINE_REG_LABEL     zero
+DEFINE_REG_LABEL     ra
+DEFINE_REG_LABEL     sp
+DEFINE_REG_LABEL     gp
+DEFINE_REG_LABEL     tp
+DEFINE_REG_LABEL     t0
+DEFINE_REG_LABEL     t1
+DEFINE_REG_LABEL     t2
+DEFINE_REG_LABEL     s0
+DEFINE_REG_LABEL     s1
+DEFINE_REG_LABEL     a0
+DEFINE_REG_LABEL     a1
+DEFINE_REG_LABEL     a2
+DEFINE_REG_LABEL     a3
+DEFINE_REG_LABEL     a4
+DEFINE_REG_LABEL     a5
+DEFINE_REG_LABEL     a6
+DEFINE_REG_LABEL     a7
+DEFINE_REG_LABEL     s2
+DEFINE_REG_LABEL     s3
+DEFINE_REG_LABEL     s4
+DEFINE_REG_LABEL     s5
+DEFINE_REG_LABEL     s6
+DEFINE_REG_LABEL     s7
+DEFINE_REG_LABEL     s8
+DEFINE_REG_LABEL     s9
+DEFINE_REG_LABEL     s10
+DEFINE_REG_LABEL     s11
+DEFINE_REG_LABEL     t3
+DEFINE_REG_LABEL     t4
+DEFINE_REG_LABEL     t5
+DEFINE_REG_LABEL     t6
+
+////////////////////////////////////////////////////////////////////////////////
+// FPR LABELS
+////////////////////////////////////////////////////////////////////////////////
+
+DEFINE_REG_LABEL     ft0
+DEFINE_REG_LABEL     ft1
+DEFINE_REG_LABEL     ft2
+DEFINE_REG_LABEL     ft3
+DEFINE_REG_LABEL     ft4
+DEFINE_REG_LABEL     ft5
+DEFINE_REG_LABEL     ft6
+DEFINE_REG_LABEL     ft7
+DEFINE_REG_LABEL     fs0
+DEFINE_REG_LABEL     fs1
+DEFINE_REG_LABEL     fa0
+DEFINE_REG_LABEL     fa1
+DEFINE_REG_LABEL     fa2
+DEFINE_REG_LABEL     fa3
+DEFINE_REG_LABEL     fa4
+DEFINE_REG_LABEL     fa5
+DEFINE_REG_LABEL     fa6
+DEFINE_REG_LABEL     fa7
+DEFINE_REG_LABEL     fs2
+DEFINE_REG_LABEL     fs3
+DEFINE_REG_LABEL     fs4
+DEFINE_REG_LABEL     fs5
+DEFINE_REG_LABEL     fs6
+DEFINE_REG_LABEL     fs7
+DEFINE_REG_LABEL     fs8
+DEFINE_REG_LABEL     fs9
+DEFINE_REG_LABEL     fs10
+DEFINE_REG_LABEL     fs11
+DEFINE_REG_LABEL     ft8
+DEFINE_REG_LABEL     ft9
+DEFINE_REG_LABEL     ft10
+DEFINE_REG_LABEL     ft11
+
+////////////////////////////////////////////////////////////////////////////////
+// FPR LABELS
+////////////////////////////////////////////////////////////////////////////////
+
+DEFINE_REG_LABEL     f0
+DEFINE_REG_LABEL     f1
+DEFINE_REG_LABEL     f2
+DEFINE_REG_LABEL     f3
+DEFINE_REG_LABEL     f4
+DEFINE_REG_LABEL     f5
+DEFINE_REG_LABEL     f6
+DEFINE_REG_LABEL     f7
+DEFINE_REG_LABEL     f8
+DEFINE_REG_LABEL     f9
+DEFINE_REG_LABEL     f10
+DEFINE_REG_LABEL     f11
+DEFINE_REG_LABEL     f12
+DEFINE_REG_LABEL     f13
+DEFINE_REG_LABEL     f14
+DEFINE_REG_LABEL     f15
+DEFINE_REG_LABEL     f16
+DEFINE_REG_LABEL     f17
+DEFINE_REG_LABEL     f18
+DEFINE_REG_LABEL     f19
+DEFINE_REG_LABEL     f20
+DEFINE_REG_LABEL     f21
+DEFINE_REG_LABEL     f22
+DEFINE_REG_LABEL     f23
+DEFINE_REG_LABEL     f24
+DEFINE_REG_LABEL     f25
+DEFINE_REG_LABEL     f26
+DEFINE_REG_LABEL     f27
+DEFINE_REG_LABEL     f28
+DEFINE_REG_LABEL     f29
+DEFINE_REG_LABEL     f30
+DEFINE_REG_LABEL     f31
+
+////////////////////////////////////////////////////////////////////////////////
+// CSR INDICES (where assembler does not recognize them)
+////////////////////////////////////////////////////////////////////////////////
+
+#define ustatus     0x000
+#define uie         0x004
+#define utvec       0x005
+#define uscratch    0x040
+#define uepc        0x041
+#define ucause      0x042
+#define utval       0x043
+#define uip         0x044
+#define sedeleg     0x102
+#define sideleg     0x103
+#define stval       0x143
+#define satp        0x180
+#define mtval       0x343
+
+.macro DEFINE_REG_LABEL_X _L, _S
+        LABEL_\_L : .string "\_S"
+.endm
+
+////////////////////////////////////////////////////////////////////////////////
+// CSR LABELS
+////////////////////////////////////////////////////////////////////////////////
+
+// User Trap Setup
+DEFINE_REG_LABEL_X   ustatus,  "ustatus"    // not recognized by assembler
+DEFINE_REG_LABEL_X   uie,      "uie"        // not recognized by assembler
+DEFINE_REG_LABEL_X   utvec,    "utvec"      // not recognized by assembler
+
+// User Trap Handling
+DEFINE_REG_LABEL_X   uscratch, "uscratch"   // not recognized by assembler
+DEFINE_REG_LABEL_X   uepc,     "uepc"       // not recognized by assembler
+DEFINE_REG_LABEL_X   ucause,   "ucause"     // not recognized by assembler
+DEFINE_REG_LABEL_X   utval,    "utval"      // not recognized by assembler
+DEFINE_REG_LABEL_X   uip       "uip"        // not recognized by assembler
+
+// User Floating-Point CSR
+DEFINE_REG_LABEL     fflags
+DEFINE_REG_LABEL     frm
+DEFINE_REG_LABEL     fcsr
+
+// User Counter Timers
+DEFINE_REG_LABEL     cycle
+DEFINE_REG_LABEL     time
+DEFINE_REG_LABEL     instret
+DEFINE_REG_LABEL     cycleh
+DEFINE_REG_LABEL     timeh
+DEFINE_REG_LABEL     instreth
+DEFINE_REG_LABEL     hpmcounter3
+DEFINE_REG_LABEL     hpmcounter4
+DEFINE_REG_LABEL     hpmcounter5
+DEFINE_REG_LABEL     hpmcounter6
+DEFINE_REG_LABEL     hpmcounter7
+DEFINE_REG_LABEL     hpmcounter8
+DEFINE_REG_LABEL     hpmcounter9
+DEFINE_REG_LABEL     hpmcounter10
+DEFINE_REG_LABEL     hpmcounter11
+DEFINE_REG_LABEL     hpmcounter12
+DEFINE_REG_LABEL     hpmcounter13
+DEFINE_REG_LABEL     hpmcounter14
+DEFINE_REG_LABEL     hpmcounter15
+DEFINE_REG_LABEL     hpmcounter16
+DEFINE_REG_LABEL     hpmcounter17
+DEFINE_REG_LABEL     hpmcounter18
+DEFINE_REG_LABEL     hpmcounter19
+DEFINE_REG_LABEL     hpmcounter20
+DEFINE_REG_LABEL     hpmcounter21
+DEFINE_REG_LABEL     hpmcounter22
+DEFINE_REG_LABEL     hpmcounter23
+DEFINE_REG_LABEL     hpmcounter24
+DEFINE_REG_LABEL     hpmcounter25
+DEFINE_REG_LABEL     hpmcounter26
+DEFINE_REG_LABEL     hpmcounter27
+DEFINE_REG_LABEL     hpmcounter28
+DEFINE_REG_LABEL     hpmcounter29
+DEFINE_REG_LABEL     hpmcounter30
+DEFINE_REG_LABEL     hpmcounter31
+DEFINE_REG_LABEL     hpmcounterh3
+DEFINE_REG_LABEL     hpmcounterh4
+DEFINE_REG_LABEL     hpmcounterh5
+DEFINE_REG_LABEL     hpmcounterh6
+DEFINE_REG_LABEL     hpmcounterh7
+DEFINE_REG_LABEL     hpmcounterh8
+DEFINE_REG_LABEL     hpmcounterh9
+DEFINE_REG_LABEL     hpmcounterh10
+DEFINE_REG_LABEL     hpmcounterh11
+DEFINE_REG_LABEL     hpmcounterh12
+DEFINE_REG_LABEL     hpmcounterh13
+DEFINE_REG_LABEL     hpmcounterh14
+DEFINE_REG_LABEL     hpmcounterh15
+DEFINE_REG_LABEL     hpmcounterh16
+DEFINE_REG_LABEL     hpmcounterh17
+DEFINE_REG_LABEL     hpmcounterh18
+DEFINE_REG_LABEL     hpmcounterh19
+DEFINE_REG_LABEL     hpmcounterh20
+DEFINE_REG_LABEL     hpmcounterh21
+DEFINE_REG_LABEL     hpmcounterh22
+DEFINE_REG_LABEL     hpmcounterh23
+DEFINE_REG_LABEL     hpmcounterh24
+DEFINE_REG_LABEL     hpmcounterh25
+DEFINE_REG_LABEL     hpmcounterh26
+DEFINE_REG_LABEL     hpmcounterh27
+DEFINE_REG_LABEL     hpmcounterh28
+DEFINE_REG_LABEL     hpmcounterh29
+DEFINE_REG_LABEL     hpmcounterh30
+DEFINE_REG_LABEL     hpmcounterh31
+
+// Supervisor Trap Setup
+DEFINE_REG_LABEL     sstatus
+DEFINE_REG_LABEL_X   sedeleg, "sedeleg"     // not recognized by assembler
+DEFINE_REG_LABEL_X   sideleg, "sideleg"     // not recognized by assembler
+DEFINE_REG_LABEL     sie
+DEFINE_REG_LABEL     stvec
+DEFINE_REG_LABEL     scounteren
+
+// Supervisor Trap Handling
+DEFINE_REG_LABEL     sscratch
+DEFINE_REG_LABEL     sepc
+DEFINE_REG_LABEL     scause
+DEFINE_REG_LABEL_X   stval, "stval"         // not recognized by assembler
+DEFINE_REG_LABEL     sip
+
+// Supervisor Protection and Translation
+DEFINE_REG_LABEL_X   satp,  "satp"          // not recognized by assembler
+
+// Machine Information Registers
+DEFINE_REG_LABEL     mvendorid
+DEFINE_REG_LABEL     marchid
+DEFINE_REG_LABEL     mimpid
+DEFINE_REG_LABEL     mhartid
+
+// Machine Trap Setup
+DEFINE_REG_LABEL     mstatus
+DEFINE_REG_LABEL     misa
+DEFINE_REG_LABEL     medeleg
+DEFINE_REG_LABEL     mideleg
+DEFINE_REG_LABEL     mie
+DEFINE_REG_LABEL     mtvec
+DEFINE_REG_LABEL     mcycle
+DEFINE_REG_LABEL     mcycleh
+DEFINE_REG_LABEL     minstret
+DEFINE_REG_LABEL     minstreth
+DEFINE_REG_LABEL     mcounteren
+
+// Machine Trap Handling
+DEFINE_REG_LABEL     mscratch
+DEFINE_REG_LABEL     mepc
+DEFINE_REG_LABEL     mcause
+DEFINE_REG_LABEL_X   mtval, "mtval"         // not recognized by assembler
+DEFINE_REG_LABEL     mip
+
+// Machine Protection and Translation
+DEFINE_REG_LABEL     pmpcfg0
+DEFINE_REG_LABEL     pmpcfg1
+DEFINE_REG_LABEL     pmpcfg2
+DEFINE_REG_LABEL     pmpcfg3
+DEFINE_REG_LABEL     pmpaddr0
+DEFINE_REG_LABEL     pmpaddr1
+DEFINE_REG_LABEL     pmpaddr2
+DEFINE_REG_LABEL     pmpaddr3
+DEFINE_REG_LABEL     pmpaddr4
+DEFINE_REG_LABEL     pmpaddr5
+DEFINE_REG_LABEL     pmpaddr6
+DEFINE_REG_LABEL     pmpaddr7
+DEFINE_REG_LABEL     pmpaddr8
+DEFINE_REG_LABEL     pmpaddr9
+DEFINE_REG_LABEL     pmpaddr10
+DEFINE_REG_LABEL     pmpaddr11
+DEFINE_REG_LABEL     pmpaddr12
+DEFINE_REG_LABEL     pmpaddr13
+DEFINE_REG_LABEL     pmpaddr14
+DEFINE_REG_LABEL     pmpaddr15
+
+// Profiling
+DEFINE_REG_LABEL     mhpmcounter3
+DEFINE_REG_LABEL     mhpmcounter4
+DEFINE_REG_LABEL     mhpmcounter5
+DEFINE_REG_LABEL     mhpmcounter6
+DEFINE_REG_LABEL     mhpmcounter7
+DEFINE_REG_LABEL     mhpmcounter8
+DEFINE_REG_LABEL     mhpmcounter9
+DEFINE_REG_LABEL     mhpmcounter10
+DEFINE_REG_LABEL     mhpmcounter11
+DEFINE_REG_LABEL     mhpmcounter12
+DEFINE_REG_LABEL     mhpmcounter13
+DEFINE_REG_LABEL     mhpmcounter14
+DEFINE_REG_LABEL     mhpmcounter15
+DEFINE_REG_LABEL     mhpmcounter16
+DEFINE_REG_LABEL     mhpmcounter17
+DEFINE_REG_LABEL     mhpmcounter18
+DEFINE_REG_LABEL     mhpmcounter19
+DEFINE_REG_LABEL     mhpmcounter20
+DEFINE_REG_LABEL     mhpmcounter21
+DEFINE_REG_LABEL     mhpmcounter22
+DEFINE_REG_LABEL     mhpmcounter23
+DEFINE_REG_LABEL     mhpmcounter24
+DEFINE_REG_LABEL     mhpmcounter25
+DEFINE_REG_LABEL     mhpmcounter26
+DEFINE_REG_LABEL     mhpmcounter27
+DEFINE_REG_LABEL     mhpmcounter28
+DEFINE_REG_LABEL     mhpmcounter29
+DEFINE_REG_LABEL     mhpmcounter30
+DEFINE_REG_LABEL     mhpmcounter31
+DEFINE_REG_LABEL     mhpmcounter3h
+DEFINE_REG_LABEL     mhpmcounter4h
+DEFINE_REG_LABEL     mhpmcounter5h
+DEFINE_REG_LABEL     mhpmcounter6h
+DEFINE_REG_LABEL     mhpmcounter7h
+DEFINE_REG_LABEL     mhpmcounter8h
+DEFINE_REG_LABEL     mhpmcounter9h
+DEFINE_REG_LABEL     mhpmcounter10h
+DEFINE_REG_LABEL     mhpmcounter11h
+DEFINE_REG_LABEL     mhpmcounter12h
+DEFINE_REG_LABEL     mhpmcounter13h
+DEFINE_REG_LABEL     mhpmcounter14h
+DEFINE_REG_LABEL     mhpmcounter15h
+DEFINE_REG_LABEL     mhpmcounter16h
+DEFINE_REG_LABEL     mhpmcounter17h
+DEFINE_REG_LABEL     mhpmcounter18h
+DEFINE_REG_LABEL     mhpmcounter19h
+DEFINE_REG_LABEL     mhpmcounter20h
+DEFINE_REG_LABEL     mhpmcounter21h
+DEFINE_REG_LABEL     mhpmcounter22h
+DEFINE_REG_LABEL     mhpmcounter23h
+DEFINE_REG_LABEL     mhpmcounter24h
+DEFINE_REG_LABEL     mhpmcounter25h
+DEFINE_REG_LABEL     mhpmcounter26h
+DEFINE_REG_LABEL     mhpmcounter27h
+DEFINE_REG_LABEL     mhpmcounter28h
+DEFINE_REG_LABEL     mhpmcounter29h
+DEFINE_REG_LABEL     mhpmcounter30h
+DEFINE_REG_LABEL     mhpmcounter31h
+DEFINE_REG_LABEL     mhpmevent3
+DEFINE_REG_LABEL     mhpmevent4
+DEFINE_REG_LABEL     mhpmevent5
+DEFINE_REG_LABEL     mhpmevent6
+DEFINE_REG_LABEL     mhpmevent7
+DEFINE_REG_LABEL     mhpmevent8
+DEFINE_REG_LABEL     mhpmevent9
+DEFINE_REG_LABEL     mhpmevent10
+DEFINE_REG_LABEL     mhpmevent11
+DEFINE_REG_LABEL     mhpmevent12
+DEFINE_REG_LABEL     mhpmevent13
+DEFINE_REG_LABEL     mhpmevent14
+DEFINE_REG_LABEL     mhpmevent15
+DEFINE_REG_LABEL     mhpmevent16
+DEFINE_REG_LABEL     mhpmevent17
+DEFINE_REG_LABEL     mhpmevent18
+DEFINE_REG_LABEL     mhpmevent19
+DEFINE_REG_LABEL     mhpmevent20
+DEFINE_REG_LABEL     mhpmevent21
+DEFINE_REG_LABEL     mhpmevent22
+DEFINE_REG_LABEL     mhpmevent23
+DEFINE_REG_LABEL     mhpmevent24
+DEFINE_REG_LABEL     mhpmevent25
+DEFINE_REG_LABEL     mhpmevent26
+DEFINE_REG_LABEL     mhpmevent27
+DEFINE_REG_LABEL     mhpmevent28
+DEFINE_REG_LABEL     mhpmevent29
+DEFINE_REG_LABEL     mhpmevent30
+DEFINE_REG_LABEL     mhpmevent31
+
+// leave space for new labels
+.align 11

tests/bitmanip/src/interest.py

@@ -0,0 +1,50 @@
+
+
+filename = '/home/zfw/nexus-am/apps/bitasm/src/test.Source'
+fileoutname = '/home/zfw/nexus-am/apps/bitasm/src/test.S'
+fs = open(filename ,'r+')
+fout = open(fileoutname, 'w')
+
+interest = ['include', 'pcnt', 'clz', 'ctz', 'pack', 'packw', 'packh', 'clmul', 'max', 'min','andn','orn','xnor','sbclr','sbinv','sbext','sbset','rol','ror']
+uninterest = ['clmulw', 'clmulrw', 'clmulhw','packu','packuw','sbclrw','sbinvw','sbextw','sbsetw','sbclriw','sbinviw','sbextiw','sbsetiw']
+
+complete = [
+'test_complete:\n',
+'    la x2, test_pass\n',
+'    jr x2\n',
+'\n',
+'.align 4\n',
+'test_result:\n',
+'    .fill 1, 4, -1\n',
+'str_Test_Pass:\n',
+'    .string "Test Pass"\n',
+'str_Test_Fail:\n',
+'    .string "Test Fail"\n']
+
+record = 0
+for line in fs.readlines():
+    if(line[0] == '#'):
+        for i in interest:
+            if i in line:
+                
+                for j in uninterest:
+                    if(j in line):
+                        record = 0
+                        break
+                if(('clmulw'in line) | ('clmulrw' in line) | ('clmulhw' in line) | ('packu' in line) | ('packuw' in line) | 
+                ('sbclrw' in line) | ('sbinvw' in line) | ('sbextw' in line) | ('sbsetw' in line) | 
+                ('sbclriw' in line) | ('sbinviw' in line) | ('sbextiw' in line) | ('sbsetiw' in line)):
+                    record = 0
+                else:
+                    record = 1
+                    break
+            else:
+                record = 0
+    if record:
+        fout.write(line)
+
+for line in complete:
+    fout.write(line)
+
+fout.close()
+fs.close()

tests/crypto/Makefile

@@ -0,0 +1,24 @@
+# NAME = Crypto
+# SRCS = $(shell find -L ./dest/ -name "*.S")
+# include $(AM_HOME)/Makefile.app
+
+include $(AM_HOME)/Makefile.check
+
+.PHONY: all run clean $(ALL)
+
+ALL = $(basename $(notdir $(shell find src/. -name "*.S")))
+
+all: $(addprefix Makefile., $(ALL))
+	echo $(ALL)
+
+$(ALL): %: Makefile.%
+
+Makefile.%: src/%.S
+	@/bin/echo -e "NAME = $*\nSRCS = $<\nLIBS += klib\ninclude $${AM_HOME}/Makefile.app" > $@
+	-@make -s -f $@ ARCH=$(ARCH) $(MAKECMDGOALS)
+	-@rm -f Makefile.$*
+
+clean:
+	rm -rf Makefile.* build/
+
+default $(MAKECMDGOALS): all ;

tests/crypto/include/crypto.h

@@ -0,0 +1,20 @@
+#ifndef __CRYPTO_H__
+#define __CRYPTO_H__
+
+
+#include <am.h>
+#include <klib.h>
+#include <klib-macros.h>
+
+void aes64ds01_entry();
+
+void sha256sig0_entry();
+void sha256sig1_entry();
+void sha256sum0_entry();
+void sha256sum1_entry();
+void sha512sig0_entry();
+void sha512sig1_entry();
+void sha512sum0_entry();
+void sha512sum1_entry();
+
+#endif

tests/crypto/include/model_test.h

@@ -0,0 +1,64 @@
+#ifndef _COMPLIANCE_MODEL_H
+#define _COMPLIANCE_MODEL_H
+
+#if XLEN == 64
+  #define ALIGNMENT 3
+#else
+  #define ALIGNMENT 2
+#endif
+
+#define RVMODEL_DATA_SECTION \
+        .pushsection .tohost,"aw",@progbits;                            \
+        .align 8; .global tohost; tohost: .dword 0;                     \
+        .align 8; .global fromhost; fromhost: .dword 0;                 \
+        .popsection;                                                    \
+        .align 8; .global begin_regstate; begin_regstate:               \
+        .word 128;                                                      \
+        .align 8; .global end_regstate; end_regstate:                   \
+        .word 4;
+
+//RV_COMPLIANCE_HALT
+#define RVMODEL_HALT                                              \
+  mv a0, x0;                                                         \
+  .word 0x0000006b
+  // self_loop:  j self_loop;
+
+#define RVMODEL_BOOT
+
+//RV_COMPLIANCE_DATA_BEGIN
+#define RVMODEL_DATA_BEGIN                                              \
+  .align 4; .global begin_signature; begin_signature:
+
+//RV_COMPLIANCE_DATA_END
+#define RVMODEL_DATA_END                                                      \
+  .align 4; .global end_signature; end_signature:  \
+  RVMODEL_DATA_SECTION                                                        \
+
+//RVTEST_IO_INIT
+#define RVMODEL_IO_INIT
+//RVTEST_IO_WRITE_STR
+#define RVMODEL_IO_WRITE_STR(_R, _STR)
+//RVTEST_IO_CHECK
+#define RVMODEL_IO_CHECK()
+//RVTEST_IO_ASSERT_GPR_EQ
+#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I)
+//RVTEST_IO_ASSERT_SFPR_EQ
+#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
+//RVTEST_IO_ASSERT_DFPR_EQ
+#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
+
+#define RVMODEL_SET_MSW_INT       \
+ li t1, 1;                         \
+ li t2, 0x2000000;                 \
+ sw t1, 0(t2);
+
+#define RVMODEL_CLEAR_MSW_INT     \
+ li t2, 0x2000000;                 \
+ sw x0, 0(t2);
+
+#define RVMODEL_CLEAR_MTIMER_INT
+
+#define RVMODEL_CLEAR_MEXT_INT
+
+#endif // _COMPLIANCE_MODEL_H
+

tests/crypto/merge.py

@@ -0,0 +1,26 @@
+import os
+
+files = os.listdir('src')
+srcfile = 'src/crypto.S'
+
+fd = open(srcfile, 'w')
+
+for f in files:
+    record = 0
+    fs = open('src/'+f, 'r+')
+    for line in fs.readlines():
+        if 'RVTEST_CODE_BEGIN' in line:
+            record = 1
+        elif 'RVMODEL_HALT' in line:
+            record = 0
+
+        if record :
+            if 'inst_' in line:
+                fd.write(f[0:-2].lower().replace('-','_')+'_')
+                fd.write(line.lstrip())
+            else:
+                fd.write(line)
+
+
+fs.close()
+fd.close()

tests/crypto/program.py

@@ -0,0 +1,46 @@
+import os
+
+spath = './tmp/'
+dpath = './src/'
+
+files = os.listdir(spath)
+
+for f in files:
+    prefix = f[0:-2].lower().replace('-','_')
+    entry = prefix + '_entry'
+    init = prefix + '_init'
+    code_begin = prefix + '_code_begin'
+    code_end = prefix + '_code_end'
+
+    fs = open(spath+f, 'r+')
+    fd = open(dpath+f, 'w')
+
+    record = 1
+    for line in fs.readlines():
+        # if ('RVTEST_SIGBASE' in line): #('RVTEST_CASE' in line) | 
+        #     continue
+        # if 'RVTEST_CODE_END' in line:
+        #     record = 0
+        # if record:
+        if '.globl rvtest_entry_point' in line:
+            fd.write('.globl ' + entry + '\n')
+        elif 'rvtest_entry_point:' in line:
+            fd.write(entry+':\n')
+        elif 'RVTEST_CODE_BEGIN' in line:
+            fd.write('RVTEST_CODE_BEGIN ' + init + ' ' + code_begin + '\n')
+        elif 'RVTEST_CODE_END' in line:
+            fd.write('RVTEST_CODE_END ' + code_end + '\n')
+        elif '.section .text.init' in line:
+            fd.write(line)
+            fd.write('.globl main\n')
+            fd.write('main:\n')
+        else:
+            fd.write(line)
+
+    # fd.write('mv a0, x0;\n')
+    # fd.write('.word 0x0000006b\n')
+
+
+fs.close()
+fd.close()
+