tests: add xs customized cache op test

tests/cacheoptest/Makefile

@@ -0,0 +1,4 @@
+NAME := cacheoptest
+SRCS := $(shell find -L ./src/ -name "*.[cS]")
+
+include $(AM_HOME)/Makefile.app

tests/cacheoptest/include/cacheop_utils.h

@@ -0,0 +1,37 @@
+clear_cop_csrs:
+    csrw cop_finish, zero
+    csrw cop_level, zero
+    csrw cop_way, zero
+    csrw cop_index, zero
+    csrw cop_bank, zero
+    csrw cop_tag_ecc, zero
+    csrw cop_tag_bits, zero
+    csrw cop_tag_data, zero
+    csrw cop_tag_data_h, zero
+    csrw cop_ecc_width, zero
+    csrw cop_data_ecc, zero
+    csrw cop_data_0, zero
+    csrw cop_data_1, zero
+    csrw cop_data_2, zero
+    csrw cop_data_3, zero
+    csrw cop_data_4, zero
+    csrw cop_data_5, zero
+    csrw cop_data_6, zero
+    csrw cop_data_7, zero
+    ret
+
+wait_until_cop_finish_or_timeout:
+    li t1, 0x0
+    li t0, 0x100
+keep_waiting:
+    addi t1, t1, 1
+    beq t0, t1, end_waiting
+    csrr t0, cop_finish
+    beq t0, zero, keep_waiting
+end_waiting:
+    ret
+
+wait_until_cop_finish:
+    csrr t0, cop_finish
+    beq t0, zero, wait_until_cop_finish
+    ret

tests/cacheoptest/include/custom_encoding.h

@@ -0,0 +1,91 @@
+#ifndef RISCV_XS_CUSTOM_ENCODING_H
+#define RISCV_XS_CUSTOM_ENCODING_H
+
+#define CSR_XS_CACHE_OP_BASE 0x5C5
+
+#define COP_CHECK 0
+#define COP_LOAD  1
+#define COP_STORE 2
+#define COP_FLUSH 3
+
+#define COP_ID_ICACHE 0
+#define COP_ID_DCACHE 1
+
+#define COP_RESULT_CODE_IDLE 0
+#define COP_RESULT_CODE_OK 1
+#define COP_RESULT_CODE_ERROR 2
+
+#define CSR_CACHE_OP_OFFSET 0
+#define CSR_OP_FINISH_OFFSET 1
+#define CSR_CACHE_LEVEL_OFFSET 2
+#define CSR_CACHE_WAY_OFFSET 3
+#define CSR_CACHE_IDX_OFFSET 4
+#define CSR_CACHE_BANK_NUM_OFFSET 5
+#define CSR_CACHE_TAG_ECC_OFFSET 6
+#define CSR_CACHE_TAG_BITS_OFFSET 7
+#define CSR_CACHE_TAG_LOW_OFFSET 8
+#define CSR_CACHE_TAG_HIGH_OFFSET 9
+#define CSR_CACHE_ECC_WIDTH_OFFSET 10
+#define CSR_CACHE_DATA_ECC_OFFSET 11
+#define CSR_CACHE_DATA_0_OFFSET 12
+#define CSR_CACHE_DATA_1_OFFSET 13
+#define CSR_CACHE_DATA_2_OFFSET 14
+#define CSR_CACHE_DATA_3_OFFSET 15
+#define CSR_CACHE_DATA_4_OFFSET 16
+#define CSR_CACHE_DATA_5_OFFSET 17
+#define CSR_CACHE_DATA_6_OFFSET 18
+#define CSR_CACHE_DATA_7_OFFSET 19
+
+#define CSR_CACHE_OP (CSR_XS_CACHE_OP_BASE + CSR_CACHE_OP_OFFSET)
+#define CSR_OP_FINISH (CSR_XS_CACHE_OP_BASE + CSR_OP_FINISH_OFFSET)
+#define CSR_CACHE_LEVEL (CSR_XS_CACHE_OP_BASE + CSR_CACHE_LEVEL_OFFSET)
+#define CSR_CACHE_WAY (CSR_XS_CACHE_OP_BASE + CSR_CACHE_WAY_OFFSET)
+#define CSR_CACHE_IDX (CSR_XS_CACHE_OP_BASE + CSR_CACHE_IDX_OFFSET)
+#define CSR_CACHE_BANK_NUM (CSR_XS_CACHE_OP_BASE + CSR_CACHE_BANK_NUM_OFFSET)
+#define CSR_CACHE_TAG_ECC (CSR_XS_CACHE_OP_BASE + CSR_CACHE_TAG_ECC_OFFSET)
+#define CSR_CACHE_TAG_BITS (CSR_XS_CACHE_OP_BASE + CSR_CACHE_TAG_BITS_OFFSET)
+#define CSR_CACHE_TAG_LOW (CSR_XS_CACHE_OP_BASE + CSR_CACHE_TAG_LOW_OFFSET)
+#define CSR_CACHE_TAG_HIGH (CSR_XS_CACHE_OP_BASE + CSR_CACHE_TAG_HIGH_OFFSET)
+#define CSR_CACHE_ECC_WIDTH (CSR_XS_CACHE_OP_BASE + CSR_CACHE_ECC_WIDTH_OFFSET)
+#define CSR_CACHE_DATA_ECC (CSR_XS_CACHE_OP_BASE + CSR_CACHE_DATA_ECC_OFFSET)
+#define CSR_CACHE_DATA_0 (CSR_XS_CACHE_OP_BASE + CSR_CACHE_DATA_0_OFFSET)
+#define CSR_CACHE_DATA_1 (CSR_XS_CACHE_OP_BASE + CSR_CACHE_DATA_1_OFFSET)
+#define CSR_CACHE_DATA_2 (CSR_XS_CACHE_OP_BASE + CSR_CACHE_DATA_2_OFFSET)
+#define CSR_CACHE_DATA_3 (CSR_XS_CACHE_OP_BASE + CSR_CACHE_DATA_3_OFFSET)
+#define CSR_CACHE_DATA_4 (CSR_XS_CACHE_OP_BASE + CSR_CACHE_DATA_4_OFFSET)
+#define CSR_CACHE_DATA_5 (CSR_XS_CACHE_OP_BASE + CSR_CACHE_DATA_5_OFFSET)
+#define CSR_CACHE_DATA_6 (CSR_XS_CACHE_OP_BASE + CSR_CACHE_DATA_6_OFFSET)
+#define CSR_CACHE_DATA_7 (CSR_XS_CACHE_OP_BASE + CSR_CACHE_DATA_7_OFFSET)
+
+#define cop_op CSR_CACHE_OP
+#define cop_finish CSR_OP_FINISH
+#define cop_level CSR_CACHE_LEVEL
+#define cop_way CSR_CACHE_WAY
+#define cop_index CSR_CACHE_IDX
+#define cop_bank CSR_CACHE_BANK_NUM
+#define cop_tag_ecc CSR_CACHE_TAG_ECC
+#define cop_tag_bits CSR_CACHE_TAG_BITS
+#define cop_tag_data CSR_CACHE_TAG_LOW
+#define cop_tag_data_h CSR_CACHE_TAG_HIGH
+#define cop_ecc_width CSR_CACHE_ECC_WIDTH
+#define cop_data_ecc CSR_CACHE_DATA_ECC
+#define cop_data_0 CSR_CACHE_DATA_0
+#define cop_data_1 CSR_CACHE_DATA_1
+#define cop_data_2 CSR_CACHE_DATA_2
+#define cop_data_3 CSR_CACHE_DATA_3
+#define cop_data_4 CSR_CACHE_DATA_4
+#define cop_data_5 CSR_CACHE_DATA_5
+#define cop_data_6 CSR_CACHE_DATA_6
+#define cop_data_7 CSR_CACHE_DATA_7
+
+#define COP_READ_TAG_ECC 0
+#define COP_READ_DATA_ECC 1
+#define COP_READ_TAG 2
+#define COP_READ_DATA 3
+#define COP_WRITE_TAG_ECC 4
+#define COP_WRITE_DATA_ECC 5
+#define COP_WRITE_TAG 6
+#define COP_WRITE_DATA 7
+#define COP_FLUSH_BLOCK 8
+
+#endif

tests/cacheoptest/include/test.h

@@ -0,0 +1,11 @@
+#ifndef __AMUNIT_H__
+#define __AMUNIT_H__
+
+#include <am.h>
+#include <klib.h>
+#include <klib-macros.h>
+#include <encoding.h>
+
+void workload();
+
+#endif

tests/cacheoptest/src/main.c

@@ -0,0 +1,24 @@
+#include <test.h>
+
+void case_passed() {
+    static int i = 0;
+    printf("Test case %d passed.\n", i++);
+    __asm__("ret");
+}
+
+void success() {
+    printf("Cache op test passed.\n");
+    while(1);
+}
+
+void failure() {
+    printf("Cache op test failed\n");
+    while(1);
+}
+
+int main() {
+    printf("Cache op test: difftest should be disabled\n");
+    printf("Hint: use --no-diff to disable difftest\n");
+    workload();
+    return 0;
+}

tests/cacheoptest/src/workload.S

@@ -0,0 +1,142 @@
+#-----------------------------------------------------------------------------
+# workload.S
+#-----------------------------------------------------------------------------
+#
+# Test customized inst/data cache control insts
+#
+#-----------------------------------------------------------------------------
+
+#include "encoding.h"
+#include "custom_encoding.h"
+#include "cacheop_utils.h"
+
+.global workload
+workload:
+  nop
+
+#-----------------------------------------------------------------------------
+# Test 1: cache op ctrl csr read / write
+#-----------------------------------------------------------------------------
+
+# basic csr read/write
+case1:
+  li a0, 0
+  csrw cop_finish, a0
+  csrr a1, cop_finish
+  bne a0, a1, failure
+
+  li a0, 0x12345678
+  csrw cop_level, a0
+  csrr a1, cop_level
+  bne a0, a1, failure
+
+  li a0, 0x12345678
+  csrw cop_data_0, a0
+  csrr a1, cop_data_0
+  bne a0, a1, failure
+
+# basic dcache data write op
+case2:
+  # reset cache op csrs
+  jal clear_cop_csrs
+
+  # prepare cache op ctrl info
+  li a0, 0x12345678
+  csrw cop_data_0, a0
+  li a2, COP_ID_DCACHE
+  csrw cop_level, a2
+
+  # send cache op resuest
+  li a2, COP_WRITE_DATA
+  csrw cop_op, a2
+
+  # wait for cache op response
+  jal wait_until_cop_finish_or_timeout
+
+  # jal case_passed
+
+#-----------------------------------------------------------------------------
+# Test 2: basic cache op flow
+#-----------------------------------------------------------------------------
+
+# dcache data write/read op: loop test
+case3:
+  # write data cache using cache op
+  # reset cache op csrs
+  jal clear_cop_csrs
+
+  # prepare cache op ctrl info
+  li a0, 0x12345678
+  csrw cop_data_0, a0
+  li a2, COP_ID_DCACHE
+  csrw cop_level, a2
+
+  # send cache op request
+  li a2, COP_WRITE_DATA
+  csrw cop_op, a2
+
+  # wait for cache op response
+  jal wait_until_cop_finish_or_timeout
+
+  # check cache op result
+  csrr a1, cop_finish
+  li a2, 1
+  bne a1, a2, failure
+
+  # read data cache using cache op
+  # reset cache op csrs
+  jal clear_cop_csrs
+
+  # prepare cache op ctrl info
+  li a2, COP_ID_DCACHE
+  csrw cop_level, a2
+
+  # send cache op request
+  li a2, COP_READ_DATA
+  csrw cop_op, a2
+
+  # wait for cache op response
+  jal wait_until_cop_finish_or_timeout
+
+  # check cache op result
+  csrr a1, cop_finish
+  li a2, 1
+  bne a1, a2, failure
+  csrr a1, cop_data_0
+  li a2, 0x12345678
+  bne a1, a2, failure
+
+  # basic flow check passed
+  # jal case_passed
+
+#-----------------------------------------------------------------------------
+# Test 3: dcache tag read/write
+#-----------------------------------------------------------------------------
+
+#-----------------------------------------------------------------------------
+# Test 3: dcache data read/write
+#-----------------------------------------------------------------------------
+
+#-----------------------------------------------------------------------------
+# Test 4: dcache ecc read/write
+#-----------------------------------------------------------------------------
+
+#-----------------------------------------------------------------------------
+# Test 5: icache tag read/write
+#-----------------------------------------------------------------------------
+
+#-----------------------------------------------------------------------------
+# Test 6: icache data read/write
+#-----------------------------------------------------------------------------
+
+#-----------------------------------------------------------------------------
+# test finished
+#-----------------------------------------------------------------------------
+
+  j success
+  
+#-----------------------------------------------------------------------------
+# misc
+#-----------------------------------------------------------------------------
+
+