Merge branch 'southlake' of github.com:OpenXiangShan/nexus-am into southlake
This commit is contained in:
commit
35a979a4bd
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@ -26,7 +26,7 @@
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# define SYNC_ADDR 0x40001004
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# define FB_ADDR 0x50000000
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#elif defined(__ARCH_RISCV64_XS_SOUTHLAKE) || defined(__ARCH_RISCV64_XS_SOUTHLAKE_FLASH)
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# define RTC_ADDR 0x1f0000bff8
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# define RTC_ADDR 0x1f1000bff8
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// CLINT 0x1f00000000
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#else
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# define SERIAL_PORT 0xa10003f8
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@ -21,7 +21,7 @@ static const _Area segments[] = { // Kernel memory mappings
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RANGE_LEN(0xc0000000, 0x100000), // page table test allocates from this position
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#elif defined(__ARCH_RISCV64_XS_SOUTHLAKE) || defined(__ARCH_RISCV64_XS_SOUTHLAKE_FLASH)
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RANGE_LEN(0x2000000000, 0x8000000), // PMEM
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RANGE_LEN(0x1f10050000, 0x1000), // uart
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RANGE_LEN(0x1f00050000, 0x1000), // uart
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// RANGE_LEN(CLINT_MMIO, 0x10000), // clint/timer
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// RANGE_LEN(0x1f0c000000, 0x4000000), // PLIC
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RANGE_LEN(0x2040000000, 0x100000), // page table test allocates from this position
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@ -3,7 +3,7 @@
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#include <riscv.h>
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#include <klib.h>
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#define UARTLITE_MMIO 0x1f10050000
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#define UARTLITE_MMIO 0x1f00050000
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#define UARTLITE_RX_FIFO 0x0
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#define UARTLITE_TX_FIFO 0x4
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#define UARTLITE_STAT_REG 0x8
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@ -13,10 +13,10 @@
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#define INTR_RANDOM_MASK (0x40070010UL)
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#define PLIC_BASE_ADDR (0x3c000000UL)
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#elif defined(__ARCH_RISCV64_XS_SOUTHLAKE) || defined(__ARCH_RISCV64_XS_SOUTHLAKE_FLASH)
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#define INTR_GEN_ADDR (0x1f10060000UL)
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#define INTR_RANDOM (0x1f10060008UL)
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#define INTR_RANDOM_MASK (0x1f10060010UL)
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#define PLIC_BASE_ADDR (0x1f0c000000UL)
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#define INTR_GEN_ADDR (0x1f00060000UL)
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#define INTR_RANDOM (0x1f00060008UL)
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#define INTR_RANDOM_MASK (0x1f00060010UL)
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#define PLIC_BASE_ADDR (0x1f1c000000UL)
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#endif
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extern int __am_ncpu;
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@ -3,9 +3,9 @@
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// naive LLC cache op test
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#if defined(__ARCH_RISCV64_XS_SOUTHLAKE) || defined(__ARCH_RISCV64_XS_SOUTHLAKE_FLASH)
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#define CACHE_CTRL_BASE 0x1f00040100
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#define CACHE_CMD_BASE 0x1f00040200
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#define HART_CTRL_RESET_REG_BASE 0x1f00001000
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#define CACHE_CTRL_BASE 0x1f10040100
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#define CACHE_CMD_BASE 0x1f10040200
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#define HART_CTRL_RESET_REG_BASE 0x1f10001000
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#else
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#define CACHE_CTRL_BASE 0x39000100
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#define CACHE_CMD_BASE 0x39000200
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