trace code
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parent
99b9b60bc4
commit
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@ -1,8 +1,22 @@
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*.*
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*
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!*/
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!Makefile
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!*.mk
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!*.scala
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!*.[cSh]
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!*.v
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!*.cpp
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!*.cc
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!.gitignore
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!.scalafmt.conf
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!build.sc
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!README.md
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build/
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# mill
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out/
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.bsp/
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.idea/
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.idea_modules/
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test_run_dir/
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build/
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7
Makefile
7
Makefile
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@ -6,6 +6,7 @@ test:
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mill -i $(PRJ).test
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verilog:
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$(call git_commit, "generate verilog")
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mkdir -p $(BUILD_DIR)
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mill -i $(PRJ).runMain Elaborate -td $(BUILD_DIR)
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@ -22,3 +23,9 @@ clean:
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-rm -rf $(BUILD_DIR)
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.PHONY: test verilog help reformat checkformat clean
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sim:
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$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
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@echo "Write this Makefile by yourself."
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-include ../Makefile
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