dirtybit: set dirtyfield as echofield

src/main/scala/huancun/Common.scala

@@ -62,6 +62,7 @@ class SourceDReq(implicit p: Parameters) extends InnerTask with HasChannelBits {
   val off = UInt(offsetBits.W)
   val denied = Bool()
   val sinkId = UInt(mshrBits.W)
+  val dirty = Bool()
 }
 
 class SourceAReq(implicit p: Parameters) extends HuanCunBundle {
@@ -102,6 +103,7 @@ class SinkDResp(implicit p: Parameters) extends HuanCunBundle {
   val sink = UInt(outerSinkBits.W)
   val last = Bool() // last beat
   val denied = Bool()
+  val dirty = Bool()
 }
 class SinkEResp(implicit p: Parameters) extends HuanCunBundle {
   // GrantAck

src/main/scala/huancun/HCCacheParameters.scala

@@ -93,10 +93,10 @@ case class HCCacheParameters(
   clientCaches:      Seq[CacheParameters] = Nil,
   inclusive:         Boolean = true,
   alwaysReleaseData: Boolean = false,
-  echoField:         Seq[BundleFieldBase] = Nil,
+  echoField:         Seq[BundleFieldBase] = Seq(DirtyField()),
   reqField:          Seq[BundleFieldBase] = Nil, // master
   respKey:           Seq[BundleKeyBase] = Nil,
-  reqKey:            Seq[BundleKeyBase] = Seq(PrefetchKey, PreferCacheKey, DirtyKey, AliasKey), // slave
+  reqKey:            Seq[BundleKeyBase] = Seq(PrefetchKey, PreferCacheKey, AliasKey), // slave
   respField:         Seq[BundleFieldBase] = Nil) {
   require(ways > 0)
   require(sets > 0)

src/main/scala/huancun/SinkD.scala

@@ -58,6 +58,7 @@ class SinkD(edge: TLEdgeOut)(implicit p: Parameters) extends HuanCunModule {
   io.resp.bits.source := Mux(io.d.valid, io.d.bits.source, RegEnable(io.d.bits.source, io.d.valid))
   io.resp.bits.sink := io.d.bits.sink
   io.resp.bits.denied := io.d.bits.denied
+  io.resp.bits.dirty := io.d.bits.echo.lift(DirtyKey).getOrElse(false.B)
 
   // Save data to Datastorage
   io.bs_waddr.valid := ((needData && io.d.valid && w_safe) || !first) && cache

src/main/scala/huancun/SourceA.scala

@@ -44,5 +44,5 @@ class SourceA(edge: TLEdgeOut)(implicit p: Parameters) extends HuanCunModule {
   a.bits.data := DontCare
   a.bits.corrupt := false.B
   a.bits.user.lift(PreferCacheKey).map( _ := false.B)
-  a.bits.user.lift(DirtyKey).map(_ := true.B)
+  a.bits.echo.lift(DirtyKey).map(_ := true.B)
 }

src/main/scala/huancun/SourceC.scala

@@ -89,7 +89,7 @@ class SourceC(edge: TLEdgeOut)(implicit p: Parameters) extends HuanCunModule {
   queue.io.enq.bits.data := io.bs_rdata.data
   queue.io.enq.bits.corrupt := false.B
   queue.io.enq.bits.user.lift(PreferCacheKey).foreach(_ := true.B)
-  queue.io.enq.bits.user.lift(DirtyKey).foreach(_ := s2_task.dirty)
+  queue.io.enq.bits.echo.lift(DirtyKey).foreach(_ := s2_task.dirty)
 
   io.c <> queue.io.deq
 }

src/main/scala/huancun/SourceD.scala

@@ -136,6 +136,7 @@ class SourceD(implicit p: Parameters) extends HuanCunModule {
   s2_d.bits.denied := false.B
   s2_d.bits.data := s1_queue.io.deq.bits.data
   s2_d.bits.corrupt := false.B
+  s2_d.bits.echo.lift(DirtyKey).foreach(_ := s2_req.dirty)
 
   val s2_can_go = Mux(s2_d.valid, s2_d.ready, s3_ready)
   when(s2_full && s2_can_go) { s2_full := false.B }
@@ -174,6 +175,7 @@ class SourceD(implicit p: Parameters) extends HuanCunModule {
   s3_d.bits.denied := false.B
   s3_d.bits.data := s3_rdata
   s3_d.bits.corrupt := false.B
+  s3_d.bits.echo.lift(DirtyKey).foreach(_ := s3_req.dirty)
 
   s3_queue.io.enq.valid := RegNext(RegNext(
     io.bs_raddr.fire() && !Mux(busy, s1_bypass_hit_reg, s1_bypass_hit_wire),

src/main/scala/huancun/inclusive/MSHR.scala

@@ -418,6 +418,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, DirWrite, TagWr
   od.way := meta.way
   od.off := req.off
   od.denied := bad_grant
+  od.dirty := false.B // TODO
 
   oe.sink := sink
 

src/main/scala/huancun/inclusive/SinkC.scala

@@ -65,7 +65,7 @@ class SinkC(implicit p: Parameters) extends BaseSinkC {
   io.alloc.bits.needHint.foreach(_ := false.B)
   io.alloc.bits.alias.foreach(_ := 0.U)
   io.alloc.bits.preferCache := true.B
-  io.alloc.bits.dirty := c.bits.user.lift(DirtyKey).getOrElse(true.B)
+  io.alloc.bits.dirty := c.bits.echo.lift(DirtyKey).getOrElse(true.B)
   io.alloc.bits.fromProbeHelper := false.B
 
   if (cacheParams.enableDebug) {
@@ -134,7 +134,7 @@ class SinkC(implicit p: Parameters) extends BaseSinkC {
   io.release.bits.size := task_r.size
   io.release.bits.corrupt := false.B
   io.release.bits.user.lift(PreferCacheKey).foreach(_ := true.B)
-  io.release.bits.user.lift(DirtyKey).foreach(_ := true.B) // this is useless
+  io.release.bits.echo.lift(DirtyKey).foreach(_ := true.B) // this is useless
 
   io.resp.valid := c.valid && isResp && can_recv_resp
   io.resp.bits.hasData := hasData

src/main/scala/huancun/noninclusive/MSHR.scala

@@ -793,6 +793,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S
   od.way := self_meta.way
   od.off := req.off
   od.denied := bad_grant
+  od.dirty := false.B // TODO
 
   oe.sink := sink
 

src/main/scala/huancun/noninclusive/SinkC.scala

@@ -45,7 +45,7 @@ class SinkC(implicit p: Parameters) extends BaseSinkC {
   io.alloc.bits.needHint.foreach(_ := false.B)
   io.alloc.bits.alias.foreach(_ := 0.U)
   io.alloc.bits.preferCache := true.B
-  io.alloc.bits.dirty := c.bits.user.lift(DirtyKey).getOrElse(true.B)
+  io.alloc.bits.dirty := c.bits.echo.lift(DirtyKey).getOrElse(true.B)
   io.alloc.bits.fromProbeHelper := false.B
   assert(!io.alloc.fire() || c.fire() && first, "alloc fire, but c channel not fire!")
 
@@ -96,7 +96,7 @@ class SinkC(implicit p: Parameters) extends BaseSinkC {
   io.release.bits.size := task_r.size
   io.release.bits.corrupt := false.B
   io.release.bits.user.lift(PreferCacheKey).foreach(_ := true.B)
-  io.release.bits.user.lift(DirtyKey).foreach(_ := task_r.dirty)
+  io.release.bits.echo.lift(DirtyKey).foreach(_ := task_r.dirty)
 
   val w_fire = io.bs_waddr.fire() && !io.bs_waddr.bits.noop || io.release.fire()
   when(w_fire) {