sourceD: able to handle put request
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wangkaifan
parent
ec35476e23
commit
ca4c919d16
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@ -24,6 +24,7 @@ import chisel3._
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import chisel3.util._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.tilelink.TLMessages.{AcquireBlock, AcquirePerm, ReleaseAck}
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import huancun.utils.HoldUnless
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class SourceD(implicit p: Parameters) extends HuanCunModule {
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/*
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@ -46,16 +47,16 @@ class SourceD(implicit p: Parameters) extends HuanCunModule {
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val bs_wdata = Output(new DSData)
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// data hazards
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val sourceD_r_hazard = ValidIO(new SourceDHazard)
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// putbuffer interface
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val pb_pop = DecoupledIO(new PutBufferPop)
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val pb_beat = Input(new PutBufferBeatEntry)
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})
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io.bs_waddr.valid := false.B
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io.bs_waddr.bits := DontCare
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io.bs_wdata := DontCare
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val d = io.d
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val s1_valid = Wire(Bool())
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val s2_valid, s2_ready = Wire(Bool())
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val s3_valid, s3_ready = Wire(Bool())
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val s4_ready = Wire(Bool())
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// stage1
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val busy = RegInit(false.B)
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@ -64,8 +65,10 @@ class SourceD(implicit p: Parameters) extends HuanCunModule {
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val s1_req = Mux(busy, s1_req_reg, io.task.bits)
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val s1_needData = s1_req.fromA && (
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s1_req.opcode === TLMessages.GrantData ||
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s1_req.opcode === TLMessages.AccessAckData
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s1_req.opcode === TLMessages.AccessAckData ||
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s1_req.opcode === TLMessages.AccessAck // Put should also read data TODO: no need for full-sized PutFullData
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)
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val s1_need_pb = s1_req.fromA && (s1_req.opcode === TLMessages.AccessAck)
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val s1_counter = RegInit(0.U(beatBits.W)) // how many beats have been sent
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val s1_total_beats = Mux(s1_needData, totalBeats(s1_req.size), 0.U(beatBits.W))
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val s1_beat = startBeat(s1_req.off) | s1_counter
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@ -125,6 +128,8 @@ class SourceD(implicit p: Parameters) extends HuanCunModule {
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val s2_latch = s1_valid && s2_ready
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val s2_req = RegEnable(s1_req, s2_latch)
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val s2_needData = RegEnable(s1_needData, s2_latch)
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val s2_last = RegEnable(s1_last, s2_latch)
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val s2_counter = RegEnable(s1_counter, s2_latch)
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val s2_full = RegInit(false.B)
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val s2_releaseAck = s2_req.opcode === ReleaseAck
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val s2_bypass_hit = RegEnable(
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@ -132,6 +137,20 @@ class SourceD(implicit p: Parameters) extends HuanCunModule {
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false.B, s2_latch
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)
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val s2_d = Wire(io.d.cloneType)
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val s2_need_pb = RegEnable(s1_need_pb, s2_latch)
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val s2_need_d = RegEnable(!s1_need_pb || s1_counter === 0.U, s2_latch) // AccessAck for Put should only be fired once
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val s2_valid_pb = RegInit(false.B) // put buffer is valid, wait put buffer fire
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val s2_pdata_raw = io.pb_beat
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val pb_ready = io.pb_pop.ready
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val s2_pdata = HoldUnless(s2_pdata_raw, s2_valid_pb)
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io.pb_pop.valid := s2_valid_pb && s2_req.fromA
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io.pb_pop.bits.bufIdx := s2_req.bufIdx
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io.pb_pop.bits.count := s2_counter
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io.pb_pop.bits.last := s2_last
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when (pb_ready) { s2_valid_pb := false.B }
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when (s2_latch) { s2_valid_pb := s1_need_pb }
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s1_queue.io.deq.ready := s2_full && s2_bypass_hit && s2_d.ready
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s2_d.valid := s2_full && ((s2_bypass_hit && s1_queue.io.deq.valid) || !s2_needData)
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@ -145,35 +164,38 @@ class SourceD(implicit p: Parameters) extends HuanCunModule {
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s2_d.bits.corrupt := false.B
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s2_d.bits.echo.lift(DirtyKey).foreach(_ := s2_req.dirty)
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val s2_can_go = Mux(s2_d.valid, s2_d.ready, s3_ready)
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val s2_can_go = Mux(s2_d.valid, s2_d.ready, s3_ready && (!s2_valid_pb || pb_ready))
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when(s2_full && s2_can_go) { s2_full := false.B }
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when(s2_latch) { s2_full := true.B }
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s2_valid := s2_full && !s2_d.valid
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s2_valid := s2_full && !s2_d.valid && (!s2_valid_pb || pb_ready)
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s2_ready := !s2_full || s2_can_go
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// stage3
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val s3_latch = s2_valid && s3_ready
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val s3_full = RegInit(false.B)
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val s3_valid_d = RegInit(false.B)
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val s3_needData = RegInit(false.B)
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val s3_req = RegEnable(s2_req, s3_latch)
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val s3_counter = RegEnable(s2_counter, s3_latch)
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val s3_pdata = RegEnable(s2_pdata, s3_latch)
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val s3_need_pb = RegEnable(s2_need_pb, s3_latch)
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val s3_releaseAck = RegEnable(s2_releaseAck, s3_latch)
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val s3_d = Wire(io.d.cloneType)
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val s3_queue = Module(new Queue(new DSData, 3, flow = true))
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assert(!s3_full || s3_needData, "Only data task can go to stage3!")
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assert(!s3_valid_d || s3_needData, "Only data task can go to stage3!")
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when(d.ready) {
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s3_full := false.B
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s3_valid_d := false.B
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s3_needData := false.B
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}
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when(s3_latch) {
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s3_full := true.B
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s3_valid_d := s2_need_d
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s3_needData := s2_needData
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}
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val s3_rdata = s3_queue.io.deq.bits.data
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s3_d.valid := s3_valid
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s3_d.valid := s3_valid_d
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s3_d.bits.opcode := s3_req.opcode
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s3_d.bits.param := Mux(s3_releaseAck, 0.U, s3_req.param)
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s3_d.bits.sink := s3_req.sinkId
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@ -189,10 +211,37 @@ class SourceD(implicit p: Parameters) extends HuanCunModule {
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false.B), false.B)
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s3_queue.io.enq.bits := io.bs_rdata
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assert(!s3_queue.io.enq.valid || s3_queue.io.enq.ready)
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s3_queue.io.deq.ready := s3_d.ready && s3_needData && s3_valid
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s3_queue.io.deq.ready := s3_d.ready && s3_needData && s3_valid // TODO: inspect this
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s3_ready := !s3_valid || s3_d.ready
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s3_valid := s3_full
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s3_ready := !s3_valid_d || s3_d.ready
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s3_valid := s3_valid_d
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// stage4
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val s4_latch = s3_valid && s4_ready
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val s4_req = RegEnable(s3_req, s4_latch)
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val s4_rdata = RegEnable(s3_rdata, s4_latch)
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val s4_pdata = RegEnable(s3_pdata, s4_latch)
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val s4_need_pb = RegEnable(s3_need_pb, s4_latch)
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val s4_beat = RegEnable(s3_counter, s4_latch)
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val s4_full = RegInit(false.B)
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when (io.bs_waddr.ready || !s4_need_pb) { s4_full := false.B }
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when (s4_latch) { s4_full := true.B }
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val selects = s4_pdata.mask.asBools
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val mergedData = Cat(selects.zipWithIndex.map { case (s, i) =>
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VecInit(Seq(s4_rdata, s4_pdata.data).map(_((i + 1) * 8 - 1, i * 8)))(s)
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}.reverse) // merge data according to mask
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io.bs_waddr.valid := s4_full && s4_need_pb
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io.bs_waddr.bits.noop := false.B
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io.bs_waddr.bits.way := s4_req.way
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io.bs_waddr.bits.set := s4_req.set
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io.bs_waddr.bits.beat := s4_beat
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io.bs_waddr.bits.write := true.B
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io.bs_wdata.data := mergedData
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s4_ready := !s4_full || io.bs_waddr.ready || !s4_need_pb
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TLArbiter.lowest(edgeIn, io.d, s3_d, s2_d)
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