From b25897ae92975c2cb8bd3782e6c53ef4dad15ef9 Mon Sep 17 00:00:00 2001 From: zhanglinjuan Date: Wed, 15 Sep 2021 18:50:17 +0800 Subject: [PATCH] Fix several bugs --- src/main/scala/huancun/BaseMSHR.scala | 1 + src/main/scala/huancun/Slice.scala | 20 +++++++++++ .../scala/huancun/noninclusive/MSHR.scala | 34 ++++++++++++++----- 3 files changed, 47 insertions(+), 8 deletions(-) diff --git a/src/main/scala/huancun/BaseMSHR.scala b/src/main/scala/huancun/BaseMSHR.scala index 2b85dbc..5e7f387 100644 --- a/src/main/scala/huancun/BaseMSHR.scala +++ b/src/main/scala/huancun/BaseMSHR.scala @@ -35,6 +35,7 @@ class NestedWriteback(implicit p: Parameters) extends HuanCunBundle { val tag = UInt(tagBits.W) val b_toN, b_toB, b_clr_dirty = Bool() val c_set_dirty = Bool() + val c_set_hit = Bool() val clients = if (!cacheParams.inclusive) Some( diff --git a/src/main/scala/huancun/Slice.scala b/src/main/scala/huancun/Slice.scala index 679ee4c..37fbd04 100644 --- a/src/main/scala/huancun/Slice.scala +++ b/src/main/scala/huancun/Slice.scala @@ -146,6 +146,7 @@ class Slice()(implicit p: Parameters) extends HuanCunModule { } val nestedWb = Wire(new NestedWriteback) + nestedWb := DontCare nestedWb.set := Mux(select_c, c_mshr.io.status.bits.set, bc_mshr.io.status.bits.set) nestedWb.tag := Mux(select_c, c_mshr.io.status.bits.tag, bc_mshr.io.status.bits.tag) @@ -179,6 +180,20 @@ class Slice()(implicit p: Parameters) extends HuanCunModule { nestedWb.c_set_dirty := select_c && c_mshr.io.tasks.dir_write.valid && c_wb_dirty + val nestedWb_c_set_hit = c_mshr match { + case c: inclusive.MSHR => + ms.map { + case m => + select_c && c.io.tasks.tag_write.valid && + c.io.tasks.tag_write.bits.tag === m.io.status.bits.tag + } + case c: noninclusive.MSHR => + ms.map { + case m => + select_c && c.io.tasks.tag_write.valid && + c.io.tasks.tag_write.bits.tag === m.io.status.bits.tag + } + } // nested client dir write (bc_mshr, c_mshr) match { @@ -207,11 +222,16 @@ class Slice()(implicit p: Parameters) extends HuanCunModule { } abc_mshr.foreach(_.io.nestedwb := nestedWb) + abc_mshr.zip(nestedWb_c_set_hit.init.init).foreach { + case (m, set_hit) => + m.io.nestedwb.c_set_hit := set_hit + } bc_mshr.io.nestedwb := 0.U.asTypeOf(nestedWb) bc_mshr.io.nestedwb.set := c_mshr.io.status.bits.set bc_mshr.io.nestedwb.tag := c_mshr.io.status.bits.tag bc_mshr.io.nestedwb.c_set_dirty := nestedWb.c_set_dirty + bc_mshr.io.nestedwb.c_set_hit := nestedWb_c_set_hit.init.last bc_mshr match { case mshr: noninclusive.MSHR => mshr.io_releaseThrough := false.B diff --git a/src/main/scala/huancun/noninclusive/MSHR.scala b/src/main/scala/huancun/noninclusive/MSHR.scala index 6e5b8ad..c219ba0 100644 --- a/src/main/scala/huancun/noninclusive/MSHR.scala +++ b/src/main/scala/huancun/noninclusive/MSHR.scala @@ -103,6 +103,8 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S i.U =/= iam && meta.hit }).asUInt.orR + val need_block_downwards = RegInit(false.B) + // When replacing a block in data array, it is not always necessary to send Release, // but only when state perm > clientStates' perm or replacing a dirty block val replace_clients_perm = ParallelMax(self_meta.clientStates) @@ -329,6 +331,15 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S meta_reg.self.clientStates.foreach(_ := INVALID) } } + val nested_c_hit_reg = RegInit(false.B) + val nested_c_hit = WireInit(nested_c_hit_reg) + when (meta_valid && !self_meta.hit && req.fromA && + io.nestedwb.set === req.set && io.nestedwb.c_set_hit + ) { + nested_c_hit := true.B + nested_c_hit_reg := true.B + } + meta_reg.clients.zipWithIndex.foreach { case (reg, i) => when(change_clients_meta(i)) { @@ -336,7 +347,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S // reg.state := BRANCH } when((io.nestedwb.clients.get) (i).isToN) { - // reg.state := INVALID + reg.state := INVALID reg.hit := false.B } } @@ -418,6 +429,8 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S probe_dirty := false.B probes_done := 0.U bad_grant := false.B + need_block_downwards := false.B + nested_c_hit_reg := false.B } @@ -493,6 +506,8 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S w_probeackfirst := false.B w_probeacklast := false.B w_probeack := false.B + s_wbselfdir := false.B + when (!self_meta.hit) { s_wbselftag := false.B } } def a_schedule(): Unit = { // A channel requests @@ -556,12 +571,6 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S } } } - when (probe_dirty) { - s_wbselfdir := false.B - when (!self_meta.hit) { - s_wbselftag := false.B - } - } // need grantack when(req_acquire) { w_grantack := false.B @@ -658,7 +667,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S oa.tag := req.tag oa.set := req.set - oa.opcode := Mux(clients_hit || self_meta.hit, AcquirePerm, AcquireBlock) + oa.opcode := Mux((clients_hit || self_meta.hit) && !need_block_downwards, AcquirePerm, AcquireBlock) oa.param := Mux(req_needT, Mux(clients_hit || self_meta.hit, BtoT, NtoT), NtoB) oa.source := io.id oa.needData := !(req.opcode === AcquirePerm) || req.size =/= offsetBits.U @@ -896,6 +905,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S s_writeprobe := false.B } } + val a_need_data = req.fromA && (req.opcode === Get || req.opcode === AcquireBlock || req.opcode === Hint) when(io.resps.sink_c.valid) { val resp = io.resps.sink_c.bits probes_done := probes_done | probeack_bit @@ -904,6 +914,14 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S w_probeack := w_probeack || probeack_last && (resp.last || req.off === 0.U) probe_dirty := probe_dirty || resp.hasData && !w_probeackfirst + when (a_need_data && probeack_last && resp.last && !resp.hasData && !nested_c_hit && !self_meta.hit) { + s_acquire := false.B + w_grantfirst := false.B + w_grantlast := false.B + w_grant := false.B + s_grantack := false.B + need_block_downwards := true.B + } } when(io.resps.sink_d.valid) { when(io.resps.sink_d.bits.opcode === Grant || io.resps.sink_d.bits.opcode === GrantData) {