forked from chunyexixiaoyu/xiuos
185 lines
6.8 KiB
C
185 lines
6.8 KiB
C
/*
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* Copyright 2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/**
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* @file board.c
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* @brief support imxrt1052-board init configure and start-up
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2021-05-29
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*/
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/*************************************************
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File name: board.c
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Description: support imxrt1052-board init configure and driver/task/... init
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Others: take SDK_2.6.1_MIMXRT1052xxxxB/devices/MIMXRT1052/project_template/board.c
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History:
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1. Date: 2021-05-29
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Author: AIIT XUOS Lab
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Modification:
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1. support imxrt1052-board InitBoardHardware
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*************************************************/
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#include "board.h"
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#include "pin_mux.h"
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#include "fsl_iomuxc.h"
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#include "fsl_gpio.h"
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#include <connect_uart.h>
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#include "fsl_lpuart.h"
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#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
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4 bits for subpriority */
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#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
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3 bits for subpriority */
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#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
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2 bits for subpriority */
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#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
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1 bits for subpriority */
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#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
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0 bits for subpriority */
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/* MPU configuration. */
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static void BOARD_ConfigMPU(void)
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{
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/* Disable I cache and D cache */
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SCB_DisableICache();
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SCB_DisableDCache();
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/* Disable MPU */
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ARM_MPU_Disable();
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/* Region 0 setting */
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MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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/* Region 1 setting */
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MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
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/* Region 2 setting */
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// spi flash: normal type, cacheable, no bufferable, no shareable
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MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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/* Region 3 setting */
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MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
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/* Region 4 setting */
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MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
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/* Region 5 setting */
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MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
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/* Region 6 setting */
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MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
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#if defined(BSP_USING_SDRAM)
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/* Region 7 setting */
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MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
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/* Region 8 setting */
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MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
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#endif
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/* Enable MPU */
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ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
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/* Enable I cache and D cache */
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SCB_EnableDCache();
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SCB_EnableICache();
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}
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/* This is the timer interrupt service routine. */
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void SysTick_Handler(int irqn, void *arg)
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{
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TickAndTaskTimesliceUpdate();
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}
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DECLARE_HW_IRQ(SYSTICK_IRQN, SysTick_Handler, NONE);
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#ifdef BSP_USING_LPUART
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void imxrt_uart_pins_init(void)
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{
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#ifdef BSP_USING_LPUART1
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
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0x10B0u); /* Slew Rate Field: Slow Slew Rate
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Drive Strength Field: R0/6
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Speed Field: medium(100MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Keeper
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Pull Up / Down Config. Field: 100K Ohm Pull Down
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
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0x10B0u); /* Slew Rate Field: Slow Slew Rate
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Drive Strength Field: R0/6
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Speed Field: medium(100MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Keeper
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Pull Up / Down Config. Field: 100K Ohm Pull Down
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Hyst. Enable Field: Hysteresis Disabled */
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#endif
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#ifdef BSP_USING_LPUART2
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
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0U);
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
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0x10B0u);
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
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0x10B0u);
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#endif
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}
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#endif /* BSP_USING_LPUART */
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/**
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* This function will initial rt1050 board.
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*/
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void InitBoardHardware()
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{
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BOARD_ConfigMPU();
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BOARD_InitPins();
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BOARD_BootClockRUN();
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NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
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SysTick_Config(SystemCoreClock / TICK_PER_SECOND);
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#ifdef BSP_USING_LPUART
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imxrt_uart_pins_init();
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#endif
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InitBoardMemory((void *)HEAP_BEGIN, (void *)HEAP_END);
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Imrt1052HwUartInit();
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InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
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}
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