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Add nuttx to the system framework, which is 10.1.0

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TangYiwen123 2021-06-09 14:34:06 +08:00
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commit b907bfab1c
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524
Ubiquitous/Nuttx/nuttx/arch/arm/src/sama5/sam_oneshot.c Normal file
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/****************************************************************************
* arch/arm/src/sama5/sam_oneshot.c
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* The Atmel sample code has a BSD compatible license that requires this
* copyright notice:
*
* Copyright (c) 2011, Atmel Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the names NuttX nor Atmel nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* References:
*
* SAMA5D3 Series Data Sheet
* Atmel NoOS sample code.
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include <errno.h>
#include <nuttx/irq.h>
#include <nuttx/clock.h>
#include "sam_oneshot.h"
#include "sam_freerun.h"
#ifdef CONFIG_SAMA5_ONESHOT
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: sam_oneshot_handler
*
* Description:
* Timer interrupt callback. When the oneshot timer interrupt expires,
* this function will be called. It will forward the call to the next
* level up.
*
* Input Parameters:
* tch - The handle that represents the timer state
* arg - An opaque argument provided when the interrupt was registered
* sr - The value of the timer interrupt status register at the time
* that the interrupt occurred.
*
* Returned Value:
* None
*
****************************************************************************/
static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
{
struct sam_oneshot_s *oneshot = (struct sam_oneshot_s *)arg;
oneshot_handler_t oneshot_handler;
void *oneshot_arg;
tmrinfo("Expired...\n");
DEBUGASSERT(oneshot && oneshot->handler);
/* The clock was stopped, but not disabled when the RC match occurred.
* Disable the TC now and disable any further interrupts.
*/
sam_tc_attach(oneshot->tch, NULL, NULL, 0);
sam_tc_stop(oneshot->tch);
/* The timer is no longer running */
oneshot->running = false;
/* Forward the event, clearing out any vestiges */
oneshot_handler = (oneshot_handler_t)oneshot->handler;
oneshot->handler = NULL;
oneshot_arg = (void *)oneshot->arg;
oneshot->arg = NULL;
#ifdef CONFIG_SAMA5_FREERUN
oneshot->start_count = 0;
#endif
oneshot_handler(oneshot_arg);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: sam_oneshot_initialize
*
* Description:
* Initialize the oneshot timer wrapper
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure
* chan Timer counter channel to be used. See the TC_CHAN*
* definitions in arch/arm/src/sama5/sam_tc.h.
* resolution The required resolution of the timer in units of
* microseconds. NOTE that the range is restricted to the
* range of uint16_t (excluding zero).
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
uint16_t resolution)
{
uint32_t frequency;
uint32_t divisor;
uint32_t cmr;
int ret;
tmrinfo("chan=%d resolution=%d usec\n", chan, resolution);
DEBUGASSERT(oneshot && resolution > 0);
/* Get the TC frequency the corresponds to the requested resolution */
frequency = USEC_PER_SEC / (uint32_t)resolution;
/* The pre-calculate values to use when we start the timer */
ret = sam_tc_divisor(frequency, &divisor, &cmr);
if (ret < 0)
{
tmrerr("ERROR: sam_tc_divisor failed: %d\n", ret);
return ret;
}
tmrinfo("frequency=%lu, divisor=%lu, cmr=%08lx\n",
(unsigned long)frequency, (unsigned long)divisor,
(unsigned long)cmr);
/* Allocate the timer/counter and select its mode of operation
*
* CMR_TCCLKS - Returned by sam_tc_divisor
* TC_CMR_CLKI=0 - Not inverted
* TC_CMR_BURST_NONE - Not gated by an external signal
* TC_CMR_CPCSTOP=1 - Stop the clock on an RC compare event
* TC_CMR_CPCDIS=0 - Don't disable the clock on an RC compare event
* TC_CMR_EEVTEDG_NONE - No external events (and, hence, no edges
* TC_CMR_EEVT_TIOB - ???? REVISIT
* TC_CMR_ENET=0 - External event trigger disabled
* TC_CMR_WAVSEL_UPRC - TC_CV is incremented from 0 to the value of RC,
* then automatically reset on a RC Compare
* TC_CMR_WAVE - Waveform mode
* TC_CMR_ACPA_NONE - RA compare has no effect on TIOA
* TC_CMR_ACPC_NONE - RC compare has no effect on TIOA
* TC_CMR_AEEVT_NONE - No external event effect on TIOA
* TC_CMR_ASWTRG_NONE - No software trigger effect on TIOA
* TC_CMR_BCPB_NONE - RB compare has no effect on TIOB
* TC_CMR_BCPC_NONE - RC compare has no effect on TIOB
* TC_CMR_BEEVT_NONE - No external event effect on TIOB
* TC_CMR_BSWTRG_NONE - No software trigger effect on TIOB
*/
cmr |= (TC_CMR_BURST_NONE | TC_CMR_CPCSTOP | TC_CMR_EEVTEDG_NONE |
TC_CMR_EEVT_TIOB | TC_CMR_WAVSEL_UPRC | TC_CMR_WAVE |
TC_CMR_ACPA_NONE | TC_CMR_ACPC_NONE | TC_CMR_AEEVT_NONE |
TC_CMR_ASWTRG_NONE | TC_CMR_BCPB_NONE | TC_CMR_BCPC_NONE |
TC_CMR_BEEVT_NONE | TC_CMR_BSWTRG_NONE);
oneshot->tch = sam_tc_allocate(chan, cmr);
if (!oneshot->tch)
{
tmrerr("ERROR: Failed to allocate timer channel %d\n", chan);
return -EBUSY;
}
/* Initialize the remaining fields in the state structure and return
* success.
*/
oneshot->chan = chan;
oneshot->running = false;
oneshot->handler = NULL;
oneshot->arg = NULL;
#ifdef CONFIG_SAMA5_FREERUN
oneshot->start_count = 0;
#endif
return OK;
}
/****************************************************************************
* Name: sam_oneshot_max_delay
*
* Description:
* Return the maximum delay supported by the one shot timer (in
* microseconds).
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* sam_oneshot_initialize();
* usec The location in which to return the maximum delay.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec)
{
DEBUGASSERT(oneshot != NULL && usec != NULL);
*usec = (0xffffull * USEC_PER_SEC) /
(uint64_t)sam_tc_divfreq(oneshot->tch);
return OK;
}
/****************************************************************************
* Name: sam_oneshot_start
*
* Description:
* Start the oneshot timer
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* sam_oneshot_initialize();
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int sam_oneshot_start(struct sam_oneshot_s *oneshot,
struct sam_freerun_s *freerun,
oneshot_handler_t handler, void *arg,
const struct timespec *ts)
{
uint64_t usec;
uint64_t regval;
irqstate_t flags;
tmrinfo("handler=%p arg=%p, ts=(%lu, %lu)\n",
handler, arg, (unsigned long)ts->tv_sec,
(unsigned long)ts->tv_nsec);
DEBUGASSERT(oneshot && handler && ts);
/* Was the oneshot already running? */
flags = enter_critical_section();
if (oneshot->running)
{
/* Yes.. then cancel it */
tmrinfo("Already running... cancelling\n");
sam_oneshot_cancel(oneshot, freerun, NULL);
}
/* Save the new handler and its argument */
oneshot->handler = handler;
oneshot->arg = arg;
/* Express the delay in microseconds */
usec = (uint64_t)ts->tv_sec *
USEC_PER_SEC + (uint64_t)(ts->tv_nsec /
NSEC_PER_USEC);
/* Get the timer counter frequency and determine the number of counts
* need to achieve the requested delay.
*
* frequency = ticks / second
* ticks = seconds * frequency
* = (usecs * frequency) / USEC_PER_SEC;
*/
regval = (usec * (uint64_t)sam_tc_divfreq(oneshot->tch)) / USEC_PER_SEC;
tmrinfo("usec=%llu regval=%08llx\n", usec, regval);
DEBUGASSERT(regval <= UINT32_MAX);
/* Set up to receive the callback when the interrupt occurs */
sam_tc_attach(oneshot->tch, sam_oneshot_handler, oneshot,
TC_INT_CPCS);
/* Set RC so that an event will be triggered when TC_CV register counts
* up to RC.
*/
sam_tc_setregister(oneshot->tch, TC_REGC, (uint32_t)regval);
/* Start the counter */
sam_tc_start(oneshot->tch);
#ifdef CONFIG_SAMA5_FREERUN
/* The function sam_tc_start() starts the timer/counter by setting the
* bits TC_CCR_CLKEN and TC_CCR_SWTRG in the channel control register.
* The first one enables the timer/counter the latter performs an
* software trigger, which starts the clock and sets the counter
* register to zero. This reset is performed with the next valid edge
* of the selected clock. Thus it can take up USEC_PER_TICK microseconds
* until the counter register becomes zero.
*
* If the timer is canceled within this period the counter register holds
* the counter value for the last timer/counter run. To circumvent this
* the counter value of the freerun timer/counter is stored at each start
* of the oneshot timer/counter.
*
* The function up_timer_gettime() could also be used for this but it takes
* too long. If up_timer_gettime() is called within this function the
* problem vanishes at least if compiled with no optimisation.
*/
if (freerun != NULL)
{
oneshot->start_count = sam_tc_getcounter(freerun->tch);
}
#endif
/* Enable interrupts. We should get the callback when the interrupt
* occurs.
*/
oneshot->running = true;
leave_critical_section(flags);
return OK;
}
/****************************************************************************
* Name: sam_oneshot_cancel
*
* Description:
* Cancel the oneshot timer and return the time remaining on the timer.
*
* NOTE: This function may execute at a high rate with no timer running (as
* when pre-emption is enabled and disabled).
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* sam_oneshot_initialize();
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running. ts may be zero in which case the time remaining
* is not returned.
*
* Returned Value:
* Zero (OK) is returned on success. A call to up_timer_cancel() when
* the timer is not active should also return success; a negated errno
* value is returned on any failure.
*
****************************************************************************/
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
struct sam_freerun_s *freerun, struct timespec *ts)
{
irqstate_t flags;
uint64_t usec;
uint64_t sec;
uint64_t nsec;
uint32_t count;
uint32_t rc;
/* Was the timer running? */
flags = enter_critical_section();
if (!oneshot->running)
{
/* No.. Just return zero timer remaining and successful cancellation.
* This function may execute at a high rate with no timer running
* (as when pre-emption is enabled and disabled).
*/
ts->tv_sec = 0;
ts->tv_nsec = 0;
leave_critical_section(flags);
return OK;
}
/* Yes.. Get the timer counter and rc registers and stop the counter. If
* the counter expires while we are doing this, the counter clock will be
* stopped, but the clock will not be disabled.
*
* The expected behavior is that the counter register will freezes at
* a value equal to the RC register when the timer expires. The counter
* should have values between 0 and RC in all other cased.
*
* REVISIT: This does not appear to be the case.
*/
tmrinfo("Cancelling...\n");
count = sam_tc_getcounter(oneshot->tch);
rc = sam_tc_getregister(oneshot->tch, TC_REGC);
#ifdef CONFIG_SAMA5_FREERUN
/* In the case the timer/counter was canceled very short after its start,
* the counter register can hold the wrong value (the value of the last
* run). To prevent this the counter value is set to zero if not at
* least on tick passed since the start of the timer/counter.
*/
if (count > 0 && freerun != NULL &&
sam_tc_getcounter(freerun->tch) == oneshot->start_count)
{
count = 0;
}
#endif
/* Now we can disable the interrupt and stop the timer. */
sam_tc_attach(oneshot->tch, NULL, NULL, 0);
sam_tc_stop(oneshot->tch);
oneshot->running = false;
oneshot->handler = NULL;
oneshot->arg = NULL;
leave_critical_section(flags);
/* Did the caller provide us with a location to return the time
* remaining?
*/
if (ts)
{
/* Yes.. then calculate and return the time remaining on the
* oneshot timer.
*/
tmrinfo("rc=%lu count=%lu usec=%lu\n",
(unsigned long)rc, (unsigned long)count, (unsigned long)usec);
/* REVISIT: I am not certain why the timer counter value sometimes
* exceeds RC. Might be a bug, or perhaps the counter does not stop
* in all cases.
*/
if (count >= rc)
{
/* No time remaining (?) */
ts->tv_sec = 0;
ts->tv_nsec = 0;
}
else
{
/* The total time remaining is the difference. Convert that
* to units of microseconds.
*
* frequency = ticks / second
* seconds = ticks * frequency
* usecs = (ticks * USEC_PER_SEC) / frequency;
*/
usec = (((uint64_t)(rc - count)) * USEC_PER_SEC) /
sam_tc_divfreq(oneshot->tch);
/* Each time the timer/counter is canceled the time calculated from
* the two registers (counter and REGC) is accurate up to an error
* between 0 and USEC_PER_TICK microseconds. To correct this error
* one tick which means USEC_PER_TICK microseconds are subtracted.
*/
usec = usec > USEC_PER_TICK ? usec - USEC_PER_TICK : 0;
/* Return the time remaining in the correct form */
sec = usec / USEC_PER_SEC;
nsec = ((usec) - (sec * USEC_PER_SEC)) * NSEC_PER_USEC;
ts->tv_sec = (time_t)sec;
ts->tv_nsec = (unsigned long)nsec;
}
tmrinfo("remaining (%lu, %lu)\n",
(unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
}
return OK;
}
#endif /* CONFIG_SAMA5_ONESHOT */

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/****************************************************************************
* arch/arm/src/sama5/sam_oneshot.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_ONESHOT_H
#define __ARCH_ARM_SRC_SAMA5_SAM_ONESHOT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include "sam_tc.h"
#ifdef CONFIG_SAMA5_ONESHOT
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define ONESHOT_INITIALIZED(s) (((s)->tch) != NULL)
/****************************************************************************
* Public Types
****************************************************************************/
/* This describes the callback function that will be invoked when the oneshot
* timer expires. The oneshot fires, the client will receive:
*
* arg - The opaque argument provided when the interrupt was registered
*/
typedef void (*oneshot_handler_t)(void *arg);
/* The oneshot client must allocate an instance of this structure and called
* sam_oneshot_initialize() before using the oneshot facilities. The client
* should not access the contents of this structure directly since the
* contents are subject to change.
*/
struct sam_oneshot_s
{
uint8_t chan; /* The timer/counter in use */
volatile bool running; /* True: the timer is running */
TC_HANDLE tch; /* Handle returned by
* sam_tc_initialize() */
volatile oneshot_handler_t handler; /* Oneshot expiration callback */
volatile void *arg; /* The argument that will accompany
* the callback */
#ifdef CONFIG_SAMA5_FREERUN
volatile uint32_t start_count; /* Stores the value of the freerun counter,
* at each start of the oneshot timer. Is necessary
* to find out if the oneshot counter was updated
* correctly at the time of the call to
* sam_oneshot_cancel or not. */
#endif
};
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_oneshot_initialize
*
* Description:
* Initialize the oneshot timer wrapper
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure
* chan Timer counter channel to be used. See the TC_CHAN*
* definitions in arch/arm/src/sama5/sam_tc.h.
* resolution The required resolution of the timer in units of
* microseconds. NOTE that the range is restricted to the
* range of uint16_t (excluding zero).
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
uint16_t resolution);
/****************************************************************************
* Name: sam_oneshot_max_delay
*
* Description:
* Return the maximum delay supported by the one shot timer (in
* microseconds).
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* sam_oneshot_initialize();
* usec The location in which to return the maximum delay.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
/****************************************************************************
* Name: sam_oneshot_start
*
* Description:
* Start the oneshot timer
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
* sam_freerun_initialize(). May be NULL if there is no matching
* free-running timer.
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
struct sam_freerun_s;
int sam_oneshot_start(struct sam_oneshot_s *oneshot,
struct sam_freerun_s *freerun,
oneshot_handler_t handler, void *arg,
const struct timespec *ts);
/****************************************************************************
* Name: sam_oneshot_cancel
*
* Description:
* Cancel the oneshot timer and return the time remaining on the timer.
*
* NOTE: This function may execute at a high rate with no timer running (as
* when pre-emption is enabled and disabled).
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
* sam_freerun_initialize(). May be NULL if there is no matching
* free-running timer.
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running.
*
* Returned Value:
* Zero (OK) is returned on success. A call to up_timer_cancel() when
* the timer is not active should also return success; a negated errno
* value is returned on any failure.
*
****************************************************************************/
struct sam_freerun_s;
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
struct sam_freerun_s *freerun, struct timespec *ts);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* CONFIG_SAMA5_ONESHOT */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_ONESHOT_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_oneshot_lowerhalf.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <limits.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/kmalloc.h>
#include <nuttx/timers/oneshot.h>
#include "sam_oneshot.h"
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure describes the state of the oneshot timer lower-half
* driver
*/
struct sam_oneshot_lowerhalf_s
{
/* This is the part of the lower half driver that is visible to the upper-
* half client of the driver. This must be the first thing in this
* structure so that pointers to struct oneshot_lowerhalf_s are cast
* compatible to struct sam_oneshot_lowerhalf_s and vice versa.
*/
struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */
/* Private lower half data follows */
struct sam_oneshot_s oneshot; /* SAM-specific oneshot state */
oneshot_callback_t callback; /* internal handler that receives callback */
FAR void *arg; /* Argument that is passed to the handler */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static void sam_oneshot_handler(void *arg);
static int sam_max_delay(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts);
static int sam_start(FAR struct oneshot_lowerhalf_s *lower,
oneshot_callback_t callback, FAR void *arg,
FAR const struct timespec *ts);
static int sam_cancel(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts);
/****************************************************************************
* Private Data
****************************************************************************/
/* Lower half operations */
static const struct oneshot_operations_s g_oneshot_ops =
{
.max_delay = sam_max_delay,
.start = sam_start,
.cancel = sam_cancel,
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: sam_oneshot_handler
*
* Description:
* Timer expiration handler
*
* Input Parameters:
* arg - Should be the same argument provided when sam_oneshot_start()
* was called.
*
* Returned Value:
* None
*
****************************************************************************/
static void sam_oneshot_handler(void *arg)
{
FAR struct sam_oneshot_lowerhalf_s *priv =
(FAR struct sam_oneshot_lowerhalf_s *)arg;
oneshot_callback_t callback;
FAR void *cbarg;
DEBUGASSERT(priv != NULL);
/* Perhaps the callback was nullified in a race condition with
* sam_cancel?
*/
if (priv->callback)
{
/* Sample and nullify BEFORE executing callback (in case the callback
* restarts the oneshot).
*/
callback = priv->callback;
cbarg = priv->arg;
priv->callback = NULL;
priv->arg = NULL;
/* Then perform the callback */
callback(&priv->lh, cbarg);
}
}
/****************************************************************************
* Name: sam_max_delay
*
* Description:
* Determine the maximum delay of the one-shot timer (in microseconds)
*
* Input Parameters:
* lower An instance of the lower-half oneshot state structure. This
* structure must have been previously initialized via a call to
* oneshot_initialize();
* ts The location in which to return the maximum delay.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
static int sam_max_delay(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts)
{
FAR struct sam_oneshot_lowerhalf_s *priv =
(FAR struct sam_oneshot_lowerhalf_s *)lower;
uint64_t usecs;
int ret;
DEBUGASSERT(priv != NULL && ts != NULL);
ret = sam_oneshot_max_delay(&priv->oneshot, &usecs);
if (ret >= 0)
{
uint64_t sec = usecs / 1000000;
usecs -= 1000000 * sec;
ts->tv_sec = (time_t)sec;
ts->tv_nsec = (long)(usecs * 1000);
}
return ret;
}
/****************************************************************************
* Name: sam_start
*
* Description:
* Start the oneshot timer
*
* Input Parameters:
* lower An instance of the lower-half oneshot state structure. This
* structure must have been previously initialized via a call to
* oneshot_initialize();
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
static int sam_start(FAR struct oneshot_lowerhalf_s *lower,
oneshot_callback_t callback, FAR void *arg,
FAR const struct timespec *ts)
{
FAR struct sam_oneshot_lowerhalf_s *priv =
(FAR struct sam_oneshot_lowerhalf_s *)lower;
irqstate_t flags;
int ret;
DEBUGASSERT(priv != NULL && callback != NULL && ts != NULL);
/* Save the callback information and start the timer */
flags = enter_critical_section();
priv->callback = callback;
priv->arg = arg;
ret = sam_oneshot_start(&priv->oneshot, NULL,
sam_oneshot_handler, priv, ts);
leave_critical_section(flags);
if (ret < 0)
{
tmrerr("ERROR: sam_oneshot_start failed: %d\n", flags);
}
return ret;
}
/****************************************************************************
* Name: sam_cancel
*
* Description:
* Cancel the oneshot timer and return the time remaining on the timer.
*
* NOTE: This function may execute at a high rate with no timer running (as
* when pre-emption is enabled and disabled).
*
* Input Parameters:
* lower Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* oneshot_initialize();
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running.
*
* Returned Value:
* Zero (OK) is returned on success. A call to up_timer_cancel() when
* the timer is not active should also return success; a negated errno
* value is returned on any failure.
*
****************************************************************************/
static int sam_cancel(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts)
{
FAR struct sam_oneshot_lowerhalf_s *priv =
(FAR struct sam_oneshot_lowerhalf_s *)lower;
irqstate_t flags;
int ret;
DEBUGASSERT(priv != NULL);
/* Cancel the timer */
flags = enter_critical_section();
ret = sam_oneshot_cancel(&priv->oneshot, NULL, ts);
priv->callback = NULL;
priv->arg = NULL;
leave_critical_section(flags);
if (ret < 0)
{
tmrerr("ERROR: sam_oneshot_cancel failed: %d\n", flags);
}
return ret;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: oneshot_initialize
*
* Description:
* Initialize the oneshot timer and return a oneshot lower half driver
* instance.
*
* Input Parameters:
* chan Timer counter channel to be used.
* resolution The required resolution of the timer in units of
* microseconds. NOTE that the range is restricted to the
* range of uint16_t (excluding zero).
*
* Returned Value:
* On success, a non-NULL instance of the oneshot lower-half driver is
* returned. NULL is return on any failure.
*
****************************************************************************/
FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
uint16_t resolution)
{
FAR struct sam_oneshot_lowerhalf_s *priv;
int ret;
/* Allocate an instance of the lower half driver */
priv = (FAR struct sam_oneshot_lowerhalf_s *)
kmm_zalloc(sizeof(struct sam_oneshot_lowerhalf_s));
if (priv == NULL)
{
tmrerr("ERROR: Failed to initialized state structure\n");
return NULL;
}
/* Initialize the lower-half driver structure */
priv->lh.ops = &g_oneshot_ops;
/* Initialize the contained SAM oneshot timer */
ret = sam_oneshot_initialize(&priv->oneshot, chan, resolution);
if (ret < 0)
{
tmrerr("ERROR: sam_oneshot_initialize failed: %d\n", ret);
kmm_free(priv);
return NULL;
}
return &priv->lh;
}

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/****************************************************************************
* arch/arm/src/sama5/sam_pck.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <arch/board/board.h>
#include "hardware/sam_pinmap.h"
#include "arm_arch.h"
#include "sam_pio.h"
#include "sam_isi.h"
#include "sam_pck.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: sam_pck_configure
*
* Description:
* Configure a programmable clock output. The selected PCK is programmed
* to the selected frequency using either PLLA or the MCK as the source
* clock (depending on the value of the selected frequency). The clock
* is initially disabled. You must call sam_pck_enable() to enable the
* clock after it has been configured.
*
* Input Parameters:
* pckid - Identifies the programmable clock output (0, 1, or 2)
* clocksrc - MCK or SCK. If MCK is selected, the logic will automatically
* select the PLLACK clock if it seems like a better choice.
* frequency - Defines the desired frequency. The exact frequency may
* not be attainable. In this case, frequency is interpreted to be
* a not-to-exceed frequency.
*
* Returned Value:
* The actual frequency of the clock output.
*
****************************************************************************/
uint32_t sam_pck_configure(enum pckid_e pckid, enum pckid_clksrc_e clksrc,
uint32_t frequency)
{
uint32_t regval;
uint32_t clkin;
uint32_t actual;
#ifdef SAMA5_HAVE_PCK_INT_PRES
uint32_t pres;
#endif
/* Pick a clock source. Several are possible but only MCK, PLLA, the
* MAINCK,or SCK are supported here.
*/
switch (clksrc)
{
case PCKSRC_MCK: /* Source clock = MCK or PLLACK */
{
/* Pick either the MCK or the PLLACK, whichever will best realize
* the target frequency.
*/
DEBUGASSERT(BOARD_MCK_FREQUENCY < BOARD_PLLA_FREQUENCY);
/* Pick the PLLACK if it seems like a better choice */
if (frequency <= BOARD_MCK_FREQUENCY ||
frequency < BOARD_PLLA_FREQUENCY / 64)
{
regval = PMC_PCK_CSS_MCK;
clkin = BOARD_MCK_FREQUENCY;
}
else
{
regval = PMC_PCK_CSS_PLLA;
clkin = BOARD_PLLA_FREQUENCY;
}
}
break;
case PCKSRC_MAINCK: /* Source clock = MAIN clock */
regval = PMC_PCK_CSS_MAIN;
clkin = BOARD_MAINCK_FREQUENCY;
break;
case PCKSRC_SCK: /* Source clock = SCK */
regval = PMC_PCK_CSS_SLOW;
clkin = BOARD_SLOWCLK_FREQUENCY;
break;
default:
_err("ERROR: Unknown clock source\n");
return 0;
}
#ifdef SAMA5_HAVE_PCK_INT_PRES
/* Programmable Clock frequency is selected clock frequency divided by
* PRES + 1
*/
pres = clkin / frequency;
if (pres < 1)
{
pres = 1;
}
else if (pres > 256)
{
pres = 256;
}
regval |= PMC_PCK_PRES(pres - 1);
actual = clkin / pres;
#else
/* The the larger smallest divisor that does not exceed the requested
* frequency.
*/
if (frequency >= clkin)
{
regval |= PMC_PCK_PRES_DIV1;
actual = clkin;
}
else if (frequency >= (clkin >> 1))
{
regval |= PMC_PCK_PRES_DIV2;
actual = clkin >> 1;
}
else if (frequency >= (clkin >> 2))
{
regval |= PMC_PCK_PRES_DIV4;
actual = clkin >> 2;
}
else if (frequency >= (clkin >> 3))
{
regval |= PMC_PCK_PRES_DIV8;
actual = clkin >> 3;
}
else if (frequency >= (clkin >> 4))
{
regval |= PMC_PCK_PRES_DIV16;
actual = clkin >> 4;
}
else if (frequency >= (clkin >> 5))
{
regval |= PMC_PCK_PRES_DIV32;
actual = clkin >> 5;
}
else if (frequency >= (clkin >> 6))
{
regval |= PMC_PCK_PRES_DIV64;
actual = clkin >> 6;
}
else
{
serr("ERROR: frequency cannot be realized.\n");
serr(" frequency=%lu clkin=%lu\n",
(unsigned long)frequency, (unsigned long)clkin);
return 0;
}
#endif
/* Disable the programmable clock, configure the PCK output pin, then set
* the selected configuration.
*/
switch (pckid)
{
case PCK0:
putreg32(PMC_PCK0, SAM_PMC_SCDR);
#ifdef PIO_PMC_PCK0
sam_configpio(PIO_PMC_PCK0);
#endif
putreg32(regval, SAM_PMC_PCK0);
break;
case PCK1:
putreg32(PMC_PCK1, SAM_PMC_SCDR);
#ifdef PIO_PMC_PCK1
sam_configpio(PIO_PMC_PCK1);
#endif
putreg32(regval, SAM_PMC_PCK1);
break;
case PCK2:
putreg32(PMC_PCK2, SAM_PMC_SCDR);
#ifdef PIO_PMC_PCK2
sam_configpio(PIO_PMC_PCK2);
#endif
putreg32(regval, SAM_PMC_PCK2);
break;
default:
return -EINVAL;
}
/* And return the actual frequency */
return actual;
}
/****************************************************************************
* Function: sam_pck_enable
*
* Description:
* Enable or disable a programmable clock output.
*
* Input Parameters:
* pckid - Identifies the programmable clock output (0, 1, or 2)
* enable - True: enable the clock output, False: disable the clock output
*
* Returned Value:
* None
*
****************************************************************************/
void sam_pck_enable(enum pckid_e pckid, bool enable)
{
uintptr_t regaddr;
uint32_t regval;
/* Select the bit in the PMC_SDER or PMC_SCER corresponding to the
* programmable clock.
*/
regval = PMC_PCKN(pckid);
/* Select the SDER or SCER */
regaddr = enable ? SAM_PMC_SCER : SAM_PMC_SCDR;
/* And do the deead */
putreg32(regval, regaddr);
}

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/****************************************************************************
* arch/arm/src/sama5/sam_pck.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_PCK_H
#define __ARCH_ARM_SRC_SAMA5_SAM_PCK_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_pmc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/* Identifies the programmable clock */
enum pckid_e
{
PCK0 = 0,
PCK1,
PCK2
};
enum pckid_clksrc_e
{
PCKSRC_MCK = 0, /* Source clock is the master clock (MCK) or PLLA output (PLLACK) */
PCKSRC_MAINCK, /* Source clock is the main clock (probably the XTAL) */
PCKSRC_SCK /* Source clock is the slow clock (SCK) */
};
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Function: sam_pck_configure
*
* Description:
* Configure a programmable clock output. The selected PCK is programmed
* to the selected frequency using either PLLA or the MCK as the source
* clock (depending on the value of the selected frequency). The clock
* is initially disabled. You must call sam_pck_enable() to enable the
* clock after it has been configured.
*
* Input Parameters:
* pckid - Identifies the programmable clock output (0, 1, or 2)
* clocksrc - MCK or SCK. If MCK is selected, the logic will automatically
* select the PLLACK clock if it seems like a better choice.
* frequency - Defines the desired frequency. The exact frequency may
* not be attainable. In this case, frequency is interpreted to be
* a not-to-exceed frequency.
*
* Returned Value:
* The actual frequency of the clock output.
*
****************************************************************************/
uint32_t sam_pck_configure(enum pckid_e pckid, enum pckid_clksrc_e clksrc,
uint32_t frequency);
/****************************************************************************
* Function: sam_pck_enable
*
* Description:
* Enable or disable a programmable clock output.
*
* Input Parameters:
* pckid - Identifies the programmable clock output (0, 1, or 2)
* enable - True: enable the clock output, False: disable the clock output
*
* Returned Value:
* None
*
****************************************************************************/
void sam_pck_enable(enum pckid_e pckid, bool enable);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_PCK_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_periphclks.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_PERIPHCLKS_H
#define __ARCH_ARM_SRC_SAMA5_SAM_PERIPHCLKS_H
/****************************************************************************
* Included Files
****************************************************************************/
/* chip.h holds the characteristics of the configured chip */
#include <nuttx/config.h>
#include <arch/sama5/chip.h>
/* Include the correct logic for the configured chip */
#if defined(ATSAMA5D2)
# include "sama5d2x_periphclks.h"
#elif defined(ATSAMA5D3)
# include "sama5d3x_periphclks.h"
#elif defined(ATSAMA5D4)
# include "sama5d4x_periphclks.h"
#else
# error Unrecognized SAMA5 family
#endif
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_PERIPHCLKS_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_pgalloc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/addrenv.h>
#include <nuttx/pgalloc.h>
#include "chip.h"
#include "mmu.h"
#include "sam_pgalloc.h"
#ifdef CONFIG_MM_PGALLOC
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Currently, page cache memory must be allocated in DRAM. There are other
* possibilities, but the logic in this file will have to extended in order
* handle any other possibility.
*/
#ifndef CONFIG_SAMA5_DDRCS_PGHEAP
# error CONFIG_SAMA5_DDRCS_PGHEAP must be selected
#endif
#ifndef CONFIG_SAMA5_DDRCS_PGHEAP_OFFSET
# error CONFIG_SAMA5_DDRCS_PGHEAP_OFFSET must be specified
#endif
#if (CONFIG_SAMA5_DDRCS_PGHEAP_OFFSET & MM_PGMASK) != 0
# warning CONFIG_SAMA5_DDRCS_PGHEAP_OFFSET is not aligned to a page boundary
#endif
#ifndef CONFIG_SAMA5_DDRCS_PGHEAP_SIZE
# error CONFIG_SAMA5_DDRCS_PGHEAP_SIZE must be specified
#endif
#if (CONFIG_SAMA5_DDRCS_PGHEAP_SIZE & MM_PGMASK) != 0
# warning CONFIG_SAMA5_DDRCS_PGHEAP_SIZE is not aligned to a page boundary
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_allocate_pgheap
*
* Description:
* If there is a page allocator in the configuration, then this function
* must be provided by the platform-specific code. The OS initialization
* logic will call this function early in the initialization sequence to
* get the page heap information needed to configure the page allocator.
*
****************************************************************************/
void up_allocate_pgheap(FAR void **heap_start, size_t *heap_size)
{
DEBUGASSERT(heap_start && heap_size);
*heap_start = (FAR void *)((uintptr_t)SAM_DDRCS_PSECTION +
CONFIG_SAMA5_DDRCS_PGHEAP_OFFSET);
*heap_size = CONFIG_SAMA5_DDRCS_PGHEAP_SIZE;
}
/****************************************************************************
* Name: sam_virtpgaddr
*
* Description:
* Check if the physical address lies in the page pool and, if so
* get the mapping to the virtual address in the user data area.
*
****************************************************************************/
#ifndef CONFIG_ARCH_PGPOOL_MAPPING
uintptr_t sam_virtpgaddr(uintptr_t paddr)
{
uintptr_t poolstart;
uintptr_t poolend;
/* REVISIT: Not implemented correctly. The reverse lookup from physical
* to virtual. This will return a kernel accessible virtual address, but
* not an address usable by the user code.
*
* The correct solutions is complex and, perhaps, will never be needed.
*/
poolstart = ((uintptr_t)SAM_DDRCS_PSECTION +
CONFIG_SAMA5_DDRCS_PGHEAP_OFFSET);
poolend = poolstart + CONFIG_SAMA5_DDRCS_PGHEAP_SIZE;
if (paddr >= poolstart && paddr < poolend)
{
return paddr - SAM_DDRCS_PSECTION + SAM_DDRCS_VSECTION;
}
return 0;
}
#endif /* !CONFIG_ARCH_PGPOOL_MAPPING */
#endif /* CONFIG_MM_PGALLOC */

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/****************************************************************************
* arch/arm/src/sama5/sam_pgalloc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_PGALLOC_H
#define __ARCH_ARM_SRC_SAMA5_SAM_PGALLOC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "pgalloc.h"
#ifdef CONFIG_MM_PGALLOC
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_physpgaddr
*
* Description:
* Check if the virtual address lies in the user data area and, if so
* get the mapping to the physical address in the page pool.
*
****************************************************************************/
#define sam_physpgaddr(vaddr) arm_physpgaddr(vaddr)
/****************************************************************************
* Name: sam_virtpgaddr
*
* Description:
* Check if the physical address lies in the page pool and, if so
* get the mapping to the virtual address in the user data area.
*
****************************************************************************/
#ifdef CONFIG_ARCH_PGPOOL_MAPPING
# define sam_virtpgaddr(vaddr) arm_virtpgaddr(vaddr)
#else
uintptr_t sam_virtpgaddr(uintptr_t paddr);
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* CONFIG_MM_PGALLOC */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_PGALLOC_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_pio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
/* chip.h holds the characteristics of the configured chip */
#include <nuttx/config.h>
#include <arch/sama5/chip.h>
/* Include the correct logic for the configured chip */
#if defined(ATSAMA5D2)
# include "sama5d2x_pio.c"
#elif defined(ATSAMA5D3) || defined(ATSAMA5D4)
# include "sama5d3x4x_pio.c"
#else
# error Unrecognized SAMA5 family
#endif
/****************************************************************************
* Public Functions
****************************************************************************/

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/****************************************************************************
* arch/arm/src/sama5/sam_pio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_PIO_H
#define __ARCH_ARM_SRC_SAMA5_SAM_PIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <arch/sama5/chip.h>
#include "hardware/sam_memorymap.h"
/* Definitions and types customized for each SAMA5Dx family */
#if defined(ATSAMA5D2)
# include "sama5d2x_pio.h"
#elif defined(ATSAMA5D3) || defined(ATSAMA5D4)
# include "sama5d3x4x_pio.h"
#else
# error Unrecognized SAMA5 architecture
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/* Lookup for non-secure PIOs */
extern const uintptr_t g_piobase[SAM_NPIO];
#define sam_pion_vbase(n) (g_piobase[(n)])
#ifdef ATSAMA5D2
/* Lookup for secrure PIOs */
extern const uintptr_t g_spiobase[SAM_NPIO];
# define sam_spion_vbase(n) (g_spiobase[(n)])
#endif
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_pioirqinitialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for PIO
* pins.
*
****************************************************************************/
#ifdef CONFIG_SAMA5_PIO_IRQ
void sam_pioirqinitialize(void);
#else
# define sam_pioirqinitialize()
#endif
/****************************************************************************
* Name: sam_configpio
*
* Description:
* Configure a PIO pin based on bit-encoded description of the pin.
*
****************************************************************************/
int sam_configpio(pio_pinset_t cfgset);
/****************************************************************************
* Name: sam_piowrite
*
* Description:
* Write one or zero to the selected PIO pin
*
****************************************************************************/
void sam_piowrite(pio_pinset_t pinset, bool value);
/****************************************************************************
* Name: sam_pioread
*
* Description:
* Read one or zero from the selected PIO pin
*
****************************************************************************/
bool sam_pioread(pio_pinset_t pinset);
/****************************************************************************
* Name: sam_pioirq
*
* Description:
* Configure an interrupt for the specified PIO pin.
*
****************************************************************************/
#ifdef CONFIG_SAMA5_PIO_IRQ
void sam_pioirq(pio_pinset_t pinset);
#else
# define sam_pioirq(pinset)
#endif
/****************************************************************************
* Name: sam_pioirqenable
*
* Description:
* Enable the interrupt for specified PIO IRQ
*
****************************************************************************/
#ifdef CONFIG_SAMA5_PIO_IRQ
void sam_pioirqenable(int irq);
#else
# define sam_pioirqenable(irq)
#endif
/****************************************************************************
* Name: sam_pioirqdisable
*
* Description:
* Disable the interrupt for specified PIO IRQ
*
****************************************************************************/
#ifdef CONFIG_SAMA5_PIO_IRQ
void sam_pioirqdisable(int irq);
#else
# define sam_pioirqdisable(irq)
#endif
/****************************************************************************
* Name: sam_pio_forceclk
*
* Description:
* Enable PIO clocking.
* This logic is overly conservative and does not enable PIO clocking unless
* necessary (PIO input selected, glitch/filtering enable, or PIO interrupts
* enabled). There are, however, certain conditions were we may want for
* force the PIO clock to be enabled. An example is reading the input value
* from an open drain output.
*
* The PIO automatic enable/disable logic is not smart enough enough to know
* about these cases.
* For those cases, sam_pio_forceclk() is provided.
*
****************************************************************************/
void sam_pio_forceclk(pio_pinset_t pinset, bool enable);
/****************************************************************************
* Function: sam_dumppio
*
* Description:
* Dump all PIO registers associated with the base address of the provided
* pinset.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_GPIO_INFO
int sam_dumppio(uint32_t pinset, const char *msg);
#else
# define sam_dumppio(p,m)
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_PIO_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_pioirq.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/init.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/board/board.h>
#include "arm_arch.h"
#include "arm_internal.h"
#include "hardware/sam_pio.h"
#include "hardware/sam_pmc.h"
#include "sam_pio.h"
#include "sam_periphclks.h"
#ifdef CONFIG_SAMA5_PIO_IRQ
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: sam_piobase
*
* Description:
* Return the base address of the PIO register set
*
****************************************************************************/
static inline uint32_t sam_piobase(pio_pinset_t pinset)
{
int port = (pinset & PIO_PORT_MASK) >> PIO_PORT_SHIFT;
return sam_pion_vbase(port >> PIO_PORT_SHIFT);
}
/****************************************************************************
* Name: sam_piopin
*
* Description:
* Return the base address of the PIO register set
*
****************************************************************************/
static inline int sam_piopin(pio_pinset_t pinset)
{
return 1 << ((pinset & PIO_PIN_MASK) >> PIO_PIN_SHIFT);
}
/****************************************************************************
* Name: sam_irqbase
*
* Description:
* Return PIO information associated with this IRQ
*
****************************************************************************/
static int sam_irqbase(int irq, uint32_t *base, int *pin)
{
if (irq >= SAM_IRQ_NINT)
{
#ifdef CONFIG_SAMA5_PIOA_IRQ
if (irq <= SAM_IRQ_PA31)
{
*base = SAM_PIOA_VBASE;
*pin = irq - SAM_IRQ_PA0;
return OK;
}
#endif
#ifdef CONFIG_SAMA5_PIOB_IRQ
if (irq <= SAM_IRQ_PB31)
{
*base = SAM_PIOB_VBASE;
*pin = irq - SAM_IRQ_PB0;
return OK;
}
#endif
#ifdef CONFIG_SAMA5_PIOC_IRQ
if (irq <= SAM_IRQ_PC31)
{
*base = SAM_PIOC_VBASE;
*pin = irq - SAM_IRQ_PC0;
return OK;
}
#endif
#ifdef CONFIG_SAMA5_PIOD_IRQ
if (irq <= SAM_IRQ_PD31)
{
*base = SAM_PIOD_VBASE;
*pin = irq - SAM_IRQ_PD0;
return OK;
}
#endif
#ifdef CONFIG_SAMA5_PIOE_IRQ
if (irq <= SAM_IRQ_PE31)
{
*base = SAM_PIOE_VBASE;
*pin = irq - SAM_IRQ_PE0;
return OK;
}
#endif
#ifdef CONFIG_SAMA5_PIOF_IRQ
if (irq <= SAM_IRQ_PF31)
{
*base = SAM_PIOF_VBASE;
*pin = irq - SAM_IRQ_PF0;
return OK;
}
#endif
}
return -EINVAL;
}
/****************************************************************************
* Name: sam_pioa/b/c/d/e/finterrupt
*
* Description:
* Receive PIOA/B/C/D/E/F interrupts
*
****************************************************************************/
static int sam_piointerrupt(uint32_t base, int irq0, void *context)
{
uint32_t pending;
uint32_t bit;
int irq;
pending = getreg32(base + SAM_PIO_ISR_OFFSET) & getreg32(base +
SAM_PIO_IMR_OFFSET);
for (bit = 1, irq = irq0; pending != 0; bit <<= 1, irq++)
{
if ((pending & bit) != 0)
{
/* Re-deliver the IRQ (recurses! We got here from irq_dispatch!) */
irq_dispatch(irq, context);
/* Remove this from the set of pending interrupts */
pending &= ~bit;
}
}
return OK;
}
#ifdef CONFIG_SAMA5_PIOA_IRQ
static int sam_pioainterrupt(int irq, void *context, FAR void *arg)
{
return sam_piointerrupt(SAM_PIOA_VBASE, SAM_IRQ_PA0, context);
}
#endif
#ifdef CONFIG_SAMA5_PIOB_IRQ
static int sam_piobinterrupt(int irq, void *context, FAR void *arg)
{
return sam_piointerrupt(SAM_PIOB_VBASE, SAM_IRQ_PB0, context);
}
#endif
#ifdef CONFIG_SAMA5_PIOC_IRQ
static int sam_piocinterrupt(int irq, void *context, FAR void *arg)
{
return sam_piointerrupt(SAM_PIOC_VBASE, SAM_IRQ_PC0, context);
}
#endif
#ifdef CONFIG_SAMA5_PIOD_IRQ
static int sam_piodinterrupt(int irq, void *context, FAR void *arg)
{
return sam_piointerrupt(SAM_PIOD_VBASE, SAM_IRQ_PD0, context);
}
#endif
#ifdef CONFIG_SAMA5_PIOE_IRQ
static int sam_pioeinterrupt(int irq, void *context, FAR void *arg)
{
return sam_piointerrupt(SAM_PIOE_VBASE, SAM_IRQ_PE0, context);
}
#endif
#ifdef CONFIG_SAMA5_PIOF_IRQ
static int sam_piofinterrupt(int irq, void *context, FAR void *arg)
{
return sam_piointerrupt(SAM_PIOF_VBASE, SAM_IRQ_PF0, context);
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: sam_pioirqinitialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for
* PIO pins.
*
****************************************************************************/
void sam_pioirqinitialize(void)
{
/* Configure PIOA interrupts */
#ifdef CONFIG_SAMA5_PIOA_IRQ
/* Enable PIOA clocking */
sam_pioa_enableclk();
/* Clear and disable all PIOA interrupts */
getreg32(SAM_PIOA_ISR);
putreg32(0xffffffff, SAM_PIOA_IDR);
/* Attach and enable the PIOA IRQ */
irq_attach(SAM_IRQ_PIOA, sam_pioainterrupt, NULL);
up_enable_irq(SAM_IRQ_PIOA);
#endif
/* Configure PIOB interrupts */
#ifdef CONFIG_SAMA5_PIOB_IRQ
/* Enable PIOB clocking */
sam_piob_enableclk();
/* Clear and disable all PIOB interrupts */
getreg32(SAM_PIOB_ISR);
putreg32(0xffffffff, SAM_PIOB_IDR);
/* Attach and enable the PIOB IRQ */
irq_attach(SAM_IRQ_PIOB, sam_piobinterrupt, NULL);
up_enable_irq(SAM_IRQ_PIOB);
#endif
/* Configure PIOC interrupts */
#ifdef CONFIG_SAMA5_PIOC_IRQ
/* Enable PIOC clocking */
sam_pioc_enableclk();
/* Clear and disable all PIOC interrupts */
getreg32(SAM_PIOC_ISR);
putreg32(0xffffffff, SAM_PIOC_IDR);
/* Attach and enable the PIOC IRQ */
irq_attach(SAM_IRQ_PIOC, sam_piocinterrupt, NULL);
up_enable_irq(SAM_IRQ_PIOC);
#endif
/* Configure PIOD interrupts */
#ifdef CONFIG_SAMA5_PIOD_IRQ
/* Enable PIOD clocking */
sam_piod_enableclk();
/* Clear and disable all PIOD interrupts */
getreg32(SAM_PIOD_ISR);
putreg32(0xffffffff, SAM_PIOD_IDR);
/* Attach and enable the PIOC IRQ */
irq_attach(SAM_IRQ_PIOD, sam_piodinterrupt, NULL);
up_enable_irq(SAM_IRQ_PIOD);
#endif
/* Configure PIOE interrupts */
#ifdef CONFIG_SAMA5_PIOE_IRQ
/* Enable PIOE clocking */
sam_pioe_enableclk();
/* Clear and disable all PIOE interrupts */
getreg32(SAM_PIOE_ISR);
putreg32(0xffffffff, SAM_PIOE_IDR);
/* Attach and enable the PIOE IRQ */
irq_attach(SAM_IRQ_PIOE, sam_pioeinterrupt, NULL);
up_enable_irq(SAM_IRQ_PIOE);
#endif
/* Configure PIOF interrupts */
#ifdef CONFIG_SAMA5_PIOF_IRQ
/* Enable PIOF clocking */
sam_piof_enableclk();
/* Clear and disable all PIOF interrupts */
getreg32(SAM_PIOF_ISR);
putreg32(0xffffffff, SAM_PIOF_IDR);
/* Attach and enable the PIOF IRQ */
irq_attach(SAM_IRQ_PIOF, sam_piofinterrupt, NULL);
up_enable_irq(SAM_IRQ_PIOF);
#endif
}
/****************************************************************************
* Name: sam_pioirq
*
* Description:
* Configure an interrupt for the specified PIO pin.
*
****************************************************************************/
void sam_pioirq(pio_pinset_t pinset)
{
#if defined(SAM_PIO_ISLR_OFFSET)
uint32_t regval;
#endif
#if defined(SAM_PIO_ISLR_OFFSET) || defined(_PIO_INT_AIM)
uint32_t base = sam_piobase(pinset);
int pin = sam_piopin(pinset);
#endif
#if defined(SAM_PIO_ISLR_OFFSET)
/* Enable writing to PIO registers. The following registers are protected:
*
* - PIO Enable/Disable Registers (PER/PDR)
* - PIO Output Enable/Disable Registers (OER/ODR)
* - PIO Interrupt Security Level Register (ISLR)
* - PIO Input Filter Enable/Disable Registers (IFER/IFDR)
* - PIO Multi-driver Enable/Disable Registers (MDER/MDDR)
* - PIO Pull-Up Enable/Disable Registers (PUER/PUDR)
* - PIO Peripheral ABCD Select Register 1/2 (ABCDSR1/2)
* - PIO Output Write Enable/Disable Registers
* - PIO Pad Pull-Down Enable/Disable Registers (PPER/PPDR)
*
* I suspect that the default state is the WPMR is unprotected, so these
* operations could probably all be avoided.
*/
putreg32(PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET);
/* Is the interrupt secure? */
regval = getreg32(base + SAM_PIO_ISLR_OFFSET);
if ((pinset & PIO_INT_SECURE) != 0)
{
/* Yes.. make sure that the corresponding bit in ISLR is cleared */
regval &= ~pin;
}
else
{
/* Yes.. make sure that the corresponding bit in ISLR is set */
regval |= pin;
}
putreg32(regval, base + SAM_PIO_ISLR_OFFSET);
#endif
/* Are any additional interrupt modes selected? */
#ifdef _PIO_INT_AIM
if ((pinset & _PIO_INT_AIM) != 0)
{
/* Yes.. Enable additional interrupt mode */
putreg32(pin, base + SAM_PIO_AIMER_OFFSET);
/* Level or edge detected interrupt? */
if ((pinset & _PIO_INT_LEVEL) != 0)
{
putreg32(pin, base + SAM_PIO_LSR_OFFSET); /* Level */
}
else
{
putreg32(pin, base + SAM_PIO_ESR_OFFSET); /* Edge */
}
/* High level/rising edge or low level /falling edge? */
if ((pinset & _PIO_INT_RH) != 0)
{
/* High level/Rising edge */
putreg32(pin, base + SAM_PIO_REHLSR_OFFSET);
}
else
{
/* Low level/Falling edge */
putreg32(pin, base + SAM_PIO_FELLSR_OFFSET);
}
}
else
{
/* No.. Disable additional interrupt mode */
putreg32(pin, base + SAM_PIO_AIMDR_OFFSET);
}
#endif
#if defined(SAM_PIO_ISLR_OFFSET)
/* Disable writing to PIO registers */
putreg32(PIO_WPMR_WPEN | PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET);
#endif
}
/****************************************************************************
* Name: sam_pioirqenable
*
* Description:
* Enable the interrupt for specified PIO IRQ
*
****************************************************************************/
void sam_pioirqenable(int irq)
{
uint32_t base;
int pin;
if (sam_irqbase(irq, &base, &pin) == OK)
{
/* Clear (all) pending interrupts and enable this pin interrupt */
(void)getreg32(base + SAM_PIO_ISR_OFFSET);
putreg32((1 << pin), base + SAM_PIO_IER_OFFSET);
}
}
/****************************************************************************
* Name: sam_pioirqdisable
*
* Description:
* Disable the interrupt for specified PIO IRQ
*
****************************************************************************/
void sam_pioirqdisable(int irq)
{
uint32_t base;
int pin;
if (sam_irqbase(irq, &base, &pin) == OK)
{
/* Disable this pin interrupt */
putreg32((1 << pin), base + SAM_PIO_IDR_OFFSET);
}
}
#endif /* CONFIG_SAMA5_PIO_IRQ */

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/****************************************************************************
* arch/arm/src/sama5/sam_pmc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* SAMA5D3 Series Data Sheet
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/board/board.h>
#include "arm_arch.h"
#include "chip.h"
#ifdef CONFIG_ARCH_HAVE_SDIO
# include "hardware/sam_hsmci.h"
#endif
#include "hardware/sam_pmc.h"
#include "sam_pmc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: sam_pllack_frequency
*
* Description:
* Given the Main Clock frequency that provides the input to PLLA, return
* the frequency of the PPA output clock, PLLACK
*
* Assumptions:
* PLLA is enabled. If the PLL is is disabled, either at the input divider
* or the output multiplier, the value zero is returned.
*
****************************************************************************/
uint32_t sam_pllack_frequency(uint32_t mainclk)
{
uint32_t regval;
#ifdef SAMA5_HAVE_PLLAR_DIV
uint32_t diva;
#endif
uint32_t mula;
uint32_t pllack;
/* Get the PLLA configuration. We will multiply (and possibly divide)
* the Main Clock to get the PLLA output clock (PLLACK).
*/
regval = getreg32(SAM_PMC_CKGR_PLLAR);
pllack = mainclk;
#ifdef SAMA5_HAVE_PLLAR_DIV
/* Get the PLLA divider (DIVA)
*
* DIVA = 0: Divider output is 0
* DIVA = 1: Divider is bypassed
* DIVA = 2-255: Divider output is the selected clock divided by DIVA
*/
diva = (regval & PMC_CKGR_PLLAR_DIV_MASK) >> PMC_CKGR_PLLAR_DIV_SHIFT;
if (diva > 1)
{
pllack /= diva;
}
else if (diva < 1)
{
return 0;
}
#endif
/* Get the PLLA multiplier (MULA)
*
* MULA = 0: PLLA is deactivated
* MULA > 0: The PLLA Clock frequency is the PLLA input frequency
* multiplied by MULA + 1.
*/
mula = (regval & PMC_CKGR_PLLAR_MUL_MASK) >> PMC_CKGR_PLLAR_MUL_SHIFT;
if (mula > 0)
{
pllack *= (mula + 1);
}
else
{
return 0;
}
return pllack;
}
/****************************************************************************
* Name: sam_plladiv2_frequency
*
* Description:
* The PLLACK input to most clocking may or may not be divided by two.
* This function will return the possibly divided PLLACK clock input
* frequency.
*
* Assumptions:
* See sam_pllack_frequency.
*
****************************************************************************/
uint32_t sam_plladiv2_frequency(uint32_t mainclk)
{
uint32_t regval;
uint32_t pllack;
/* Get the PLLA output clock */
pllack = sam_pllack_frequency(mainclk);
if (pllack == 0)
{
return 0;
}
/* Check if the PLLACK output is divided by 2 */
regval = getreg32(SAM_PMC_MCKR);
if ((regval & PMC_MCKR_PLLADIV2) != 0)
{
pllack >>= 1;
}
return pllack;
}
/****************************************************************************
* Name: sam_pck_frequency
*
* Description:
* Given the Main Clock frequency that provides the input to PLLA, return
* the frequency of the processor clock (PCK).
*
* Assumptions:
* PLLA is enabled and the either the main clock or the PLLA output clock
* (PLLACK) provides the input to the MCK prescaler.
*
****************************************************************************/
uint32_t sam_pck_frequency(uint32_t mainclk)
{
uint32_t regval;
uint32_t pres;
uint32_t pck;
/* Get the input source selection to the master/processor clock divider */
regval = getreg32(SAM_PMC_MCKR);
switch (regval & PMC_MCKR_CSS_MASK)
{
case PMC_MCKR_CSS_MAIN: /* Main Clock */
/* Use the Main Clock frequency */
pck = mainclk;
break;
case PMC_MCKR_CSS_PLLA: /* PLLA Clock */
/* Use the PLLA output clock */
pck = sam_plladiv2_frequency(mainclk);
if (pck == 0)
{
return 0;
}
break;
case PMC_MCKR_CSS_SLOW: /* Slow Clock */
case PMC_MCKR_CSS_UPLL: /* UPLL Clock */
default:
return 0;
}
/* Get the PCK frequency which is given by the selected input clock
* divided by a power-of-two prescaler.
*
* PRES = 0: Selected clock
* PRES = n > 0: Selected clock divided by 2**n
*/
pres = (regval & PMC_MCKR_PRES_MASK) >> PMC_MCKR_PRES_SHIFT;
return pck >> pres;
}
/****************************************************************************
* Name: sam_mck_frequency
*
* Description:
* Given the Main Clock frequency that provides the input to PLLA, return
* the frequency of the PPA output clock, PLLACK
*
* Assumptions:
* PLLA is enabled and the either the main clock or the PLLA output clock
* (PLLACK) provides the input to the MCK prescaler.
*
****************************************************************************/
uint32_t sam_mck_frequency(uint32_t mainclk)
{
uint32_t regval;
uint32_t mdiv;
uint32_t mck;
/* The MCK frequency is equivalent to the PCK clock frequency with an
* additional divider.
*/
mck = sam_pck_frequency(mainclk);
if (mck == 0)
{
return 0;
}
/* MDIV = n:
* Master Clock is Prescaler Output Clock divided by encoded value
*/
regval = getreg32(SAM_PMC_MCKR);
switch (regval & PMC_MCKR_MDIV_MASK)
{
case PMC_MCKR_MDIV_PCKDIV1:
return mck;
case PMC_MCKR_MDIV_PCKDIV2:
mdiv = 2;
break;
case PMC_MCKR_MDIV_PCKDIV3:
mdiv = 3;
break;
case PMC_MCKR_MDIV_PCKDIV4:
mdiv = 4;
break;
default:
return 0;
}
return mck / mdiv;
}

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/****************************************************************************
* arch/arm/src/sama5/sam_pmc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_PMC_H
#define __ARCH_ARM_SRC_SAMA5_SAM_PMC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_pllack_frequency
*
* Description:
* Given the Main Clock frequency that provides the input to PLLA, return
* the frequency of the PPA output clock, PLLACK
*
* Assumptions:
* PLLA is enabled. If the PLL is is disabled, either at the input divider
* or the output multiplier, the value zero is returned.
*
****************************************************************************/
uint32_t sam_pllack_frequency(uint32_t mainclk);
/****************************************************************************
* Name: sam_plladiv2_frequency
*
* Description:
* The PLLACK input to most clocking may or may not be divided by two.
* This function will return the possibly divided PLLACK clock input
* frequency.
*
* Assumptions:
* See sam_pllack_frequency.
*
****************************************************************************/
uint32_t sam_plladiv2_frequency(uint32_t mainclk);
/****************************************************************************
* Name: sam_pck_frequency
*
* Description:
* Given the Main Clock frequency that provides the input to PLLA, return
* the frequency of the processor clock (PCK).
*
* Assumptions:
* PLLA is enabled and the either the main clock or the PLLA output clock
* (PLLACK) provides the input to the MCK prescaler.
*
****************************************************************************/
uint32_t sam_pck_frequency(uint32_t mainclk);
/****************************************************************************
* Name: sam_mck_frequency
*
* Description:
* Given the Main Clock frequency that provides the input to PLLA, return
* the frequency of the PPA output clock, PLLACK
*
* Assumptions:
* PLLA is enabled and the either the main clock or the PLLA output clock
* (PLLACK) provides the input to the MCK prescaler.
*
****************************************************************************/
uint32_t sam_mck_frequency(uint32_t mainclk);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_PMC_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_pmecc.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* This logic was based largely on Atmel sample code with modifications for
* better integration with NuttX. The Atmel sample code has a BSD
* compatible license that requires this copyright notice:
*
* Copyright (c) 2010, Atmel Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the names NuttX nor Atmel nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_PMECC_H
#define __ARCH_ARM_SRC_SAMA5_PMECC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/mtd/nand_config.h>
#include <stdint.h>
#include <stdbool.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* Block checking and H/W ECC support must be enabled for PMECC */
#ifndef CONFIG_MTD_NAND_HWECC
# undef CONFIG_SAMA5_EBICS0_PMECC
# undef CONFIG_SAMA5_EBICS1_PMECC
# undef CONFIG_SAMA5_EBICS2_PMECC
# undef CONFIG_SAMA5_EBICS3_PMECC
#endif
/* Only CS3 can support NAND. The rest of what follows is a fantasy */
# undef CONFIG_SAMA5_EBICS0_NAND
# undef CONFIG_SAMA5_EBICS1_NAND
# undef CONFIG_SAMA5_EBICS2_NAND
# undef CONFIG_SAMA5_EBICS0_PMECC
# undef CONFIG_SAMA5_EBICS1_PMECC
# undef CONFIG_SAMA5_EBICS2_PMECC
/* Disable PMECC support for any banks not enabled or configured for NAND */
#if !defined(CONFIG_SAMA5_EBICS0) || !defined(CONFIG_SAMA5_EBICS0_NAND)
# undef CONFIG_SAMA5_EBICS0_PMECC
#endif
#if !defined(CONFIG_SAMA5_EBICS1) || !defined(CONFIG_SAMA5_EBICS1_NAND)
# undef CONFIG_SAMA5_EBICS1_PMECC
#endif
#if !defined(CONFIG_SAMA5_EBICS2) || !defined(CONFIG_SAMA5_EBICS2_NAND)
# undef CONFIG_SAMA5_EBICS2_PMECC
#endif
#if !defined(CONFIG_SAMA5_EBICS3) || !defined(CONFIG_SAMA5_EBICS3_NAND)
# undef CONFIG_SAMA5_EBICS3_PMECC
#endif
/* Count the number of banks that configured for NAND with PMECC support
* enabled.
*/
#undef CONFIG_SAMA5_HAVE_PMECC
#ifdef CONFIG_SAMA5_EBICS0_PMECC
# define CONFIG_SAMA5_HAVE_PMECC 1
# define NAND_HAVE_EBICS0_PMECC 1
#else
# define NAND_HAVE_EBICS0_PMECC 0
#endif
#ifdef CONFIG_SAMA5_EBICS1_PMECC
# define CONFIG_SAMA5_HAVE_PMECC 1
# define NAND_HAVE_EBICS1_PMECC 1
#else
# define NAND_HAVE_EBICS1_PMECC 0
#endif
#ifdef CONFIG_SAMA5_EBICS2_PMECC
# define CONFIG_SAMA5_HAVE_PMECC 1
# define NAND_HAVE_EBICS2_PMECC 1
#else
# define NAND_HAVE_EBICS2_PMECC 0
#endif
#ifdef CONFIG_SAMA5_EBICS3_PMECC
# define CONFIG_SAMA5_HAVE_PMECC 1
# define NAND_HAVE_EBICS3_PMECC 1
#else
# define NAND_HAVE_EBICS3_PMECC 0
#endif
/* Count the number of banks using PMECC */
#define NAND_NPMECC_BANKS \
(NAND_HAVE_EBICS0_PMECC + NAND_HAVE_EBICS1_PMECC + \
NAND_HAVE_EBICS2_PMECC + NAND_HAVE_EBICS3_PMECC)
/* Compile this logic only if there is at least one CS configure for NAND
* and with PMECC support enabled.
*/
#ifdef CONFIG_SAMA5_HAVE_PMECC
/* Maximum PMECC size */
#ifndef CONFIG_MTD_NAND_MAX_PMECCSIZE
# define CONFIG_MTD_NAND_MAX_PMECCSIZE 200
#endif
/* The ROM code embeds the software used in the process of ECC
* detection/correction
*/
#ifdef CONFIG_SAMA5_PMECC_EMBEDDEDALGO_ADDR
# ifndef CONFIG_SAMA5_PMECC_EMBEDDEDALGO_ADDR
# define CONFIG_SAMA5_PMECC_EMBEDDEDALGO_ADDR 0x00104510
# endif
#endif
#ifdef CONFIG_SAMA5_PMECC_GALOIS_ROMTABLES
# ifndef CONFIG_SAMA5_PMECC_GALOIS_TABLE512_ROMADDR
# define CONFIG_SAMA5_PMECC_GALOIS_TABLE512_ROMADDR 0x00110000
# endif
# ifndef CONFIG_SAMA5_PMECC_GALOIS_TABLE1024_ROMADDR
# define CONFIG_SAMA5_PMECC_GALOIS_TABLE1024_ROMADDR 0x00118000
# endif
#endif
/* Gallois Field Tables *****************************************************/
/* Indexes of tables in Gallois Field tables */
#define PMECC_GF_INDEX_OF 0
#define PMECC_GF_ALPHA_TO 1
/* Gallois Field tables for 512 and 1024 bytes sectors
* First raw is "index_of" and second one is "alpha_to"
*/
#define PMECC_GF_SIZEOF_512 0x2000
#define PMECC_GF_SIZEOF_1024 0x4000
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* Gallois Field tables for 512 bytes sectors. First raw is "index_of" and
* second one is "alpha_to"
*/
#ifdef CONFIG_SAMA5_PMECC_GALOIS_TABLE512_ROMADDR
# ifndef CONFIG_SAMA5_PMECC_GALOIS_TABLE512_ROMADDR
# error CONFIG_SAMA5_PMECC_GALOIS_TABLE512_ROMADDR is not defined
# endif
# define pmecc_gf512 ((const int16_t *)CONFIG_SAMA5_PMECC_GALOIS_TABLE512_ROMADDR)
# ifndef CONFIG_SAMA5_PMECC_GALOIS_TABLE1024_ROMADDR
# error CONFIG_SAMA5_PMECC_GALOIS_TABLE1024_ROMADDR is not defined
# endif
# define pmecc_gf1024 ((const int16_t *)CONFIG_SAMA5_PMECC_GALOIS_TABLE1024_ROMADDR)
#else
EXTERN const uint16_t pmecc_gf512[2][PMECC_GF_SIZEOF_512];
EXTERN const uint16_t pmecc_gf1024[2][PMECC_GF_SIZEOF_1024];
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: pmecc_lock
*
* Description:
* Get exclusive access to PMECC hardware
*
* Input Parameters:
* None
*
* Returned Value:
* Normally success (OK) is returned, but the error -ECANCELED may be
* return in the event that task has been canceled.
*
****************************************************************************/
#if NAND_NPMECC_BANKS > 1
int pmecc_lock(void);
#else
# define pmecc_lock() (0)
#endif
/****************************************************************************
* Name: pmecc_unlock
*
* Description:
* Relinquish exclusive access to PMECC hardware
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#if NAND_NPMECC_BANKS > 1
void pmecc_unlock(void);
#else
# define pmecc_unlock()
#endif
/****************************************************************************
* Name: pmecc_enable
*
* Description:
* Enable PMECC
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void pmecc_enable(void);
/****************************************************************************
* Name: pmecc_disable
*
* Description:
* Enable PMECC
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void pmecc_disable(void);
/****************************************************************************
* Name: pmecc_initialize
*
* Description:
* Perform one-time PMECC initialization. This must be called before any
* other PMECC interfaces are used.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#if NAND_NPMECC_BANKS > 1
void pmecc_initialize(void);
#else
# define pmecc_initialize()
#endif
/****************************************************************************
* Name: pmecc_configure
*
* Description:
* Configure and Initialize the PMECC peripheral for this CS.
*
* Input Parameters:
* priv - Pointer to a struct sam_nandcs_s instance.
* protected - True: The spare area is protected with the last sector of
* data.
* False: The spare area is skipped in read or write mode.
*
* Returned Value:
* OK on success; a negated errno value on failure.
*
****************************************************************************/
struct sam_nandcs_s;
int pmecc_configure(struct sam_nandcs_s *priv, bool protected);
/****************************************************************************
* Name: pmecc_correction
*
* Description:
* Perform the PMECC correction algorithm
*
* Input Parameters:
* isr - Value of the PMECC ISR register
* data - Data to be corrected
*
* Returned Value:
* OK on success; a negated errno value on failure
*
* Assumptions:
* PMECC has been initialized for the CS and the caller holds the PMECC
* lock.
*
****************************************************************************/
int pmecc_correction(uint32_t isr, uintptr_t data);
/****************************************************************************
* Name: pmecc_get*
*
* Description:
* Various PMECC accessor functions
*
* pmecc_get_eccsize() - Returns the raw ECS size in bytes
* pmecc_get_pagesize() - Returns encoded HSMC_PMECCFG_PAGESIZE_* value
*
* Input Parameters:
* None
*
* Returned Value:
* The requested value
*
* Assumptions:
* PMECC has been initialized for the CS and the caller holds the PMECC
* lock.
*
****************************************************************************/
uint32_t pmecc_get_eccsize(void);
uint32_t pmecc_get_pagesize(void);
/****************************************************************************
* Name: pmecc_buildgf
*
* Description:
* This function is able to build Galois Field.
*
* Input Parameters:
* mm - Degree of the remainders.
* indexof - Pointer to a buffer for indexof table.
* alphato - Pointer to a buffer for alphato table.
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_SAMA5_PMECC_GALOIS_CUSTOM
void pmecc_buildgf(uint32_t mm, int16_t *indexof, int16_t *alphato);
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#else /* CONFIG_SAMA5_HAVE_PMECC */
/****************************************************************************/
/* Stub definitions to minimize conditional compilation when PMECC is
* disabled
*/
# define pmecc_lock()
# define pmecc_unlock()
# define pmecc_enable()
# define pmecc_disable()
# define pmecc_initialize()
# define pmecc_configure(a,b) (0)
# define pmecc_get_eccsize() (0)
# define pmecc_get_pagesize() (0)
#endif /* CONFIG_SAMA5_HAVE_PMECC */
#endif /* __ARCH_ARM_SRC_SAMA5_PMECC_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_pwm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_PWM_H
#define __ARCH_ARM_SRC_SAMA5_SAM_PWM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_pwm.h"
#ifdef CONFIG_SAMA5_PWM
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* Do we have any PWM channels enabled?
* If not, then why is the PWM enabled?
*/
#if !defined(CONFIG_SAMA5_PWM_CHAN0) && !defined(CONFIG_SAMA5_PWM_CHAN1) && \
!defined(CONFIG_SAMA5_PWM_CHAN2) && !defined(CONFIG_SAMA5_PWM_CHAN3)
# error "No PWM channels configured"
# undef CONFIG_SAMA5_PWM
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_pwminitialize
*
* Description:
* Initialize one timer for use with the upper_level PWM driver.
*
* Input Parameters:
* channel - A number identifying the PWM channel use.
*
* Returned Value:
* On success, a pointer to the SAMA5 lower half PWM driver is returned.
* NULL is returned on any failure.
*
****************************************************************************/
FAR struct pwm_lowerhalf_s *sam_pwminitialize(int channel);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_SAMA5_PWM */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_PWM_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_rtc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <time.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <nuttx/wqueue.h>
#include <arch/board/board.h>
#include "arm_arch.h"
#include "sam_rtc.h"
#ifdef CONFIG_RTC
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* This RTC implementation supports only date/time RTC hardware */
#ifndef CONFIG_RTC_DATETIME
# error "CONFIG_RTC_DATETIME must be set to use this driver"
#endif
#ifdef CONFIG_RTC_HIRES
# error "CONFIG_RTC_HIRES must NOT be set with this driver"
#endif
#if defined(CONFIG_RTC_ALARM) && !defined(CONFIG_SCHED_WORKQUEUE)
# error CONFIG_RTC_ALARM requires CONFIG_SCHED_WORKQUEUE
#endif
#define RTC_MAGIC 0xdeadbeef
/****************************************************************************
* Private Data
****************************************************************************/
/* Callback to use when the alarm expires */
#ifdef CONFIG_RTC_ALARM
static alarmcb_t g_alarmcb;
struct work_s g_alarmwork;
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* g_rtc_enabled is set true after the RTC has successfully initialized */
volatile bool g_rtc_enabled = false;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: rtc_dumpregs
*
* Description:
* Disable RTC write protection
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_DEBUG_RTC_INFO
static void rtc_dumpregs(FAR const char *msg)
{
rtcinfo("%s:\n", msg);
rtcinfo(" CR: %08x\n", getreg32(SAM_RTC_CR));
rtcinfo(" MR: %08x\n", getreg32(SAM_RTC_MR));
rtcinfo(" TIMR: %08x\n", getreg32(SAM_RTC_TIMR));
rtcinfo(" CALR: %08x\n", getreg32(SAM_RTC_CALR));
rtcinfo(" TIMALR: %08x\n", getreg32(SAM_RTC_TIMALR));
rtcinfo(" CALALR: %08x\n", getreg32(SAM_RTC_CALALR));
rtcinfo(" SR: %08x\n", getreg32(SAM_RTC_SR));
rtcinfo(" IMR: %08x\n", getreg32(SAM_RTC_IMR));
rtcinfo(" VER: %08x\n", getreg32(SAM_RTC_VER));
}
#else
# define rtc_dumpregs(msg)
#endif
/****************************************************************************
* Name: rtc_dumptime
*
* Description:
* Disable RTC write protection
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_DEBUG_RTC_INFO
static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg)
{
rtcinfo("%s:\n", msg);
rtcinfo(" tm_sec: %08x\n", tp->tm_sec);
rtcinfo(" tm_min: %08x\n", tp->tm_min);
rtcinfo(" tm_hour: %08x\n", tp->tm_hour);
rtcinfo(" tm_mday: %08x\n", tp->tm_mday);
rtcinfo(" tm_mon: %08x\n", tp->tm_mon);
rtcinfo(" tm_year: %08x\n", tp->tm_year);
}
#else
# define rtc_dumptime(tp, msg)
#endif
/****************************************************************************
* Name: rtc_bin2bcd
*
* Description:
* Converts a 2 digit binary to BCD format
*
* Input Parameters:
* value - The byte to be converted.
*
* Returned Value:
* The value in BCD representation
*
****************************************************************************/
static uint32_t rtc_bin2bcd(int value)
{
uint32_t msbcd = 0;
while (value >= 10)
{
msbcd++;
value -= 10;
}
return (msbcd << 4) | value;
}
/****************************************************************************
* Name: rtc_bin2bcd
*
* Description:
* Convert from 2 digit BCD to binary.
*
* Input Parameters:
* value - The BCD value to be converted.
*
* Returned Value:
* The value in binary representation
*
****************************************************************************/
static int rtc_bcd2bin(uint32_t value)
{
uint32_t tens = (value >> 4) * 10;
return (int)(tens + (value & 0x0f));
}
/****************************************************************************
* Name: rtc_worker
*
* Description:
* Perform alarm callback
*
* Input Parameters:
* Standard work callbacks
*
* Returned Value:
* Zero (OK) on success; A negated errno value on failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static void rtc_worker(FAR void *arg)
{
/* Sample once (atomically) */
alarmcb_t alarmcb = g_alarmcb;
/* Is there a subscriber to the alarm? */
if (alarmcb)
{
/* Yes.. perform the callback */
alarmcb();
}
}
#endif
/****************************************************************************
* Name: rtc_interrupt
*
* Description:
* RTC interrupt service routine
*
* Input Parameters:
* irq - The IRQ number that generated the interrupt
* context - Architecture specific register save information.
*
* Returned Value:
* Zero (OK) on success; A negated errno value on failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static int rtc_interrupt(int irq, void *context, FAR void *arg)
{
int ret;
/* Schedule the callback to occur on the low-priority worker thread */
DEBUGASSERT(work_available(&g_alarmwork));
ret = work_queue(LPWORK, &g_alarmwork, rtc_worker, NULL, 0);
if (ret < 0)
{
rtcerr("ERROR: work_queue failed: %d\n", ret);
}
/* Disable any further alarm interrupts */
putreg32(RTC_IDR_ALRDIS, SAM_RTC_IDR);
/* Clear any pending alarm interrupts */
putreg32(RTC_SCCR_ALRCLR, SAM_RTC_SCCR);
return OK;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_rtc_initialize
*
* Description:
* Initialize the hardware RTC per the selected configuration. This
* function is called once during the OS initialization sequence
*
* Input Parameters:
* None
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int up_rtc_initialize(void)
{
uint32_t ver;
rtc_dumpregs("On reset");
/* No clocking setup need be performed.
* The Real-time Clock is continuously clocked at 32768 Hz (SCLK).
* The Power Management Controller has no effect on RTC behavior.
*/
/* Set the 24 hour format */
putreg32(0, SAM_RTC_MR);
/* Has the RTC been initialized? */
ver = getreg32(SAM_RTC_VER);
g_rtc_enabled = ((ver & (RTC_VER_NVTIM | RTC_VER_NVCAL)) == 0);
#ifdef CONFIG_RTC_ALARM
/* Then attach the ALARM interrupt handler */
irq_attach(SAM_PID_SYS, rtc_interrupt, NULL);
/* Should RTC alarm interrupt be enabled at the peripheral? Let's
* assume so for now. Let's say yes if the time is valid and a valid
* alarm has been programmed.
*/
if (g_rtc_enabled && (ver & (RTC_VER_NVTIMALR | RTC_VER_NVCALALR)) == 0)
{
/* Enable the alarm interrupt at the RTC */
putreg32(RTC_IER_ALREN, SAM_RTC_IER);
}
else
{
/* Disable the alarm interrupt at the RTC */
putreg32(RTC_IDR_ALRDIS, SAM_RTC_IDR);
}
/* Enable SYSC interrupts at the AIC in any event */
up_enable_irq(SAM_PID_SYS);
#endif
rtc_dumpregs("After Initialization");
return OK;
}
/****************************************************************************
* Name: up_rtc_getdatetime
*
* Description:
* Get the current date and time from the date/time RTC. This interface
* is only supported by the date/time RTC hardware implementation.
* It is used to replace the system timer. It is only used by the RTOS
* during initialization to set up the system time when CONFIG_RTC and
* CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not).
*
* NOTE:
* Some date/time RTC hardware is capability of sub-second accuracy.
* That sub-second accuracy is lost in this interface. However, since
* the system time is reinitialized on each power-up/reset, there will
* be no timing inaccuracy in the long run.
*
* Input Parameters:
* tp - The location to return the high resolution time value.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int up_rtc_getdatetime(FAR struct tm *tp)
{
uint32_t timr;
uint32_t calr;
uint32_t cent;
uint32_t year;
uint32_t tmp;
/* Sample the data time registers.
* There is a race condition here... If we sample the time just before
* midnight on December 31, the date could be wrong because the day rolled
* over while were sampling.
*/
do
{
calr = getreg32(SAM_RTC_CALR);
timr = getreg32(SAM_RTC_TIMR);
tmp = getreg32(SAM_RTC_CALR);
}
while (tmp != calr);
rtc_dumpregs("Reading Time");
/* Convert the RTC time register fields to struct tm format.
*
* struct tm TIMR register
* tm_sec 0-61* SEC (0-59)
* tm_min 0-59 MIN (0-59)
* tm_hour 0-23 HOUR (0-23)
*
* *To allow for leap seconds. But these never actually happen.
*/
tmp = (timr & RTC_TIMR_SEC_MASK) >> RTC_TIMR_SEC_SHIFT;
tp->tm_sec = rtc_bcd2bin(tmp);
tmp = (timr & RTC_TIMR_MIN_MASK) >> RTC_TIMR_MIN_SHIFT;
tp->tm_min = rtc_bcd2bin(tmp);
tmp = (timr & RTC_TIMR_HOUR_MASK) >> RTC_TIMR_HOUR_SHIFT;
tp->tm_hour = rtc_bcd2bin(tmp);
/* Convert the RTC date register fields to struct tm format.
*
* struct tm TIMR register
* tm_mday 1-31 DATE (1-31)
* tm_wday 0-6 DAY (1-7) **
* tm_mon 0-11 MONTH: (1-12)
* tm_year * YEAR (0-99)
* CENT (19-20)
*
* *Years since 1900
* **Day of the week is not supported
*/
tmp = (calr & RTC_CALR_DATE_MASK) >> RTC_CALR_DATE_SHIFT;
tp->tm_mday = rtc_bcd2bin(tmp);
tmp = (calr & RTC_CALR_MONTH_MASK) >> RTC_CALR_MONTH_SHIFT;
tp->tm_mon = rtc_bcd2bin(tmp) - 1;
tmp = (calr & RTC_CALR_CENT_MASK) >> RTC_CALR_CENT_SHIFT;
cent = rtc_bcd2bin(tmp);
tmp = (calr & RTC_CALR_YEAR_MASK) >> RTC_CALR_YEAR_SHIFT;
year = rtc_bcd2bin(tmp);
tp->tm_year = cent * 100 + year - 1900;
rtc_dumptime(tp, "Returning");
return OK;
}
/****************************************************************************
* Name: up_rtc_settime
*
* Description:
* Set the RTC to the provided time.
* All RTC implementations must be able to set their time based on a
* standard timespec.
*
* Input Parameters:
* tp - the time to use
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int up_rtc_settime(FAR const struct timespec *tp)
{
FAR struct tm newtime;
uint32_t regval;
uint32_t timr;
uint32_t calr;
uint32_t cent;
uint32_t year;
/* Break out the time values
* (note that the time is set only to units of seconds)
*/
gmtime_r(&tp->tv_sec, &newtime);
rtc_dumptime(&newtime, "Setting time");
/* Then write the broken out values to the RTC */
/* Convert the struct tm format to RTC time register fields.
*
* struct tm TIMR register
* tm_sec 0-61* SEC (0-59)
* tm_min 0-59 MIN (0-59)
* tm_hour 0-23 HOUR (0-23)
*
* *To allow for leap seconds. But these never actually happen.
*/
timr = (rtc_bin2bcd(newtime.tm_sec) << RTC_TIMR_SEC_SHIFT) &
RTC_TIMR_SEC_MASK;
timr |= (rtc_bin2bcd(newtime.tm_min) << RTC_TIMR_MIN_SHIFT) &
RTC_TIMR_MIN_MASK;
timr |= (rtc_bin2bcd(newtime.tm_hour) << RTC_TIMR_HOUR_SHIFT) &
RTC_TIMR_HOUR_MASK;
/* Convert the struct tm format to RTC date register fields.
*
* struct tm CALR register
* tm_mday 1-31 DATE (1-31)
* tm_wday 0-6 DAY (1-7) **
* tm_mon 0-11 MONTH: (1-12)
* tm_year * YEAR (0-99)
* CENT (19-20)
*
* *Years since 1900
* **Day of the week is not supported. Set to Monday.
*/
calr = (rtc_bin2bcd(newtime.tm_mday) << RTC_CALR_DATE_SHIFT) &
RTC_CALR_DATE_MASK;
calr |= (rtc_bin2bcd(1) << RTC_CALR_DAY_SHIFT) &
RTC_CALR_DAY_MASK;
calr |= (rtc_bin2bcd(newtime.tm_mon + 1) << RTC_CALR_MONTH_SHIFT) &
RTC_CALR_MONTH_MASK;
cent = newtime.tm_year / 100 + 19;
year = newtime.tm_year % 100;
calr |= (rtc_bin2bcd(year) << RTC_CALR_YEAR_SHIFT) &
RTC_CALR_YEAR_MASK;
calr |= (rtc_bin2bcd(cent) << RTC_CALR_CENT_SHIFT) &
RTC_CALR_CENT_MASK;
/* Stop RTC time and date counting */
regval = getreg32(SAM_RTC_CR);
regval |= (RTC_CR_UPDTIM | RTC_CR_UPDCAL);
putreg32(regval, SAM_RTC_CR);
/* Wait until the RTC has stopped so that we can update the time */
while ((getreg32(SAM_RTC_SR) & RTC_SR_ACKUPD) != RTC_SR_ACKUPD);
/* Clear the ACKUPD bit in the status register */
putreg32(RTC_SCCR_ACKCLR, SAM_RTC_SCCR);
/* Set the new date */
putreg32(calr, SAM_RTC_CALR);
/* Write the new time */
putreg32(timr, SAM_RTC_TIMR);
/* Resume RTC date/time counting */
regval = getreg32(SAM_RTC_CR);
regval &= ~(RTC_CR_UPDTIM | RTC_CR_UPDCAL);
putreg32(regval, SAM_RTC_CR);
/* Clear the SEC status in the SR */
regval = getreg32(SAM_RTC_SCCR);
regval = RTC_SCCR_SECCLR;
putreg32(regval, SAM_RTC_SCCR);
/* The RTC should now be enabled */
g_rtc_enabled = ((getreg32(SAM_RTC_VER) &
(RTC_VER_NVTIM | RTC_VER_NVCAL)) == 0);
DEBUGASSERT(g_rtc_enabled);
rtc_dumpregs("New time setting");
return OK;
}
/****************************************************************************
* Name: sam_rtc_setalarm
*
* Description:
* Set up an alarm.
* Up to two alarms can be supported (ALARM A and ALARM B).
*
* Input Parameters:
* tp - the time to set the alarm
* callback - the function to call when the alarm expires.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
int sam_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback)
{
FAR struct tm newalarm;
irqstate_t flags;
uint32_t timalr;
uint32_t calalr;
int ret = -EBUSY;
/* Is there already something waiting on the ALARM? */
flags = enter_critical_section();
if (g_alarmcb == NULL)
{
/* No.. Save the callback function pointer */
g_alarmcb = callback;
/* Clear any pending alarm interrupts */
putreg32(RTC_SCCR_ALRCLR, SAM_RTC_SCCR);
/* Break out the time values (note that the time is set only to units
* of seconds)
*/
gmtime_r(&tp->tv_sec, &newalarm);
rtc_dumptime(&newalarm, "Setting alarm");
/* Then write the broken out values to the RTC */
/* Convert the struct tm format to RTC time register fields.
*
* struct tm TIMALR register
* tm_sec 0-61* SEC (0-59)
* tm_min 0-59 MIN (0-59)
* tm_hour 0-23 HOUR (0-23)
*
* *To allow for leap seconds. But these never actually happen.
*/
timalr = (rtc_bin2bcd(newalarm.tm_sec) << RTC_TIMALR_SEC_SHIFT) &
RTC_TIMALR_SEC_MASK;
timalr |= (rtc_bin2bcd(newalarm.tm_min) << RTC_TIMALR_MIN_SHIFT) &
RTC_TIMALR_MIN_MASK;
timalr |= (rtc_bin2bcd(newalarm.tm_hour) << RTC_TIMALR_HOUR_SHIFT) &
RTC_TIMALR_HOUR_MASK;
timalr |= (RTC_TIMALR_SECEN | RTC_TIMALR_MINEN | RTC_TIMALR_HOUREN);
/* Convert the struct tm format to RTC date register fields.
*
* struct tm CALALR register
* tm_mday 1-31 DATE (1-31)
* tm_wday 0-6 DAY (1-7) **
* tm_mon 0-11 MONTH: (1-12)
* tm_year * YEAR (0-99)
* CENT (19-20)
*
* *Years since 1900
* **Day of the week is not supported
*/
calalr = (rtc_bin2bcd(newalarm.tm_mday) <<
RTC_CALALR_DATE_SHIFT) &
RTC_CALALR_DATE_MASK;
calalr |= (rtc_bin2bcd(newalarm.tm_mon + 1) <<
RTC_CALALR_MONTH_SHIFT) &
RTC_CALALR_MONTH_MASK;
calalr |= (RTC_CALALR_MTHEN | RTC_CALALR_DATEEN);
/* Set the new date */
putreg32(calalr, SAM_RTC_CALALR);
/* Write the new time */
putreg32(timalr, SAM_RTC_TIMALR);
DEBUGASSERT((getreg32(SAM_RTC_VER) & RTC_VER_NVTIMALR) == 0);
DEBUGASSERT((getreg32(SAM_RTC_VER) & RTC_VER_NVCALALR) == 0);
rtc_dumpregs("New alarm setting");
/* Enable alarm interrupts */
putreg32(RTC_IER_ALREN, SAM_RTC_IER);
ret = OK;
}
leave_critical_section(flags);
return ret;
}
#endif
#endif /* CONFIG_RTC */

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/****************************************************************************
* arch/arm/src/sama5/sam_rtc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_RTC_H
#define __ARCH_ARM_SRC_SAMA5_SAM_RTC_H
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_rtc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/* The form of an alarm callback */
typedef void (*alarmcb_t)(void);
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_rtc_setalarm
*
* Description:
* Set up an alarm.
*
* Input Parameters:
* tp - the time to set the alarm
* callback - the function to call when the alarm expires.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
struct timespec;
int sam_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_RTC_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_sckc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/clock.h>
#include <arch/board/board.h>
#include "arm_arch.h"
#include "sam_sckc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: sam_sckc_enable
*
* Description:
* Enable or disable the slow clock oscillator driver by an external
* crystal.
*
* Input Parameters:
* enable - True: enable the slow clock, False: disable the slow clock
*
* Returned Value:
* None
*
****************************************************************************/
void sam_sckc_enable(bool enable)
{
uint32_t regval;
#ifdef ATSAMA5D3
/* REVISIT: Missing the logic that disables the external OSC32 */
/* Enable external OSC 32 kHz */
regval = getreg32(SAM_SCKC_CR);
regval |= SCKC_CR_OSC32EN;
putreg32(regval, SAM_SCKC_CR);
/* Wait for 32,768 XTAL start-up time */
up_udelay(5 * USEC_PER_SEC / BOARD_SLOWCLK_FREQUENCY);
/* Disable OSC 32 kHz bypass */
regval &= ~SCKC_CR_OSC32BYP;
putreg32(regval, SAM_SCKC_CR);
/* Switch slow clock source to external OSC 32 kHz */
regval |= SCKC_CR_OSCSEL;
putreg32(regval, SAM_SCKC_CR);
/* Wait 5 slow clock cycles for internal resynchronization */
up_udelay(5 * USEC_PER_SEC / BOARD_SLOWCLK_FREQUENCY);
/* Disable internal RC 32 kHz */
regval &= ~SCKC_CR_RCEN;
putreg32(regval, SAM_SCKC_CR);
#else
/* Switch slow clock source to external OSC 32 kHz */
regval = enable ? SCKC_CR_OSCSEL : 0;
putreg32(regval, SAM_SCKC_CR);
/* Wait 5 slow clock cycles for internal resynchronization */
up_udelay(5 * USEC_PER_SEC / BOARD_SLOWCLK_FREQUENCY);
#endif
}

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/****************************************************************************
* arch/arm/src/sama5/sam_sckc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_SCKC_H
#define __ARCH_ARM_SRC_SAMA5_SAM_SCKC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include "chip.h"
#include "hardware/sam_sckc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_sckc_enable
*
* Description:
* Enable or disable the slow clock oscillator driver by an external
* crystal.
*
* Input Parameters:
* enable - True: enable the slow clock, False: disable the slow clock
*
* Returned Value:
* None
*
****************************************************************************/
void sam_sckc_enable(bool enable);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_SCKC_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_sdmmc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SDMMC_H
#define __ARCH_ARM_SRC_SAMA5_SDMMC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/sdio.h>
#include <nuttx/mmcsd.h>
#include "chip.h"
#include "hardware/sam_sdmmc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_sdmmc_set_sdio_card_isr
*
* Description:
* SDIO card generates interrupt via SDIO_DATA_1 pin.
* Called by board-specific logic to register an ISR for SDIO card.
*
* Input Parameters:
* func - callback function.
* arg - arg to be passed to the function.
*
* Returned Value:
* None
*
****************************************************************************/
void sam_sdmmc_set_sdio_card_isr(FAR struct sdio_dev_s *dev,
int (*func)(void *), void *arg);
/****************************************************************************
* Name: sam_sdmmc_sdio_initialize
*
* Description:
* Initialize SDMMC for operation.
*
* Input Parameters:
* slotno - Not used.
*
* Returned Value:
* A reference to a SDIO interface structure. NULL is returned on
* failures.
*
****************************************************************************/
FAR struct sdio_dev_s *sam_sdmmc_sdio_initialize(int slotno);
/****************************************************************************
* Name: sdio_mediachange
*
* Description:
* Called by board-specific logic -- possibly from an interrupt handler --
* in order to signal to the driver that a card has been inserted or
* removed from the slot
*
* Input Parameters:
* dev - An instance of the SDIO driver device state structure.
* cardinslot - true is a card has been detected in the slot; false if a
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
* Returned Value:
* None
*
****************************************************************************/
void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
/****************************************************************************
* Name: sdio_wrprotect
*
* Description:
* Called by board-specific logic to report if the card in the slot is
* mechanically write protected.
*
* Input Parameters:
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is writeprotected.
*
* Returned Value:
* None
*
****************************************************************************/
void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect);
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SDMMC_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_serial.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_SERIAL_H
#define __ARCH_ARM_SRC_SAMA5_SAM_SERIAL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_internal.h"
#include "sam_config.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_earlyserialinit
*
* Description:
* Performs the low level USART initialization early in debug so that the
* serial console will be available during bootup. This must be called
* before arm_serialinit.
*
****************************************************************************/
#ifdef USE_EARLYSERIALINIT
void sam_earlyserialinit(void);
#endif
/****************************************************************************
* Name: uart_earlyserialinit
*
* Description:
* Performs the low level USART initialization early in debug so that the
* serial console will be available during bootup. This must be called
* before arm_serialinit.
*
****************************************************************************/
#if defined(USE_EARLYSERIALINIT) && (defined(SAMA5_HAVE_UART) || defined(SAMA5_HAVE_USART))
void uart_earlyserialinit(void);
#endif
/****************************************************************************
* Name: flexus_earlyserialinit
*
* Description:
* Performs the low level Flexcom USART initialization early so that the
* Flexcom serial console will be available during bootup. This must be
* called before flexus_serialinit.
*
****************************************************************************/
#if defined(USE_EARLYSERIALINIT) && defined(SAMA5_HAVE_FLEXCOM_USART)
void flexus_earlyserialinit(void);
#endif
/****************************************************************************
* Name: uart_serialinit
*
* Description:
* Register UART/USART serial console and serial ports. This assumes that
* uart_earlyserialinit was called previously.
*
****************************************************************************/
#if defined(USE_SERIALDRIVER) && (defined(SAMA5_HAVE_UART) || defined(SAMA5_HAVE_USART))
void uart_serialinit(void);
#endif
/****************************************************************************
* Name: flexus_serialinit
*
* Description:
* Register Flexcom serial console and serial ports. This assumes that
* flexus_earlyserialinit was called previously.
*
****************************************************************************/
#if defined(USE_SERIALDRIVER) && defined(SAMA5_HAVE_FLEXCOM_USART)
void flexus_serialinit(void);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_SERIAL_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_serialinit.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "sam_config.h"
#include "sam_dbgu.h"
#include "sam_serial.h"
#ifdef USE_SERIALDRIVER
/****************************************************************************
* Public Functions
****************************************************************************/
#ifdef USE_EARLYSERIALINIT
/****************************************************************************
* Name: sam_earlyserialinit
*
* Description:
* Performs the low level serial initialization early so that the serial
* console will be available during bootup. This must be called
* before arm_serialinit.
*
****************************************************************************/
void sam_earlyserialinit(void)
{
/* NOTE: All PIO configuration for the USARTs was performed in
* sam_lowsetup
*/
#if defined(SAMA5_HAVE_UART) || defined(SAMA5_HAVE_USART)
/* Initialize UART/USART drivers */
uart_earlyserialinit();
#endif
#ifdef SAMA5_HAVE_FLEXCOM_USART
/* Initialize Flexcom USARTs */
flexus_earlyserialinit();
#endif
}
#endif
/****************************************************************************
* Name: arm_serialinit
*
* Description:
* Register all serial console and serial ports. This assumes
* that arm_earlyserialinit was called previously.
*
****************************************************************************/
void arm_serialinit(void)
{
#if defined(SAMA5_HAVE_UART) || defined(SAMA5_HAVE_USART)
/* Register UART/USART drivers */
uart_serialinit();
#endif
#ifdef SAMA5_HAVE_FLEXCOM_USART
/* Register Flexcom USART drivers */
flexus_serialinit();
#endif
/* Register the DBGU as well */
#ifdef CONFIG_SAMA5_DBGU
sam_dbgu_register();
#endif
}
#endif /* USE_SERIALDRIVER */

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/****************************************************************************
* arch/arm/src/sama5/sam_spi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_SPI_H
#define __ARCH_ARM_SRC_SAMA5_SAM_SPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The SPI port number used as an input to sam_spibus_initialize encodes
* information about the SPI controller (0 or 1) and the SPI chip select
* (0-3)
*/
#define __SPI_CS_SHIFT (0) /* Bits 0-1: SPI chip select number */
#define __SPI_CS_MASK (3 << __SPI_CS_SHIFT)
# define __SPI_CS0 (0 << __SPI_CS_SHIFT)
# define __SPI_CS1 (1 << __SPI_CS_SHIFT)
# define __SPI_CS2 (2 << __SPI_CS_SHIFT)
# define __SPI_CS3 (3 << __SPI_CS_SHIFT)
#define __SPI_SPI_SHIFT (2) /* Bit 2: SPI controller number */
#define __SPI_SPI_MASK (1 << __SPI_SPI_SHIFT)
# define __SPI_SPI0 (0 << __SPI_SPI_SHIFT) /* SPI0 */
# define __SPI_SPI1 (1 << __SPI_SPI_SHIFT) /* SPI1 */
#define SPI0_CS0 (__SPI_SPI0 | __SPI_CS0)
#define SPI0_CS1 (__SPI_SPI0 | __SPI_CS1)
#define SPI0_CS2 (__SPI_SPI0 | __SPI_CS2)
#define SPI0_CS3 (__SPI_SPI0 | __SPI_CS3)
#define SPI1_CS0 (__SPI_SPI1 | __SPI_CS0)
#define SPI1_CS1 (__SPI_SPI1 | __SPI_CS1)
#define SPI1_CS2 (__SPI_SPI1 | __SPI_CS2)
#define SPI1_CS3 (__SPI_SPI1 | __SPI_CS3)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
struct spi_dev_s; /* Forward reference */
/****************************************************************************
* Name: sam_spibus_initialize
*
* Description:
* Initialize the selected SPI port
*
* Input Parameters:
* cs - Chip select number (identifying the "logical" SPI port)
*
* Returned Value:
* Valid SPI device structure reference on success; a NULL on failure
*
****************************************************************************/
struct spi_dev_s *sam_spibus_initialize(int port);
/****************************************************************************
* Name: sam_spi[0|1]select, sam_spi[0|1]status, and sam_spi[0|1]cmddata
*
* Description:
* These external functions must be provided by board-specific logic. They
* include:
*
* o sam_spi[0|1]select is a functions tomanage the board-specific chip
* selects
* o sam_spi[0|1]status and sam_spi[0|1]cmddata: Implementations of the
* status and cmddata methods of the SPI interface defined by struct
* spi_ops_ (see include/nuttx/spi/spi.h). All other methods including
* sam_spibus_initialize()) are provided by common SAM3/4 logic.
*
* To use this common SPI logic on your board:
*
* 1. Provide logic in sam_boardinitialize() to configure SPI chip select
* pins.
* 2. Provide sam_spi[0|1]select() and sam_spi[0|1]status() functions in
* your board- specific logic. These functions will perform chip
* selection and status operations using PIOs in the way your board is
* configured.
* 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
* sam_spi[0|1]cmddata() functions in your board-specific logic. This
* function will perform cmd/data selection operations using PIOs in
* the way your board is configured.
* 3. Add a call to sam_spibus_initialize() in your low level application
* initialization logic
* 4. The handle returned by sam_spibus_initialize() may then be used to
* bind the SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
****************************************************************************/
/****************************************************************************
* Name: sam_spi[0|1]select
*
* Description:
* PIO chip select pins may be programmed by the board specific logic in
* one of two different ways. First, the pins may be programmed as SPI
* peripherals. In that case, the pins are completely controlled by the
* SPI driver. This method still needs to be provided, but it may be only
* a stub.
*
* An alternative way to program the PIO chip select pins is as a normal
* PIO output. In that case, the automatic control of the CS pins is
* bypassed and this function must provide control of the chip select.
* NOTE: In this case, the PIO output pin does *not* have to be the
* same as the NPCS pin normal associated with the chip select number.
*
* Input Parameters:
* dev - SPI device info
* devid - Identifies the (logical) device
* selected - TRUE:Select the device, FALSE:De-select the device
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_SAMA5_SPI0
void sam_spi0select(uint32_t devid, bool selected);
#endif
#ifdef CONFIG_SAMA5_SPI1
void sam_spi1select(uint32_t devid, bool selected);
#endif
/****************************************************************************
* Name: sam_spi[0|1]status
*
* Description:
* Return status information associated with the SPI device.
*
* Input Parameters:
* dev - SPI device info
* devid - Identifies the (logical) device
*
* Returned Value:
* Bit-encoded SPI status (see include/nuttx/spi/spi.h.
*
****************************************************************************/
#ifdef CONFIG_SAMA5_SPI0
uint8_t sam_spi0status(FAR struct spi_dev_s *dev, uint32_t devid);
#endif
#ifdef CONFIG_SAMA5_SPI1
uint8_t sam_spi1status(FAR struct spi_dev_s *dev, uint32_t devid);
#endif
/****************************************************************************
* Name: sam_spi[0|1]cmddata
*
* Description:
* Some SPI devices require an additional control to determine if the SPI
* data being sent is a command or is data. If CONFIG_SPI_CMDDATA then
* this function will be called to different be command and data transfers.
*
* This is often needed, for example, by LCD drivers. Some LCD hardware
* may be configured to use 9-bit data transfers with the 9th bit
* indicating command or data. That same hardware may be configurable,
* instead, to use 8-bit data but to require an additional, board-
* specific PIO control to distinguish command and data. This function
* would be needed in that latter case.
*
* Input Parameters:
* dev - SPI device info
* devid - Identifies the (logical) device
*
* Returned Value:
* Zero on success; a negated errno on failure.
*
****************************************************************************/
#ifdef CONFIG_SPI_CMDDATA
#ifdef CONFIG_SAMA5_SPI0
int sam_spi0cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_SAMA5_SPI1
int sam_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_SPI_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_ssc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_SSC_H
#define __ARCH_ARM_SRC_SAMA5_SAM_SSC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/audio/i2s.h>
#include "chip.h"
#include "hardware/sam_ssc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_ssc_initialize
*
* Description:
* Initialize the selected I2S port.
*
* Input Parameters:
* Port number (for hardware that has multiple I2S interfaces)
*
* Returned Value:
* Valid I2S device structure reference on success; a NULL on failure
*
****************************************************************************/
FAR struct i2s_dev_s *sam_ssc_initialize(int port);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_SSC_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_systemreset.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <arch/sama5/chip.h>
#include "arm_arch.h"
#include "hardware/sam_rstc.h"
#ifdef CONFIG_SAMA5_SYSTEMRESET
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_systemreset
*
* Description:
* Internal reset logic.
*
****************************************************************************/
void up_systemreset(void)
{
uint32_t rstcr;
#if defined(CONFIG_SAMA5_EXTRESET_ERST) && CONFIG_SAMA5_EXTRESET_ERST != 0
uint32_t rstmr;
#endif
rstcr = (RSTC_CR_PROCRST | RSTC_CR_KEY);
#if defined(CONFIG_SAMA5_EXTRESET_ERST) && CONFIG_SAMA5_EXTRESET_ERST != 0
rstcr |= RSTC_CR_EXTRST;
rstmr = getreg32(SAM_RSTC_MR);
rstmr &= ~RSTC_MR_ERSTL_MASK;
rstmr &= RSTC_MR_ERSTL(CONFIG_SAMA5_EXTRESET_ERST - 1) | RSTC_MR_KEY;
putreg32(rstmr, SAM_RSTC_MR);
#endif
putreg32(rstcr, SAM_RSTC_CR);
/* Wait for the reset */
for (; ; );
}
#endif /* CONFIG_SAMA5_SYSTEMRESET */

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/****************************************************************************
* arch/arm/src/sama5/sam_tc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_TC_H
#define __ARCH_ARM_SRC_SAMA5_SAM_TC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <debug.h>
#include "chip.h"
#include "hardware/sam_tc.h"
#if defined(CONFIG_SAMA5_TC0) || defined(CONFIG_SAMA5_TC1) || defined(CONFIG_SAMA5_TC2)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The timer/counter and channel arguments to sam_tc_allocate() */
#define TC_CHAN0 0 /* TC0 */
#define TC_CHAN1 1
#define TC_CHAN2 2
#define TC_CHAN3 3 /* TC1 */
#define TC_CHAN4 4
#define TC_CHAN5 5
#define TC_CHAN6 6 /* TC2 */
#define TC_CHAN7 7
#define TC_CHAN8 8
/* Register identifier used with sam_tc_setregister */
#define TC_REGA 0
#define TC_REGB 1
#define TC_REGC 2
/* Timer debug is enabled if any timer client is enabled */
#ifndef CONFIG_DEBUG_TIMER_INFO
# undef CONFIG_SAMA5_TC_REGDEBUG
#endif
#if !defined(CONFIG_SAMA5_TC_DEBUG) && defined(CONFIG_SAMA5_ADC) && defined(CONFIG_DEBUG_ANALOG)
# define CONFIG_SAMA5_TC_DEBUG 1
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/* An opaque handle used to represent a timer channel */
typedef void *TC_HANDLE;
/* Timer interrupt callback. When a timer interrupt expires, the client will
* receive:
*
* tch - The handle that represents the timer state
* arg - An opaque argument provided when the interrupt was registered
* sr - The value of the timer interrupt status register at the time
* that the interrupt occurred.
*/
typedef void (*tc_handler_t)(TC_HANDLE tch, void *arg, uint32_t sr);
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_tc_allocate
*
* Description:
* Configures a Timer Counter to operate in the given mode. The timer is
* stopped after configuration and must be restarted with sam_tc_start().
* All the interrupts of the timer are also disabled.
*
* Input Parameters:
* channel TC channel number (see TC_CHANx definitions)
* mode Operating mode (TC_CMR value).
*
* Returned Value:
* On success, a non-NULL handle value is returned. This handle may be
* used with subsequent timer/counter interfaces to manage the timer. A
* NULL handle value is returned on a failure.
*
****************************************************************************/
TC_HANDLE sam_tc_allocate(int channel, int mode);
/****************************************************************************
* Name: sam_tc_free
*
* Description:
* Release the handle previously allocated by sam_tc_allocate().
*
* Input Parameters:
* handle Channel handle previously allocated by sam_tc_allocate()
*
* Returned Value:
* None
*
****************************************************************************/
void sam_tc_free(TC_HANDLE handle);
/****************************************************************************
* Name: sam_tc_start
*
* Description:
* Reset and Start the TC Channel. Enables the timer clock and performs a
* software reset to start the counting.
*
* Input Parameters:
* handle Channel handle previously allocated by sam_tc_allocate()
*
* Returned Value:
*
****************************************************************************/
void sam_tc_start(TC_HANDLE handle);
/****************************************************************************
* Name: sam_tc_stop
*
* Description:
* Stop TC Channel. Disables the timer clock, stopping the counting.
*
* Input Parameters:
* handle Channel handle previously allocated by sam_tc_allocate()
*
* Returned Value:
*
****************************************************************************/
void sam_tc_stop(TC_HANDLE handle);
/****************************************************************************
* Name: sam_tc_attach/sam_tc_detach
*
* Description:
* Attach or detach an interrupt handler to the timer interrupt. The
* interrupt is detached if the handler argument is NULL.
*
* Input Parameters:
* handle The handle that represents the timer state
* handler The interrupt handler that will be invoked when the interrupt
* condition occurs
* arg An opaque argument that will be provided when the interrupt
* handler callback is executed. Ignored if handler is NULL.
* mask The value of the timer interrupt mask register that defines
* which interrupts should be disabled. Ignored if handler is
* NULL.
*
* Returned Value:
* The address of the previous handler, if any.
*
****************************************************************************/
tc_handler_t sam_tc_attach(TC_HANDLE handle, tc_handler_t handler,
void *arg, uint32_t mask);
#define sam_tc_detach(h) sam_tc_attach(h, NULL, NULL, 0)
/****************************************************************************
* Name: sam_tc_getpending
*
* Description:
* Return the current contents of the interrupt status register, clearing
* all pending interrupts.
*
* Input Parameters:
* handle The handle that represents the timer state
*
* Returned Value:
* The value of the channel interrupt status register.
*
****************************************************************************/
uint32_t sam_tc_getpending(TC_HANDLE handle);
/****************************************************************************
* Name: sam_tc_setregister
*
* Description:
* Set TC_REGA, TC_REGB, or TC_REGC register.
*
* Input Parameters:
* handle Channel handle previously allocated by sam_tc_allocate()
* regid One of {TC_REGA, TC_REGB, or TC_REGC}
* regval Then value to set in the register
*
* Returned Value:
* None
*
****************************************************************************/
void sam_tc_setregister(TC_HANDLE handle, int regid, uint32_t regval);
/****************************************************************************
* Name: sam_tc_getregister
*
* Description:
* Get the current value of the TC_REGA, TC_REGB, or TC_REGC register.
*
* Input Parameters:
* handle Channel handle previously allocated by sam_tc_allocate()
* regid One of {TC_REGA, TC_REGB, or TC_REGC}
*
* Returned Value:
* The value of the specified register.
*
****************************************************************************/
uint32_t sam_tc_getregister(TC_HANDLE handle, int regid);
/****************************************************************************
* Name: sam_tc_getcounter
*
* Description:
* Return the current value of the timer counter register
*
* Input Parameters:
* handle Channel handle previously allocated by sam_tc_allocate()
*
* Returned Value:
* The current value of the timer counter register for this channel.
*
****************************************************************************/
uint32_t sam_tc_getcounter(TC_HANDLE handle);
/****************************************************************************
* Name: sam_tc_infreq
*
* Description:
* Return the timer input frequency, that is, the MCK frequency divided
* down so that the timer/counter is driven within its maximum frequency.
*
* Input Parameters:
* None
*
* Returned Value:
* The timer input frequency.
*
****************************************************************************/
uint32_t sam_tc_infreq(void);
/****************************************************************************
* Name: sam_tc_divfreq
*
* Description:
* Return the divided timer input frequency that is currently driving the
* the timer counter.
*
* Input Parameters:
* handle Channel handle previously allocated by sam_tc_allocate()
*
* Returned Value:
* The timer counter frequency.
*
****************************************************************************/
uint32_t sam_tc_divfreq(TC_HANDLE handle);
/****************************************************************************
* Name: sam_tc_divisor
*
* Description:
* Finds the best MCK divisor given the timer frequency and MCK. The
* result is guaranteed to satisfy the following equation:
*
* (Ftcin / (div * 65536)) <= freq <= (Ftcin / div)
*
* where:
* freq - the desired frequency
* Ftcin - The timer/counter input frequency
* div - With DIV being the highest possible value.
*
* Input Parameters:
* frequency Desired timer frequency.
* div Divisor value.
* tcclks TCCLKS field value for divisor.
*
* Returned Value:
* Zero (OK) if a proper divisor has been found, otherwise a negated errno
* value indicating the nature of the failure.
*
****************************************************************************/
int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* CONFIG_SAMA5_TC0 || CONFIG_SAMA5_TC1 || CONFIG_SAMA5_TC2 */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_TC_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_tickless.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Tickless OS Support.
*
* When CONFIG_SCHED_TICKLESS is enabled, all support for timer interrupts
* is suppressed and the platform specific code is expected to provide the
* following custom functions.
*
* void up_timer_initialize(void): Initializes the timer facilities.
* Called early in the initialization sequence (by up_initialize()).
* int up_timer_gettime(FAR struct timespec *ts): Returns the current
* time from the platform specific time source.
* int up_timer_cancel(void): Cancels the interval timer.
* int up_timer_start(FAR const struct timespec *ts): Start (or re-starts)
* the interval timer.
*
* The RTOS will provide the following interfaces for use by the platform-
* specific interval timer implementation:
*
* void nxsched_timer_expiration(void): Called by the platform-specific
* logic when the interval timer expires.
*
****************************************************************************/
/****************************************************************************
* SAMA5 Timer Usage
*
* This current implementation uses two timers: A one-shot timer to provide
* the timed events and a free running timer to provide the current time.
* Since timers are a limited resource, that could be an issue on some
* systems.
*
* We could do the job with a single timer if we were to keep the single
* timer in a free-running at all times. The SAMA5 timer/counters have
* 32-bit counters with the capability to generate a compare interrupt when
* the timer matches a compare value but also to continue counting without
* stopping (giving another, different interrupt when the timer rolls over
* from 0xffffffff to zero). So we could potentially just set the compare
* at the number of ticks you want PLUS the current value of timer. Then
* you could have both with a single timer: An interval timer and a free-
* running counter with the same timer!
*
* Patches are welcome!
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <nuttx/arch.h>
#include "sam_oneshot.h"
#include "sam_freerun.h"
#ifdef CONFIG_SCHED_TICKLESS
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef CONFIG_SAMA5_HAVE_TC
# error Timer/counters must be selected for the Tickless OS option
#endif
#ifndef CONFIG_SAMA5_ONESHOT
# error CONFIG_SAMA5_ONESHOT must be selected for the Tickless OS option
#endif
#ifndef CONFIG_SAMA5_FREERUN
# error CONFIG_SAMA5_FREERUN must be selected for the Tickless OS option
#endif
#ifndef CONFIG_SAMA5_TICKLESS_FREERUN
# error CONFIG_SAMA5_TICKLESS_FREERUN must be selected for the Tickless OS option
#endif
#ifndef CONFIG_SAMA5_TICKLESS_ONESHOT
# error CONFIG_SAMA5_TICKLESS_ONESHOT must be selected for the Tickless OS option
#endif
#if CONFIG_SAMA5_TICKLESS_ONESHOT == 0 && !defined(CONFIG_SAMA5_TC0)
# error CONFIG_SAMA5_TICKLESS_ONESHOT == 0 && CONFIG_SAMA5_TC0 not selected
#elif CONFIG_SAMA5_TICKLESS_ONESHOT == 1 && !defined(CONFIG_SAMA5_TC0)
# error CONFIG_SAMA5_TICKLESS_ONESHOT == 1 && CONFIG_SAMA5_TC0 not selected
#elif CONFIG_SAMA5_TICKLESS_ONESHOT == 2 && !defined(CONFIG_SAMA5_TC0)
# error CONFIG_SAMA5_TICKLESS_ONESHOT == 2 && CONFIG_SAMA5_TC0 not selected
#elif CONFIG_SAMA5_TICKLESS_ONESHOT == 3 && !defined(CONFIG_SAMA5_TC1)
# error CONFIG_SAMA5_TICKLESS_ONESHOT == 3 && CONFIG_SAMA5_TC1 not selected
#elif CONFIG_SAMA5_TICKLESS_ONESHOT == 4 && !defined(CONFIG_SAMA5_TC1)
# error CONFIG_SAMA5_TICKLESS_ONESHOT == 4 && CONFIG_SAMA5_TC1 not selected
#elif CONFIG_SAMA5_TICKLESS_ONESHOT == 5 && !defined(CONFIG_SAMA5_TC1)
# error CONFIG_SAMA5_TICKLESS_ONESHOT == 5 && CONFIG_SAMA5_TC1 not selected
#elif CONFIG_SAMA5_TICKLESS_ONESHOT == 6 && !defined(CONFIG_SAMA5_TC2)
# error CONFIG_SAMA5_TICKLESS_ONESHOT == 6 && CONFIG_SAMA5_TC2 not selected
#elif CONFIG_SAMA5_TICKLESS_ONESHOT == 7 && !defined(CONFIG_SAMA5_TC2)
# error CONFIG_SAMA5_TICKLESS_ONESHOT == 7 && CONFIG_SAMA5_TC2 not selected
#elif CONFIG_SAMA5_TICKLESS_ONESHOT == 8 && !defined(CONFIG_SAMA5_TC2)
# error CONFIG_SAMA5_TICKLESS_ONESHOT == 8 && CONFIG_SAMA5_TC2 not selected
#endif
#if CONFIG_SAMA5_TICKLESS_ONESHOT < 0 || CONFIG_SAMA5_TICKLESS_ONESHOT > 8
# error CONFIG_SAMA5_TICKLESS_ONESHOT is not valid
#endif
#if CONFIG_SAMA5_TICKLESS_FREERUN == 0 && !defined(CONFIG_SAMA5_TC0)
# error CONFIG_SAMA5_TICKLESS_FREERUN == 0 && CONFIG_SAMA5_TC0 not selected
#elif CONFIG_SAMA5_TICKLESS_FREERUN == 1 && !defined(CONFIG_SAMA5_TC0)
# error CONFIG_SAMA5_TICKLESS_FREERUN == 1 && CONFIG_SAMA5_TC0 not selected
#elif CONFIG_SAMA5_TICKLESS_FREERUN == 2 && !defined(CONFIG_SAMA5_TC0)
# error CONFIG_SAMA5_TICKLESS_FREERUN == 2 && CONFIG_SAMA5_TC0 not selected
#elif CONFIG_SAMA5_TICKLESS_FREERUN == 3 && !defined(CONFIG_SAMA5_TC1)
# error CONFIG_SAMA5_TICKLESS_FREERUN == 3 && CONFIG_SAMA5_TC1 not selected
#elif CONFIG_SAMA5_TICKLESS_FREERUN == 4 && !defined(CONFIG_SAMA5_TC1)
# error CONFIG_SAMA5_TICKLESS_FREERUN == 4 && CONFIG_SAMA5_TC1 not selected
#elif CONFIG_SAMA5_TICKLESS_FREERUN == 5 && !defined(CONFIG_SAMA5_TC1)
# error CONFIG_SAMA5_TICKLESS_FREERUN == 5 && CONFIG_SAMA5_TC1 not selected
#elif CONFIG_SAMA5_TICKLESS_FREERUN == 6 && !defined(CONFIG_SAMA5_TC2)
# error CONFIG_SAMA5_TICKLESS_FREERUN == 6 && CONFIG_SAMA5_TC2 not selected
#elif CONFIG_SAMA5_TICKLESS_FREERUN == 7 && !defined(CONFIG_SAMA5_TC2)
# error CONFIG_SAMA5_TICKLESS_FREERUN == 7 && CONFIG_SAMA5_TC2 not selected
#elif CONFIG_SAMA5_TICKLESS_FREERUN == 8 && !defined(CONFIG_SAMA5_TC2)
# error CONFIG_SAMA5_TICKLESS_FREERUN == 8 && CONFIG_SAMA5_TC2 not selected
#endif
#if CONFIG_SAMA5_TICKLESS_FREERUN < 0 || CONFIG_SAMA5_TICKLESS_FREERUN > 8
# error CONFIG_SAMA5_TICKLESS_FREERUN is not valid
#endif
#if CONFIG_SAMA5_TICKLESS_FREERUN == CONFIG_SAMA5_TICKLESS_ONESHOT
# error CONFIG_SAMA5_TICKLESS_FREERUN is the same as CONFIG_SAMA5_TICKLESS_ONESHOT
#endif
/****************************************************************************
* Private Types
****************************************************************************/
struct sam_tickless_s
{
struct sam_oneshot_s oneshot;
struct sam_freerun_s freerun;
};
/****************************************************************************
* Private Data
****************************************************************************/
static struct sam_tickless_s g_tickless;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: sam_oneshot_handler
*
* Description:
* Called when the one shot timer expires
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
* Assumptions:
* Called early in the initialization sequence before any special
* concurrency protections are required.
*
****************************************************************************/
static void sam_oneshot_handler(void *arg)
{
tmrinfo("Expired...\n");
nxsched_timer_expiration();
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_timer_initialize
*
* Description:
* Initializes all platform-specific timer facilities. This function is
* called early in the initialization sequence by up_initialize().
* On return, the current up-time should be available from
* up_timer_gettime() and the interval timer is ready for use (but not
* actively timing.
*
* Provided by platform-specific code and called from the architecture-
* specific logic.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
* Assumptions:
* Called early in the initialization sequence before any special
* concurrency protections are required.
*
****************************************************************************/
void up_timer_initialize(void)
{
#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP
uint64_t max_delay;
#endif
int ret;
/* Initialize the one-shot timer */
ret = sam_oneshot_initialize(&g_tickless.oneshot,
CONFIG_SAMA5_TICKLESS_ONESHOT,
CONFIG_USEC_PER_TICK);
if (ret < 0)
{
tmrerr("ERROR: sam_oneshot_initialize failed\n");
DEBUGPANIC();
}
DEBUGASSERT(ONESHOT_INITIALIZED(&g_tickless.oneshot));
#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP
/* Get the maximum delay of the one-shot timer in microseconds */
ret = sam_oneshot_max_delay(&g_tickless.oneshot, &max_delay);
if (ret < 0)
{
tmrerr("ERROR: sam_oneshot_max_delay failed\n");
DEBUGPANIC();
}
/* Convert this to configured clock ticks for use by the OS timer logic */
max_delay /= CONFIG_USEC_PER_TICK;
if (max_delay > (uint64_t)UINT32_MAX)
{
g_oneshot_maxticks = UINT32_MAX;
}
else
{
g_oneshot_maxticks = (uint32_t)max_delay;
}
#endif
/* Initialize the free-running timer */
ret = sam_freerun_initialize(&g_tickless.freerun,
CONFIG_SAMA5_TICKLESS_FREERUN,
CONFIG_USEC_PER_TICK);
if (ret < 0)
{
tmrerr("ERROR: sam_freerun_initialize failed\n");
DEBUGPANIC();
}
DEBUGASSERT(FREERUN_INITIALIZED(&g_tickless.freerun));
}
/****************************************************************************
* Name: up_timer_gettime
*
* Description:
* Return the elapsed time since power-up (or, more correctly, since
* up_timer_initialize() was called). This function is functionally
* equivalent to:
*
* int clock_gettime(clockid_t clockid, FAR struct timespec *ts);
*
* when clockid is CLOCK_MONOTONIC.
*
* This function provides the basis for reporting the current time and
* also is used to eliminate error build-up from small errors in interval
* time calculations.
*
* Provided by platform-specific code and called from the RTOS base code.
*
* Input Parameters:
* ts - Provides the location in which to return the up-time.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure.
*
* Assumptions:
* Called from the normal tasking context. The implementation must
* provide whatever mutual exclusion is necessary for correct operation.
* This can include disabling interrupts in order to assure atomic register
* operations.
*
****************************************************************************/
int up_timer_gettime(FAR struct timespec *ts)
{
return FREERUN_INITIALIZED(&g_tickless.freerun) ?
sam_freerun_counter(&g_tickless.freerun, ts) :
-EAGAIN;
}
/****************************************************************************
* Name: up_timer_cancel
*
* Description:
* Cancel the interval timer and return the time remaining on the timer.
* These two steps need to be as nearly atomic as possible.
* nxsched_timer_expiration() will not be called unless the timer is
* restarted with up_timer_start().
*
* If, as a race condition, the timer has already expired when this
* function is called, then that pending interrupt must be cleared so
* that up_timer_start() and the remaining time of zero should be
* returned.
*
* NOTE: This function may execute at a high rate with no timer running (as
* when pre-emption is enabled and disabled).
*
* Provided by platform-specific code and called from the RTOS base code.
*
* Input Parameters:
* ts - Location to return the remaining time. Zero should be returned
* if the timer is not active. ts may be zero in which case the
* time remaining is not returned.
*
* Returned Value:
* Zero (OK) is returned on success. A call to up_timer_cancel() when
* the timer is not active should also return success; a negated errno
* value is returned on any failure.
*
* Assumptions:
* May be called from interrupt level handling or from the normal tasking
* level. Interrupts may need to be disabled internally to assure
* non-reentrancy.
*
****************************************************************************/
int up_timer_cancel(FAR struct timespec *ts)
{
return ONESHOT_INITIALIZED(&g_tickless.oneshot) &&
FREERUN_INITIALIZED(&g_tickless.freerun) ?
sam_oneshot_cancel(&g_tickless.oneshot, &g_tickless.freerun, ts) :
-EAGAIN;
}
/****************************************************************************
* Name: up_timer_start
*
* Description:
* Start the interval timer. nxsched_timer_expiration() will be
* called at the completion of the timeout (unless up_timer_cancel
* is called to stop the timing.
*
* Provided by platform-specific code and called from the RTOS base code.
*
* Input Parameters:
* ts - Provides the time interval until nxsched_timer_expiration() is
* called.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure.
*
* Assumptions:
* May be called from interrupt level handling or from the normal tasking
* level. Interrupts may need to be disabled internally to assure
* non-reentrancy.
*
****************************************************************************/
int up_timer_start(FAR const struct timespec *ts)
{
return ONESHOT_INITIALIZED(&g_tickless.oneshot) ?
sam_oneshot_start(&g_tickless.oneshot, &g_tickless.freerun,
sam_oneshot_handler, NULL, ts) : -EAGAIN;
}
#endif /* CONFIG_SCHED_TICKLESS */

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/****************************************************************************
* arch/arm/src/sama5/sam_timerisr.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/board/board.h>
#include "arm_arch.h"
#include "sam_periphclks.h"
#include "hardware/sam_pit.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The PIT counter runs at a rate of the main clock (MCK) divided by 16.
*
* On the SAMA5D4, the clocking to the PIC may be divided down from MCK.
* Perhaps because of H32MXDIV? We will let the board.h tell us the correct
* PIT include clock by defining BOARD_PIT_FREQUENCY.
*/
#define PIT_CLOCK (BOARD_PIT_FREQUENCY >> 4)
/* The desired timer interrupt frequency is provided by the definition
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
* system clock ticks per second. That value is a user configurable setting
* that defaults to 100 (100 ticks per second = 10 MS interval).
*
* The PIT counts from zero and up until it reaches the overflow value set
* in the field PIV of the Mode Register (PIT MR). So an PIV value of n
* corresponds a duration of n * PIT_CLOCK
*/
#define PIT_PIV ((PIT_CLOCK + (CLK_TCK >> 1)) / CLK_TCK)
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: sam_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
* of the systems.
*
****************************************************************************/
static int sam_timerisr(int irq, uint32_t *regs, void *arg)
{
/* "When CPIV and PICNT values are obtained by reading the Periodic
* Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is
* reset and the PITS is cleared, thus acknowledging the interrupt. The
* value of PICNT gives the number of periodic intervals elapsed since the
* last read of PIT_PIVR."
*/
uint32_t picnt = getreg32(SAM_PIT_PIVR) >> PIT_PICNT_SHIFT;
/* Process timer interrupt (multiple times if we missed an interrupt) */
while (picnt-- > 0)
{
nxsched_process_timer();
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: up_timer_initialize
*
* Description:
* This function is called during start-up to initialize
* the timer interrupt.
*
****************************************************************************/
void up_timer_initialize(void)
{
uint32_t regval;
/* Enable the PIT peripheral */
sam_pit_enableclk();
/* Make sure that interrupts from the PIT are disabled */
up_disable_irq(SAM_IRQ_PIT);
/* Attach the timer interrupt vector */
irq_attach(SAM_IRQ_PIT, (xcpt_t)sam_timerisr, NULL);
/* Set the PIT overflow value (PIV), enable the PIT, and enable
* interrupts from the PIT.
*/
regval = PIT_PIV;
DEBUGASSERT(regval <= PIT_MR_PIV_MASK);
regval |= (PIT_MR_PITEN | PIT_MR_PITIEN);
putreg32(regval, SAM_PIT_MR);
/* And enable the timer interrupt */
up_enable_irq(SAM_IRQ_PIT);
}

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/****************************************************************************
* arch/arm/src/sama5/sam_trng.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <string.h>
#include <errno.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/fs/fs.h>
#include <nuttx/drivers/drivers.h>
#include <nuttx/semaphore.h>
#include "arm_arch.h"
#include "arm_internal.h"
#include "sam_periphclks.h"
#include "sam_trng.h"
#if defined(CONFIG_SAMA5_TRNG)
#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH)
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Interrupts */
static int sam_interrupt(int irq, void *context, FAR void *arg);
/* Character driver methods */
static ssize_t sam_read(struct file *filep, char *buffer, size_t);
/****************************************************************************
* Private Types
****************************************************************************/
struct trng_dev_s
{
sem_t exclsem; /* Enforces exclusive access to the TRNG */
sem_t waitsem; /* Wait for buffer full */
uint32_t *samples; /* Current buffer being filled */
size_t maxsamples; /* Size of the current buffer (in 32-bit words) */
volatile size_t nsamples; /* Number of samples currently buffered */
volatile bool first; /* The first random number must be handled differently */
};
/****************************************************************************
* Private Data
****************************************************************************/
static struct trng_dev_s g_trngdev;
static const struct file_operations g_trngops =
{
NULL, /* open */
NULL, /* close */
sam_read, /* read */
NULL, /* write */
NULL, /* seek */
NULL, /* ioctl */
NULL /* poll */
};
/****************************************************************************
* Private functions
****************************************************************************/
/****************************************************************************
* Name: sam_interrupt
*
* Description:
* The TRNG interrupt handler
*
* Input Parameters:
*
* Returned Value:
*
*
****************************************************************************/
static int sam_interrupt(int irq, void *context, FAR void *arg)
{
uint32_t odata;
/* Loop where there are samples available to be read and/or until the user
* buffer is filled. Each sample requires only 84 clocks it is likely
* that we will loop here.
*/
for (; ; )
{
/* Read the random sample (before checking DATRDY -- but probably not
* necessary)
*/
odata = getreg32(SAM_TRNG_ODATA);
/* Verify that sample data is available (DATARDY is cleared when the
* interrupt status register is read)
*/
if ((getreg32(SAM_TRNG_ISR) & TRNG_INT_DATRDY) == 0)
{
/* No? Then return and continue processing on the next
* interrupt.
*/
return OK;
}
/* As required by the FIPS PUB (Federal Information Processing Standard
* Publication) 140-2, the first random number generated after setting
* the RNGEN bit should not be used, but saved for comparison with the
* next generated random number. Each subsequent generated random
* number has to be compared with the previously generated number. The
* test fails if any two compared numbers are equal (continuous random
* number generator test).
*/
if (g_trngdev.nsamples == 0)
{
/* This is the first sample we have taken. Save it for subsequent
* comparison.
*/
g_trngdev.samples[0] = odata;
g_trngdev.nsamples = 1;
continue;
}
/* This is not the first sample. Check if the new sample differs from
* the preceding sample.
*/
else if (odata == g_trngdev.samples[g_trngdev.nsamples - 1])
{
/* Two samples with the same value. Discard this one and try
* again.
*/
continue;
}
/* This sample differs from the previous value. Have we discarded the
* first sample yet?
*/
if (g_trngdev.first)
{
/* No, discard it now by replacing it with the new sample */
g_trngdev.samples[0] = odata;
g_trngdev.nsamples = 1;
g_trngdev.first = false;
}
/* Yes.. the first sample has been discarded */
else
{
/* Add the new random number to the buffer */
g_trngdev.samples[g_trngdev.nsamples] = odata;
g_trngdev.nsamples++;
}
/* Have all of the requested samples been saved? */
if (g_trngdev.nsamples == g_trngdev.maxsamples)
{
/* Yes.. disable any further interrupts */
putreg32(TRNG_INT_DATRDY, SAM_TRNG_IDR);
/* Disable the TRNG */
putreg32(TRNG_CR_DISABLE | TRNG_CR_KEY, SAM_TRNG_CR);
/* And wakeup the waiting read thread. */
nxsem_post(&g_trngdev.waitsem);
return OK;
}
}
}
/****************************************************************************
* Name: sam_read
*
* Description:
* This is the standard, NuttX character driver read method
*
* Input Parameters:
* filep - The VFS file instance
* buffer - Buffer in which to return the random samples
* buflen - The length of the buffer
*
* Returned Value:
*
****************************************************************************/
static ssize_t sam_read(struct file *filep, char *buffer, size_t buflen)
{
ssize_t retval;
int ret;
finfo("buffer=%p buflen=%d\n", buffer, (int)buflen);
/* Get exclusive access to the TRNG hardware */
ret = nxsem_wait(&g_trngdev.exclsem);
if (ret < 0)
{
return ret;
}
/* Save the buffer information. */
DEBUGASSERT(((uintptr_t)buffer & 3) == 0);
g_trngdev.samples = (uint32_t *)buffer;
g_trngdev.maxsamples = buflen >> 2;
g_trngdev.nsamples = 0;
g_trngdev.first = true;
/* Enable the TRNG */
putreg32(TRNG_CR_ENABLE | TRNG_CR_KEY, SAM_TRNG_CR);
/* Clear any pending TRNG interrupts by reading the interrupt status
* register
*/
getreg32(SAM_TRNG_ISR);
/* Enable TRNG interrupts */
putreg32(TRNG_INT_DATRDY, SAM_TRNG_IER);
/* Wait until the buffer is filled */
while (g_trngdev.nsamples < g_trngdev.maxsamples)
{
ret = nxsem_wait(&g_trngdev.waitsem);
finfo("Awakened: nsamples=%d maxsamples=%d ret=%d\n",
g_trngdev.nsamples, g_trngdev.maxsamples, ret);
if (ret < 0)
{
/* We must have been awakened by a signal */
if (g_trngdev.nsamples > 0)
{
break;
}
else
{
retval = ret;
goto errout;
}
}
}
/* Success... calculate the number of bytes to return */
retval = g_trngdev.nsamples << 2;
errout:
/* Disable TRNG interrupts */
putreg32(TRNG_INT_DATRDY, SAM_TRNG_IDR);
/* Disable the TRNG */
putreg32(TRNG_CR_DISABLE | TRNG_CR_KEY, SAM_TRNG_CR);
/* Release our lock on the TRNG hardware */
nxsem_post(&g_trngdev.exclsem);
finfo("Return %d\n", (int)retval);
return retval;
}
/****************************************************************************
* Name: sam_rng_initialize
*
* Description:
* Initialize the TRNG hardware.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static int sam_rng_initialize(void)
{
int ret;
finfo("Initializing TRNG hardware\n");
/* Initialize the device structure */
memset(&g_trngdev, 0, sizeof(struct trng_dev_s));
/* Initialize semphores */
nxsem_init(&g_trngdev.exclsem, 0, 1);
nxsem_init(&g_trngdev.waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&g_trngdev.waitsem, SEM_PRIO_NONE);
/* Enable clocking to the TRNG */
sam_trng_enableclk();
/* Initialize the TRNG interrupt */
ret = irq_attach(SAM_IRQ_TRNG, sam_interrupt, NULL);
if (ret < 0)
{
ferr("ERROR: Failed to attach to IRQ%d\n", SAM_IRQ_TRNG);
return ret;
}
/* Disable the interrupts at the TRNG */
putreg32(TRNG_INT_DATRDY, SAM_TRNG_IDR);
/* Disable the TRNG */
putreg32(TRNG_CR_DISABLE | TRNG_CR_KEY, SAM_TRNG_CR);
/* Enable the TRNG interrupt at the AIC */
up_enable_irq(SAM_IRQ_TRNG);
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: devrandom_register
*
* Description:
* Initialize the TRNG hardware and register the /dev/random driver.
* Must be called BEFORE devurandom_register.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_DEV_RANDOM
void devrandom_register(void)
{
int ret;
ret = sam_rng_initialize();
if (ret >= 0)
{
ret = register_driver("/dev/random", &g_trngops, 0644, NULL);
if (ret < 0)
{
ferr("ERROR: Failed to register /dev/random\n");
}
}
}
#endif
/****************************************************************************
* Name: devurandom_register
*
* Description:
* Register /dev/urandom
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_DEV_URANDOM_ARCH
void devurandom_register(void)
{
int ret;
#ifndef CONFIG_DEV_RANDOM
ret = sam_rng_initialize();
if (ret >= 0)
#endif
{
ret = register_driver("/dev/urandom", &g_trngops, 0644, NULL);
if (ret < 0)
{
ferr("ERROR: Failed to register /dev/urandom\n");
}
}
}
#endif
#endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */
#endif /* CONFIG_SAMA5_TRNG */

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/****************************************************************************
* arch/arm/src/sama5/sam_trng.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_TRNG_H
#define __ARCH_ARM_SRC_SAMA5_SAM_TRNG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_trng.h"
#if defined(CONFIG_DEV_RANDOM) && defined(CONFIG_SAMA5_TRNG)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_DEV_RANDOM && CONFIG_SAMA5_TRNG */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_TRNG_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_tsd.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_TSD_H
#define __ARCH_ARM_SRC_SAMA5_SAM_TSD_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/sam_adc.h"
#if defined(CONFIG_SAMA5_ADC) && defined(CONFIG_SAMA5_TSD)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#ifdef CONFIG_SAMA_TSD_RXP
# define CONFIG_SAMA_TSD_RXP 6
#endif
/* Touchscreen interrupt event sets
*
* ADC_INT_XRDY TSD Measure XPOS Ready Interrupt
* ADC_INT_YRDY TSD Measure YPOS Ready Interrupt
* ADC_INT_PRDY TSD Measure Pressure Ready Interrupt
* ADC_INT_PEN Pen Contact Interrupt
* ADC_INT_NOPEN No Pen Contact Interrupt
* ADC_SR_PENS Pen detect Status (Not an interrupt)
*/
#define ADC_TSD_CMNINTS (ADC_INT_XRDY | ADC_INT_YRDY | ADC_INT_PRDY | ADC_INT_NOPEN)
#define ADC_TSD_ALLINTS (ADC_TSD_CMNINTS | ADC_INT_PEN)
#define ADC_TSD_ALLSTATUS (ADC_TSD_ALLINTS | ADC_SR_PENS)
#define ADC_TSD_RELEASEINTS ADC_TSD_CMNINTS
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_tsd_register
*
* Description:
* Configure the SAMA5 touchscreen. This will register the driver as
* /dev/inputN where N is the minor device number
*
* Input Parameters:
* dev - The ADC device handle received from sam_adc_initialize()
* minor - The input device minor number
*
* Returned Value:
* Zero is returned on success. Otherwise, a negated errno value is
* returned to indicate the nature of the failure.
*
****************************************************************************/
struct sam_adc_s;
int sam_tsd_register(FAR struct sam_adc_s *adc, int minor);
/****************************************************************************
* Interfaces exported from the touchscreen to the ADC driver
****************************************************************************/
/****************************************************************************
* Name: sam_tsd_interrupt
*
* Description:
* Handles ADC interrupts associated with touchscreen channels
*
* Input Parameters:
* pending - Current set of pending interrupts being handled
*
* Returned Value:
* None
*
****************************************************************************/
void sam_tsd_interrupt(uint32_t pending);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* CONFIG_SAMA5_ADC && CONFIG_SAMA5_TSD */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_TSD_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_twi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_TWI_H
#define __ARCH_ARM_SRC_SAMA5_SAM_TWI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/i2c/i2c_master.h>
#include "hardware/sam_twi.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_i2cbus_initialize
*
* Description:
* Initialize the selected I2C port. And return a unique instance of struct
* struct i2c_master_s. This function may be called to obtain multiple
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
* Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
* Valid I2C device structure reference on success; a NULL on failure
*
****************************************************************************/
FAR struct i2c_master_s *sam_i2cbus_initialize(int port);
/****************************************************************************
* Name: sam_i2cbus_uninitialize
*
* Description:
* De-initialize the selected I2C port, and power down the device.
*
* Input Parameters:
* Device structure as returned by the sam_i2cbus_initialize()
*
* Returned Value:
* OK on success, ERROR when internal reference count mismatch or dev
* points to invalid hardware device.
*
****************************************************************************/
int sam_i2cbus_uninitialize(FAR struct i2c_master_s *dev);
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_TWI_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_udphs.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_UDPHS_H
#define __ARCH_ARM_SRC_SAMA5_SAM_UDPHS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/usb/usbdev.h>
#include <stdint.h>
#include "chip.h"
#include "hardware/sam_udphs.h"
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: sam_usbsuspend
*
* Description:
* Board logic must provide the sam_usbsuspend logic if the USBDEV driver
* is used. This function is called whenever the USB enters or leaves
* suspend mode. This is an opportunity for the board logic to shutdown
* clocks, power, etc. while the USB is suspended.
*
****************************************************************************/
void sam_usbsuspend(FAR struct usbdev_s *dev, bool resume);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_UDPHS_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_usbhost.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include <nuttx/usb/usbhost_trace.h>
#include "sam_usbhost.h"
#ifdef HAVE_USBHOST_TRACE
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define TR_OHCI false
#define TR_EHCI true
#define TR_FMT1 false
#define TR_FMT2 true
#define TRENTRY(id,ehci,fmt1,string) {string}
#ifndef NULL
# define NULL ((FAR void *)0)
#endif
/****************************************************************************
* Private Types
****************************************************************************/
struct sam_usbhost_trace_s
{
#if 0
uint16_t id;
bool ehci;
bool fmt2;
#endif
FAR const char *string;
};
/****************************************************************************
* Private Data
****************************************************************************/
static const struct sam_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] =
{
#ifdef CONFIG_SAMA5_OHCI
TRENTRY(OHCI_TRACE1_DEVDISCONN,
TR_OHCI, TR_FMT1,
"OHCI ERROR: RHport%d Device disconnected\n"),
TRENTRY(OHCI_TRACE1_INTRUNRECOVERABLE,
TR_OHCI, TR_FMT1,
"OHCI ERROR: Unrecoverable error. pending: %06x\n"),
TRENTRY(OHCI_TRACE1_INTRUNHANDLED,
TR_OHCI, TR_FMT1,
"OHCI ERROR: Unhandled interrupts pending: %06x\n"),
TRENTRY(OHCI_TRACE1_EPLISTALLOC_FAILED,
TR_OHCI, TR_FMT1,
"OHCI ERROR: Failed to allocate EP list\n"),
TRENTRY(OHCI_TRACE1_EDALLOC_FAILED,
TR_OHCI, TR_FMT1,
"OHCI ERROR: Failed to allocate ED\n"),
TRENTRY(OHCI_TRACE1_TDALLOC_FAILED,
TR_OHCI, TR_FMT1,
"OHCI ERROR: Failed to allocate TD\n"),
TRENTRY(OHCI_TRACE1_IRQATTACH,
TR_OHCI, TR_FMT1,
"OHCI ERROR: Failed to attach IRQ%d\n"),
#ifdef CONFIG_USBHOST_ASYNCH
TRENTRY(OHCI_TRACE1_BADTDSTATUS,
TR_OHCI, TR_FMT1,
"OHCI ERROR: Bad asynch TD completion status: %d\n"),
#endif
#ifdef HAVE_USBHOST_TRACE_VERBOSE
TRENTRY(OHCI_VTRACE1_PHYSED,
TR_OHCI, TR_FMT1,
"OHCI physed: %06x\n"),
TRENTRY(OHCI_VTRACE1_VIRTED,
TR_OHCI, TR_FMT1,
"OHCI ed: %06x\n"),
TRENTRY(OHCI_VTRACE1_CSC,
TR_OHCI, TR_FMT1,
"OHCI Connect Status Change, RHSTATUS: %06x\n"),
TRENTRY(OHCI_VTRACE1_DRWE,
TR_OHCI, TR_FMT1,
"OHCI DRWE: Remote wake-up, RHSTATUS: %06x\n"),
TRENTRY(OHCI_VTRACE1_ALREADYCONN,
TR_OHCI, TR_FMT1,
"OHCI Already connected, RHPORTST: %06x\n"),
TRENTRY(OHCI_VTRACE1_SPEED,
TR_OHCI, TR_FMT1,
"OHCI Port speed: %d\n"),
TRENTRY(OHCI_VTRACE1_ALREADYDISCONN,
TR_OHCI, TR_FMT1,
"OHCI Already disconnected, RHPORTST: %06x\n"),
TRENTRY(OHCI_VTRACE1_RHSC,
TR_OHCI, TR_FMT1,
"OHCI Root Hub Status Change. Pending: %06x\n"),
TRENTRY(OHCI_VTRACE1_WDHINTR,
TR_OHCI, TR_FMT1,
"OHCI Writeback Done Head interrupt. Pending: %06x\n"),
TRENTRY(OHCI_VTRACE1_CLASSENUM,
TR_OHCI, TR_FMT1,
"OHCI Hub port %d: Enumerate device\n"),
TRENTRY(OHCI_VTRACE1_ENUMDISCONN,
TR_OHCI, TR_FMT1,
"OHCI RHport%dNot connected\n"),
TRENTRY(OHCI_VTRACE1_INITIALIZING,
TR_OHCI, TR_FMT1,
"OHCI Initializing Stack\n"),
TRENTRY(OHCI_VTRACE1_INITIALIZED,
TR_OHCI, TR_FMT1,
"OHCI Initialized\n"),
TRENTRY(OHCI_VTRACE1_INTRPENDING,
TR_OHCI, TR_FMT1,
"OHCI Interrupts pending: %06x\n"),
#endif
#endif
#ifdef CONFIG_SAMA5_EHCI
TRENTRY(EHCI_TRACE1_SYSTEMERROR,
TR_EHCI, TR_FMT1,
"EHCI ERROR: System error: %06x\n"),
TRENTRY(EHCI_TRACE1_QTDFOREACH_FAILED,
TR_EHCI, TR_FMT1,
"EHCI ERROR: sam_qtd_foreach failed: %d\n"),
TRENTRY(EHCI_TRACE1_QHALLOC_FAILED,
TR_EHCI, TR_FMT1,
"EHCI ERROR: Failed to allocate a QH\n"),
TRENTRY(EHCI_TRACE1_BUFTOOBIG,
TR_EHCI, TR_FMT1,
"EHCI ERROR: Buffer too big. Remaining %d\n"),
TRENTRY(EHCI_TRACE1_REQQTDALLOC_FAILED,
TR_EHCI, TR_FMT1,
"EHCI ERROR: Failed to allocate request qTD"),
TRENTRY(EHCI_TRACE1_ADDBPL_FAILED,
TR_EHCI, TR_FMT1,
"EHCI ERROR: sam_qtd_addbpl failed: %d\n"),
TRENTRY(EHCI_TRACE1_DATAQTDALLOC_FAILED,
TR_EHCI, TR_FMT1,
"EHCI ERROR: Failed to allocate data buffer qTD, 0"),
TRENTRY(EHCI_TRACE1_DEVDISCONNECTED,
TR_EHCI, TR_FMT1,
"EHCI ERROR: Device disconnected %d\n"),
TRENTRY(EHCI_TRACE1_QHCREATE_FAILED,
TR_EHCI, TR_FMT1,
"EHCI ERROR: sam_qh_create failed\n"),
TRENTRY(EHCI_TRACE1_QTDSETUP_FAILED,
TR_EHCI, TR_FMT1,
"EHCI ERROR: sam_qtd_setupphase failed\n"),
TRENTRY(EHCI_TRACE1_QTDDATA_FAILED,
TR_EHCI, TR_FMT1,
"EHCI ERROR: sam_qtd_dataphase failed\n"),
TRENTRY(EHCI_TRACE1_QTDSTATUS_FAILED,
TR_EHCI, TR_FMT1,
"EHCI ERROR: sam_qtd_statusphase failed\n"),
TRENTRY(EHCI_TRACE1_TRANSFER_FAILED,
TR_EHCI, TR_FMT1,
"EHCI ERROR: Transfer failed %d\n"),
TRENTRY(EHCI_TRACE1_QHFOREACH_FAILED,
TR_EHCI, TR_FMT1,
"EHCI ERROR: sam_qh_foreach failed: %d\n"),
TRENTRY(EHCI_TRACE1_SYSERR_INTR,
TR_EHCI, TR_FMT1,
"EHCI: Host System Error Interrupt\n"),
TRENTRY(EHCI_TRACE1_USBERR_INTR,
TR_EHCI, TR_FMT1,
"EHCI: USB Error Interrupt (USBERRINT) Interrupt: %06x\n"),
TRENTRY(EHCI_TRACE1_EPALLOC_FAILED,
TR_EHCI, TR_FMT1,
"EHCI ERROR: Failed to allocate EP info structure\n"),
TRENTRY(EHCI_TRACE1_BADXFRTYPE,
TR_EHCI, TR_FMT1,
"EHCI ERROR: Support for transfer type %d not implemented\n"),
TRENTRY(EHCI_TRACE1_HCHALTED_TIMEOUT,
TR_EHCI, TR_FMT1,
"EHCI ERROR: Timed out waiting for HCHalted. USBSTS: %06x\n"),
TRENTRY(EHCI_TRACE1_QHPOOLALLOC_FAILED,
TR_EHCI, TR_FMT1,
"EHCI ERROR: Failed to allocate the QH pool\n"),
TRENTRY(EHCI_TRACE1_QTDPOOLALLOC_FAILED,
TR_EHCI, TR_FMT1,
"EHCI ERROR: Failed to allocate the qTD pool\n"),
TRENTRY(EHCI_TRACE1_PERFLALLOC_FAILED,
TR_EHCI, TR_FMT1,
"EHCI ERROR: Failed to allocate the periodic frame list\n"),
TRENTRY(EHCI_TRACE1_RESET_FAILED,
TR_EHCI, TR_FMT1,
"EHCI ERROR: sam_reset failed: %d\n"),
TRENTRY(EHCI_TRACE1_RUN_FAILED,
TR_EHCI, TR_FMT1,
"EHCI ERROR: EHCI Failed to run: USBSTS=%06x\n"),
TRENTRY(EHCI_TRACE1_IRQATTACH_FAILED,
TR_EHCI, TR_FMT1,
"EHCI ERROR: Failed to attach IRQ%d\n"),
#ifdef HAVE_USBHOST_TRACE_VERBOSE
TRENTRY(EHCI_VTRACE1_PORTSC_CSC,
TR_EHCI, TR_FMT1,
"EHCI Connect Status Change: %06x\n"),
TRENTRY(EHCI_VTRACE1_PORTSC_CONNALREADY,
TR_EHCI, TR_FMT1,
"EHCI Already connected: %06x\n"),
TRENTRY(EHCI_VTRACE1_PORTSC_DISCALREADY,
TR_EHCI, TR_FMT1,
"EHCI Already disconnected: %06x\n"),
TRENTRY(EHCI_VTRACE1_TOPHALF,
TR_EHCI, TR_FMT1,
"EHCI Interrupt: %06x\n"),
TRENTRY(EHCI_VTRACE1_AAINTR,
TR_EHCI, TR_FMT1,
"EHCI Async Advance Interrupt\n"),
TRENTRY(EHCI_VTRACE1_USBINTR,
TR_EHCI, TR_FMT1,
"EHCI USB Interrupt (USBINT) Interrupt: %06x\n"),
TRENTRY(EHCI_VTRACE1_CLASSENUM,
TR_EHCI, TR_FMT1,
"EHCI Hub port %d: Enumerate device\n"),
TRENTRY(EHCI_VTRACE1_ENUM_DISCONN,
TR_EHCI, TR_FMT1,
"EHCI Enumeration not connected\n"),
TRENTRY(EHCI_VTRACE1_INITIALIZING,
TR_EHCI, TR_FMT1,
"EHCI Initializing EHCI Stack\n"),
TRENTRY(EHCI_VTRACE1_HCCPARAMS,
TR_EHCI, TR_FMT1,
"EHCI HCCPARAMS=%06x\n"),
TRENTRY(EHCI_VTRACE1_INIITIALIZED,
TR_EHCI, TR_FMT1,
"EHCI USB EHCI Initialized\n"),
#endif
#endif
};
static const struct sam_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] =
{
#ifdef CONFIG_SAMA5_OHCI
TRENTRY(OHCI_TRACE2_BADTDSTATUS,
TR_OHCI, TR_FMT2,
"OHCI ERROR: RHport%d Bad TD completion status: %d\n"),
TRENTRY(OHCI_TRACE2_WHDTDSTATUS,
TR_OHCI, TR_FMT2,
"OHCI ERROR: WHD Bad TD completion status: %d xfrtype: %d\n"),
TRENTRY(OHCI_TRACE2_EP0ENQUEUE_FAILED,
TR_OHCI, TR_FMT2,
"OHCI ERROR: RHport%d Failed to enqueue EP0: %d\n"),
TRENTRY(OHCI_TRACE2_EDENQUEUE_FAILED,
TR_OHCI, TR_FMT2,
"OHCI ERROR: Failed to queue ED for transfer type %d: %d\n"),
TRENTRY(OHCI_TRACE2_CLASSENUM_FAILED,
TR_OHCI, TR_FMT2,
"OHCI Hub port %d usbhost_enumerate() failed: %d\n"),
#ifdef HAVE_USBHOST_TRACE_VERBOSE
TRENTRY(OHCI_VTRACE2_EP0CONFIG,
TR_OHCI, TR_FMT2,
"OHCI EP0 configure speed=%d funcaddr=%d\n"),
TRENTRY(OHCI_VTRACE2_INTERVAL,
TR_OHCI, TR_FMT2,
"OHCI interval: %d->%d\n"),
TRENTRY(OHCI_VTRACE2_MININTERVAL,
TR_OHCI, TR_FMT2,
"OHCI MIN interval: %d offset: %d\n"),
TRENTRY(OHCI_VTRACE2_RHPORTST,
TR_OHCI, TR_FMT2,
"OHCI RHPORTST%d: %04x\n"),
TRENTRY(OHCI_VTRACE2_CONNECTED,
TR_OHCI, TR_FMT2,
"OHCI RHPort%d connected, rhswait: %d\n"),
TRENTRY(OHCI_VTRACE2_DISCONNECTED,
TR_OHCI, TR_FMT2,
"OHCI RHPort%d disconnected, rhswait: %d\n"),
TRENTRY(OHCI_VTRACE2_WAKEUP,
TR_OHCI, TR_FMT2,
"OHCI RHPort%d connected: %d\n"),
TRENTRY(OHCI_VTRACE2_EP0CTRLED,
TR_OHCI, TR_FMT2,
"OHCI RHPort%d EP0 CTRL: %04x\n"),
TRENTRY(OHCI_VTRACE2_EPALLOC,
TR_OHCI, TR_FMT2,
"OHCI EP%d CTRL: %04x\n"),
TRENTRY(OHCI_VTRACE2_CTRLIN,
TR_OHCI, TR_FMT2,
"OHCI CTRLIN RHPort%d req: %02x\n"),
TRENTRY(OHCI_VTRACE2_CTRLOUT,
TR_OHCI, TR_FMT2,
"OHCI CTRLOUT RHPort%d req: %02x\n"),
TRENTRY(OHCI_VTRACE2_TRANSFER,
TR_OHCI, TR_FMT2,
"OHCI EP%d buflen: %d\n"),
TRENTRY(OHCI_VTRACE2_INITCONNECTED,
TR_OHCI, TR_FMT2,
"OHCI RHPort%d Device connected: %d\n"),
#ifdef CONFIG_USBHOST_HUB
TRENTRY(OHCI_VTRACE2_HUBWAKEUP,
TR_OHCI, TR_FMT2,
"OHCI Hub Port%d connected: %d\n"),
#endif
#endif
#endif
#ifdef CONFIG_SAMA5_EHCI
TRENTRY(EHCI_TRACE2_EPSTALLED,
TR_EHCI, TR_FMT2,
"EHCI EP%d Stalled: TOKEN=%04x\n"),
TRENTRY(EHCI_TRACE2_EPIOERROR,
TR_EHCI, TR_FMT2,
"EHCI ERROR: EP%d TOKEN=%04x\n"),
TRENTRY(EHCI_TRACE2_CLASSENUM_FAILED,
TR_EHCI, TR_FMT2,
"EHCI Hub port %d usbhost_enumerate() failed: %d\n"),
#ifdef HAVE_USBHOST_TRACE_VERBOSE
TRENTRY(EHCI_VTRACE2_EP0CONFIG,
TR_EHCI, TR_FMT2,
"EHCI EP0 configure speed=%d funcaddr=%d\n"),
TRENTRY(EHCI_VTRACE2_ASYNCXFR,
TR_EHCI, TR_FMT2,
"EHCI Async transfer EP%d buflen=%d\n"),
TRENTRY(EHCI_VTRACE2_INTRXFR,
TR_EHCI, TR_FMT2,
"EHCI Intr Transfer EP%d buflen=%d\n"),
TRENTRY(EHCI_VTRACE2_IOCCHECK,
TR_EHCI, TR_FMT2,
"EHCI IOC EP%d TOKEN=%04x\n"),
TRENTRY(EHCI_VTRACE2_PORTSC,
TR_EHCI, TR_FMT2,
"EHCI PORTSC%d: %04x\n"),
TRENTRY(EHCI_VTRACE2_PORTSC_CONNECTED,
TR_EHCI, TR_FMT2,
"EHCI RHPort%d connected, pscwait: %d\n"),
TRENTRY(EHCI_VTRACE2_PORTSC_DISCONND,
TR_EHCI, TR_FMT2,
"EHCI RHport%d disconnected, pscwait: %d\n"),
TRENTRY(EHCI_VTRACE2_MONWAKEUP,
TR_EHCI, TR_FMT2,
"EHCI Hub port%d connected: %d\n"),
TRENTRY(EHCI_VTRACE2_EPALLOC,
TR_EHCI, TR_FMT2,
"EHCI EPALLOC: EP%d TYPE=%d\n"),
TRENTRY(EHCI_VTRACE2_CTRLINOUT,
TR_EHCI, TR_FMT2,
"EHCI CTRLIN/OUT: RHPort%d req: %02x\n"),
TRENTRY(EHCI_VTRACE2_HCIVERSION,
TR_EHCI, TR_FMT2,
"EHCI HCIVERSION %x.%02x\n"),
TRENTRY(EHCI_VTRACE2_HCSPARAMS,
TR_EHCI, TR_FMT2,
"EHCI nports=%d, HCSPARAMS=%04x\n"),
#endif
#endif
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: usbhost_trformat1 and usbhost_trformat2
*
* Description:
* This interface must be provided by platform specific logic that knows
* the HCDs encoding of USB trace data.
*
* Given an 9-bit index, return a format string suitable for use with, say,
* printf. The returned format is expected to handle two unsigned integer
* values.
*
****************************************************************************/
FAR const char *usbhost_trformat1(uint16_t id)
{
int ndx = TRACE1_INDEX(id);
if (ndx < TRACE1_NSTRINGS)
{
return g_trace1[ndx].string;
}
return NULL;
}
FAR const char *usbhost_trformat2(uint16_t id)
{
int ndx = TRACE2_INDEX(id);
if (ndx < TRACE2_NSTRINGS)
{
return g_trace2[ndx].string;
}
return NULL;
}
#endif /* HAVE_USBHOST_TRACE */

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/****************************************************************************
* arch/arm/src/sama5/sam_usbhost.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_USBHOST_H
#define __ARCH_ARM_SRC_SAMA5_SAM_USBHOST_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/usb/usbhost_trace.h>
#ifdef CONFIG_USBHOST
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* This is the interface argument for call outs to board-specific functions
* which need to know which USB host interface is being used.
*/
#define SAM_EHCI_IFACE 0
#define SAM_OHCI_IFACE 1
/* This is the interface argument for call outs to board-specific functions
* which need to know which root hub port is being used.
*/
#define SAM_RHPORT1 0
#define SAM_RHPORT2 1
#define SAM_RHPORT3 2
/****************************************************************************
* Public Types
****************************************************************************/
#ifdef HAVE_USBHOST_TRACE
enum usbhost_trace1codes_e
{
__TRACE1_BASEVALUE = 0, /* This will force the first value to be 1 */
#ifdef CONFIG_SAMA5_OHCI
OHCI_TRACE1_DEVDISCONN, /* OHCI ERROR: RHport Device disconnected */
OHCI_TRACE1_INTRUNRECOVERABLE, /* OHCI ERROR: Unrecoverable error */
OHCI_TRACE1_INTRUNHANDLED, /* OHCI ERROR: Unhandled interrupts */
OHCI_TRACE1_EPLISTALLOC_FAILED, /* OHCI ERROR: Failed to allocate EP list */
OHCI_TRACE1_EDALLOC_FAILED, /* OHCI ERROR: Failed to allocate ED */
OHCI_TRACE1_TDALLOC_FAILED, /* OHCI ERROR: Failed to allocate TD */
OHCI_TRACE1_IRQATTACH, /* OHCI ERROR: Failed to attach IRQ */
#ifdef CONFIG_USBHOST_ASYNCH
OHCI_TRACE1_BADTDSTATUS, /* OHCI ERROR: Bad asynch TD completion status */
#endif
#ifdef HAVE_USBHOST_TRACE_VERBOSE
OHCI_VTRACE1_PHYSED, /* OHCI physed */
OHCI_VTRACE1_VIRTED, /* OHCI ed */
OHCI_VTRACE1_CSC, /* OHCI Connect Status Change */
OHCI_VTRACE1_DRWE, /* OHCI DRWE: Remote wake-up */
OHCI_VTRACE1_ALREADYCONN, /* OHCI Already connected */
OHCI_VTRACE1_SPEED, /* OHCI Low speed */
OHCI_VTRACE1_ALREADYDISCONN, /* OHCI Already disconnected */
OHCI_VTRACE1_RHSC, /* OHCI Root Hub Status Change */
OHCI_VTRACE1_WDHINTR, /* OHCI Writeback Done Head interrupt */
OHCI_VTRACE1_CLASSENUM, /* OHCI Enumerate the device */
OHCI_VTRACE1_ENUMDISCONN, /* OHCI RHport Not connected */
OHCI_VTRACE1_INITIALIZING, /* OHCI Initializing Stack */
OHCI_VTRACE1_INITIALIZED, /* OHCI Initialized */
OHCI_VTRACE1_INTRPENDING, /* OHCI Interrupts pending */
#endif
#endif
#ifdef CONFIG_SAMA5_EHCI
EHCI_TRACE1_SYSTEMERROR, /* EHCI ERROR: System error */
EHCI_TRACE1_QTDFOREACH_FAILED, /* EHCI ERROR: sam_qtd_foreach failed */
EHCI_TRACE1_QHALLOC_FAILED, /* EHCI ERROR: Failed to allocate a QH */
EHCI_TRACE1_BUFTOOBIG, /* EHCI ERROR: Buffer too big */
EHCI_TRACE1_REQQTDALLOC_FAILED, /* EHCI ERROR: Failed to allocate request qTD */
EHCI_TRACE1_ADDBPL_FAILED, /* EHCI ERROR: sam_qtd_addbpl failed */
EHCI_TRACE1_DATAQTDALLOC_FAILED, /* EHCI ERROR: Failed to allocate data buffer qTD */
EHCI_TRACE1_DEVDISCONNECTED, /* EHCI ERROR: Device disconnected */
EHCI_TRACE1_QHCREATE_FAILED, /* EHCI ERROR: sam_qh_create failed */
EHCI_TRACE1_QTDSETUP_FAILED, /* EHCI ERROR: sam_qtd_setupphase failed */
EHCI_TRACE1_QTDDATA_FAILED, /* EHCI ERROR: sam_qtd_dataphase failed */
EHCI_TRACE1_QTDSTATUS_FAILED, /* EHCI ERROR: sam_qtd_statusphase failed */
EHCI_TRACE1_TRANSFER_FAILED, /* EHCI ERROR: Transfer failed */
EHCI_TRACE1_QHFOREACH_FAILED, /* EHCI ERROR: sam_qh_foreach failed: */
EHCI_TRACE1_SYSERR_INTR, /* EHCI: Host System Error Interrupt */
EHCI_TRACE1_USBERR_INTR, /* EHCI: USB Error Interrupt (USBERRINT) Interrupt */
EHCI_TRACE1_EPALLOC_FAILED, /* EHCI ERROR: Failed to allocate EP info structure */
EHCI_TRACE1_BADXFRTYPE, /* EHCI ERROR: Support for transfer type not implemented */
EHCI_TRACE1_HCHALTED_TIMEOUT, /* EHCI ERROR: Timed out waiting for HCHalted */
EHCI_TRACE1_QHPOOLALLOC_FAILED, /* EHCI ERROR: Failed to allocate the QH pool */
EHCI_TRACE1_QTDPOOLALLOC_FAILED, /* EHCI ERROR: Failed to allocate the qTD pool */
EHCI_TRACE1_PERFLALLOC_FAILED, /* EHCI ERROR: Failed to allocate the periodic frame list */
EHCI_TRACE1_RESET_FAILED, /* EHCI ERROR: sam_reset failed */
EHCI_TRACE1_RUN_FAILED, /* EHCI ERROR: EHCI Failed to run */
EHCI_TRACE1_IRQATTACH_FAILED, /* EHCI ERROR: Failed to attach IRQ */
#ifdef HAVE_USBHOST_TRACE_VERBOSE
EHCI_VTRACE1_PORTSC_CSC, /* EHCI Connect Status Change */
EHCI_VTRACE1_PORTSC_CONNALREADY, /* EHCI Already connected */
EHCI_VTRACE1_PORTSC_DISCALREADY, /* EHCI Already disconnected */
EHCI_VTRACE1_TOPHALF, /* EHCI Interrupt top half */
EHCI_VTRACE1_AAINTR, /* EHCI Async Advance Interrupt */
EHCI_VTRACE1_USBINTR, /* EHCI USB Interrupt (USBINT) Interrupt */
EHCI_VTRACE1_CLASSENUM, /* EHCI Enumerate the device */
EHCI_VTRACE1_ENUM_DISCONN, /* EHCI Enumeration not connected */
EHCI_VTRACE1_INITIALIZING, /* EHCI Initializing EHCI Stack */
EHCI_VTRACE1_HCCPARAMS, /* EHCI HCCPARAMS */
EHCI_VTRACE1_INIITIALIZED, /* EHCI USB EHCI Initialized */
#endif
#endif
__TRACE1_NSTRINGS, /* Separates the format 1 from the format 2 strings */
#ifdef CONFIG_SAMA5_OHCI
OHCI_TRACE2_BADTDSTATUS, /* OHCI ERROR: RHport Bad TD completion status */
OHCI_TRACE2_WHDTDSTATUS, /* OHCI ERROR: WDH Bad TD completion status */
OHCI_TRACE2_EP0ENQUEUE_FAILED, /* OHCI ERROR: RHport Failed to enqueue EP0 */
OHCI_TRACE2_EDENQUEUE_FAILED, /* OHCI ERROR: Failed to queue ED for transfer type */
OHCI_TRACE2_CLASSENUM_FAILED, /* OHCI usbhost_enumerate() failed */
#ifdef HAVE_USBHOST_TRACE_VERBOSE
OHCI_VTRACE2_EP0CONFIG, /* OHCI EP0 configuration */
OHCI_VTRACE2_INTERVAL, /* OHCI interval */
OHCI_VTRACE2_MININTERVAL, /* OHCI MIN interval/offset */
OHCI_VTRACE2_RHPORTST, /* OHCI RHPORTST */
OHCI_VTRACE2_CONNECTED, /* OHCI RHPort connected */
OHCI_VTRACE2_DISCONNECTED, /* OHCI RHPort disconnected */
OHCI_VTRACE2_WAKEUP, /* OHCI RHPort connected wakeup */
OHCI_VTRACE2_EP0CTRLED, /* OHCI RHPort EP0 CTRL */
OHCI_VTRACE2_EPALLOC, /* OHCI EP CTRL */
OHCI_VTRACE2_CTRLIN, /* OHCI CTRLIN */
OHCI_VTRACE2_CTRLOUT, /* OHCI CTRLOUT */
OHCI_VTRACE2_TRANSFER, /* OHCI EP buflen */
OHCI_VTRACE2_INITCONNECTED, /* OHCI RHPort Device connected */
#ifdef CONFIG_USBHOST_HUB
OHCI_VTRACE2_HUBWAKEUP, /* EHCI Hub Port connected wakeup */
#endif
#endif
#endif
#ifdef CONFIG_SAMA5_EHCI
EHCI_TRACE2_EPSTALLED, /* EHCI EP Stalled */
EHCI_TRACE2_EPIOERROR, /* EHCI ERROR: EP TOKEN */
EHCI_TRACE2_CLASSENUM_FAILED, /* EHCI usbhost_enumerate() failed */
#ifdef HAVE_USBHOST_TRACE_VERBOSE
EHCI_VTRACE2_EP0CONFIG, /* EHCI EP0 configuration */
EHCI_VTRACE2_ASYNCXFR, /* EHCI Async transfer */
EHCI_VTRACE2_INTRXFR, /* EHCI Interrupt Transfer */
EHCI_VTRACE2_IOCCHECK, /* EHCI IOC */
EHCI_VTRACE2_PORTSC, /* EHCI PORTSC */
EHCI_VTRACE2_PORTSC_CONNECTED, /* EHCI RHPort connected */
EHCI_VTRACE2_PORTSC_DISCONND, /* EHCI RHport disconnected */
EHCI_VTRACE2_MONWAKEUP, /* EHCI RHPort connected wakeup */
EHCI_VTRACE2_EPALLOC, /* EHCI EPALLOC */
EHCI_VTRACE2_CTRLINOUT, /* EHCI CTRLIN/OUT */
EHCI_VTRACE2_HCIVERSION, /* EHCI HCIVERSION */
EHCI_VTRACE2_HCSPARAMS, /* EHCI HCSPARAMS */
#endif
#endif
__TRACE2_NSTRINGS /* Total number of enumeration values */
};
# define TRACE1_FIRST ((int)__TRACE1_BASEVALUE + 1)
# define TRACE1_INDEX(id) ((int)(id) - TRACE1_FIRST)
# define TRACE1_NSTRINGS TRACE1_INDEX(__TRACE1_NSTRINGS)
# define TRACE2_FIRST ((int)__TRACE1_NSTRINGS + 1)
# define TRACE2_INDEX(id) ((int)(id) - TRACE2_FIRST)
# define TRACE2_NSTRINGS TRACE2_INDEX(__TRACE2_NSTRINGS)
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_ohci_initialize
*
* Description:
* Initialize USB OHCI host controller hardware.
*
* Input Parameters:
* controller -- If the device supports more than one USB OHCI interface,
* then this identifies which controller is being initializeed.
* Normally, this is just zero.
*
* Returned Value:
* And instance of the USB host interface. The controlling task should
* use this interface to (1) call the wait() method to wait for a device
* to be connected, and (2) call the enumerate() method to bind the device
* to a class driver.
*
* Assumptions:
* - This function should called in the initialization sequence in order
* to initialize the USB device functionality.
* - Class drivers should be initialized prior to calling this function.
* Otherwise, there is a race condition if the device is already connected.
*
****************************************************************************/
#ifdef CONFIG_SAMA5_OHCI
struct usbhost_connection_s;
FAR struct usbhost_connection_s *sam_ohci_initialize(int controller);
#endif
/****************************************************************************
* Name: sam_ohci_tophalf
*
* Description:
* OHCI "Top Half" interrupt handler. If both EHCI and OHCI are enabled,
* then EHCI will manage the common UHPHS interrupt and will forward the
* interrupt event to this function.
*
****************************************************************************/
#ifdef CONFIG_SAMA5_OHCI
int sam_ohci_tophalf(int irq, FAR void *context, FAR void *arg);
#endif
/****************************************************************************
* Name: sam_ehci_initialize
*
* Description:
* Initialize USB EHCI host controller hardware.
*
* Input Parameters:
* controller -- If the device supports more than one EHCI interface, then
* this identifies which controller is being initializeed. Normally,
* this is just zero.
*
* Returned Value:
* And instance of the USB host interface. The controlling task should
* use this interface to (1) call the wait() method to wait for a device
* to be connected, and (2) call the enumerate() method to bind the device
* to a class driver.
*
* Assumptions:
* - This function should called in the initialization sequence in order
* to initialize the USB device functionality.
* - Class drivers should be initialized prior to calling this function.
* Otherwise, there is a race condition if the device is already connected.
*
****************************************************************************/
#ifdef CONFIG_SAMA5_EHCI
struct usbhost_connection_s;
FAR struct usbhost_connection_s *sam_ehci_initialize(int controller);
#endif
/****************************************************************************
* Name: sam_usbhost_vbusdrive
*
* Description:
* Enable/disable driving of VBUS 5V output. This function must be
* provided by each platform that implements the OHCI or EHCI host
* interface
*
* Input Parameters:
* rhport - Selects root hub port to be powered host interface.
* See SAM_RHPORT_*definitions above.
* enable - true: enable VBUS power; false: disable VBUS power
*
* Returned Value:
* None
*
****************************************************************************/
void sam_usbhost_vbusdrive(int rhport, bool enable);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_USBHOST */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_USBHOST_H */

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/****************************************************************************
* arch/arm/src/sama5/sam_wdt.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <stdint.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/timers/watchdog.h>
#include <arch/board/board.h>
#include "arm_arch.h"
#include "sam_wdt.h"
#if defined(CONFIG_WATCHDOG) && defined(CONFIG_SAMA5_WDT)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#ifndef CONFIG_DEBUG_WATCHDOG_INFO
# undef CONFIG_SAMA5_WDT_REGDEBUG
#endif
/* The Watchdog Timer uses the Slow Clock divided by 128 to establish the
* maximum Watchdog period to be 16 seconds (with a typical Slow Clock of
* 32768 kHz).
*/
#ifndef BOARD_SCLK_FREQUENCY
# define BOARD_SCLK_FREQUENCY 32768
#endif
#define WDT_FREQUENCY (BOARD_SCLK_FREQUENCY / 128)
/* At 32768Hz, the maximum timeout value will be:
*
* 4096 / WDT_FREQUENCY = 256 seconds or 16,000 milliseconds
*
* And the minimum (non-zero) timeout would be:
*
* 1 / WDT_FREQUENCY = 3.9 milliseconds
*/
#define WDT_MINTIMEOUT ((1000 + WDT_FREQUENCY - 1) / WDT_FREQUENCY)
#define WDT_MAXTIMEOUT ((4096 * 1000) / WDT_FREQUENCY)
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure provides the private representation of the "lower-half"
* driver state structure. This structure must be cast-compatible with the
* well-known watchdog_lowerhalf_s structure.
*/
struct sam_lowerhalf_s
{
FAR const struct watchdog_ops_s *ops; /* Lower half operations */
#ifdef CONFIG_SAMA5_WDT_INTERRUPT
xcpt_t handler; /* Current WDT interrupt handler */
#endif
uint32_t timeout; /* The actual timeout value (milliseconds) */
uint16_t reload; /* The 12-bit watchdog reload value */
bool started; /* The timer has been started */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Register operations ******************************************************/
#ifdef CONFIG_SAMA5_WDT_REGDEBUG
static uint32_t sam_getreg(uintptr_t regaddr);
static void sam_putreg(uint32_t regval, uintptr_t regaddr);
#else
# define sam_getreg(regaddr) getreg32(regaddr)
# define sam_putreg(regval,regaddr) putreg32(regval,regaddr)
#endif
/* Interrupt handling *******************************************************/
#ifdef CONFIG_SAMA5_WDT_INTERRUPT
static int sam_interrupt(int irq, FAR void *context, FAR void *arg);
#endif
/* "Lower half" driver methods **********************************************/
static int sam_start(FAR struct watchdog_lowerhalf_s *lower);
static int sam_stop(FAR struct watchdog_lowerhalf_s *lower);
static int sam_keepalive(FAR struct watchdog_lowerhalf_s *lower);
static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower,
FAR struct watchdog_status_s *status);
static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower,
uint32_t timeout);
static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower,
xcpt_t handler);
static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
unsigned long arg);
/****************************************************************************
* Private Data
****************************************************************************/
/* "Lower half" driver methods */
static const struct watchdog_ops_s g_wdgops =
{
.start = sam_start,
.stop = sam_stop,
.keepalive = sam_keepalive,
.getstatus = sam_getstatus,
.settimeout = sam_settimeout,
.capture = sam_capture,
.ioctl = sam_ioctl,
};
/* "Lower half" driver state */
static struct sam_lowerhalf_s g_wdtdev;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: sam_getreg
*
* Description:
* Get the contents of an SAMA5 register
*
****************************************************************************/
#ifdef CONFIG_SAMA5_WDT_REGDEBUG
static uint32_t sam_getreg(uintptr_t regaddr)
{
static uint32_t prevaddr = 0;
static uint32_t count = 0;
static uint32_t preval = 0;
/* Read the value from the register */
uint32_t regval = getreg32(regaddr);
/* Is this the same value that we read from the same register last time?
* Are we polling the register? If so, suppress some of the output.
*/
if (regaddr == prevaddr && regval == preval)
{
if (count == 0xffffffff || ++count > 3)
{
if (count == 4)
{
wdinfo("...\n");
}
return regval;
}
}
/* No this is a new address or value */
else
{
/* Did we print "..." for the previous value? */
if (count > 3)
{
/* Yes.. then show how many times the value repeated */
wdinfo("[repeats %d more times]\n", count - 3);
}
/* Save the new address, value, and count */
prevaddr = regaddr;
preval = regval;
count = 1;
}
/* Show the register value read */
wdinfo("%08x->%048\n", regaddr, regval);
return regval;
}
#endif
/****************************************************************************
* Name: sam_putreg
*
* Description:
* Set the contents of an SAMA5 register to a value
*
****************************************************************************/
#ifdef CONFIG_SAMA5_WDT_REGDEBUG
static void sam_putreg(uint32_t regval, uintptr_t regaddr)
{
/* Show the register value being written */
wdinfo("%08x<-%08x\n", regaddr, regval);
/* Write the value */
putreg32(regval, regaddr);
}
#endif
/****************************************************************************
* Name: sam_interrupt
*
* Description:
* WDT early warning interrupt
*
* Input Parameters:
* Usual interrupt handler arguments.
*
* Returned Value:
* Always returns OK.
*
****************************************************************************/
#ifdef CONFIG_SAMA5_WDT_INTERRUPT
static int sam_interrupt(int irq, FAR void *context, FAR void *arg)
{
FAR struct sam_lowerhalf_s *priv = &g_wdtdev;
/* Is there a registered handler? */
if (priv->handler)
{
/* Yes... NOTE: This interrupt service routine (ISR) must reload
* the WDT counter to prevent the reset. Otherwise, we will reset
* upon return.
*/
priv->handler(irq, context);
}
return OK;
}
#endif
/****************************************************************************
* Name: sam_start
*
* Description:
* Start the watchdog timer, resetting the time to the current timeout,
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int sam_start(FAR struct watchdog_lowerhalf_s *lower)
{
FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower;
/* The watchdog timer is enabled or disabled by writing to the MR register.
*
* NOTE:
* The Watchdog Mode Register (WDT_MR) can be written only once. Only
* a processor reset resets it. Writing the WDT_MR register reloads the
* timer with the newly programmed mode parameters.
*/
wdinfo("Entry\n");
return priv->started ? OK : -ENOSYS;
}
/****************************************************************************
* Name: sam_stop
*
* Description:
* Stop the watchdog timer
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int sam_stop(FAR struct watchdog_lowerhalf_s *lower)
{
/* The watchdog timer is enabled or disabled by writing to the MR register.
*
* NOTE:
* The Watchdog Mode Register (WDT_MR) can be written only once. Only
* a processor reset resets it. Writing the WDT_MR register reloads the
* timer with the newly programmed mode parameters.
*/
wdinfo("Entry\n");
return -ENOSYS;
}
/****************************************************************************
* Name: sam_keepalive
*
* Description:
* Reset the watchdog timer to the current timeout value, prevent any
* imminent watchdog timeouts. This is sometimes referred as "pinging"
* the atchdog timer or "petting the dog".
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int sam_keepalive(FAR struct watchdog_lowerhalf_s *lower)
{
wdinfo("Entry\n");
/* Write WDT_CR_WDRSTT to the WDT CR register (along with the KEY value)
* will restart the watchdog timer.
*/
sam_putreg(WDT_CR_WDRSTT | WDT_CR_KEY, SAM_WDT_CR);
return OK;
}
/****************************************************************************
* Name: sam_getstatus
*
* Description:
* Get the current watchdog timer status
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* stawtus - The location to return the watchdog status information.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower,
FAR struct watchdog_status_s *status)
{
FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower;
wdinfo("Entry\n");
DEBUGASSERT(priv);
/* Return the status bit */
status->flags = WDFLAGS_RESET;
if (priv->started)
{
status->flags |= WDFLAGS_ACTIVE;
}
#ifdef CONFIG_SAMA5_WDT_INTERRUPT
if (priv->handler)
{
status->flags |= WDFLAGS_CAPTURE;
}
#endif
/* Return the actual timeout is milliseconds */
status->timeout = priv->timeout;
/* Get the time remaining until the watchdog expires (in milliseconds)
*
* REVISIT: I think this that this information is available.
*/
status->timeleft = 0;
wdinfo("Status :\n");
wdinfo(" flags : %08x\n", status->flags);
wdinfo(" timeout : %d\n", status->timeout);
wdinfo(" timeleft : %d\n", status->timeleft);
return OK;
}
/****************************************************************************
* Name: sam_settimeout
*
* Description:
* Set a new timeout value (and reset the watchdog timer)
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* timeout - The new timeout value in millisecnds.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower,
uint32_t timeout)
{
FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower;
uint32_t reload;
uint32_t regval;
DEBUGASSERT(priv);
wdinfo("Entry: timeout=%d\n", timeout);
/* Can this timeout be represented? */
if (timeout < WDT_MINTIMEOUT || timeout >= WDT_MAXTIMEOUT)
{
wderr("ERROR: Cannot represent timeout: %d < %d > %d\n",
WDT_MINTIMEOUT, timeout, WDT_MAXTIMEOUT);
return -ERANGE;
}
/* Calculate the reload value to achiee this (approximate) timeout.
*
* Examples with WDT_FREQUENCY = 32768 / 128 = 256:
* timeout = 4 -> reload = 1
* timeout = 16000 -> reload = 4096
*/
reload = (timeout * WDT_FREQUENCY + 500) / 1000;
if (reload < 1)
{
reload = 1;
}
else if (reload > 4095)
{
reload = 4095;
}
/* Calculate and save the actual timeout value in milliseconds:
*
* timeout = 1000 * (reload + 1) / Fwwdg
*/
priv->timeout = (1000 * reload + WDT_FREQUENCY / 2) / WDT_FREQUENCY;
/* Remember the selected values */
priv->reload = reload;
wdinfo("reload=%d timeout: %d->%d\n",
reload, timeout, priv->timeout);
/* Set the WDT_MR according to calculated value
*
* NOTE:
* The Watchdog Mode Register (WDT_MR) can be written only once. Only
* a processor reset resets it. Writing the WDT_MR register reloads the
* timer with the newly programmed mode parameters.
*/
regval = WDT_MR_WDV(reload) | WDT_MR_WDD(reload);
#ifdef CONFIG_SAMA5_WDT_INTERRUPT
/* Generate an interrupt whent he watchdog timer expires */
regval |= WDT_MR_WDFIEN;
#else
/* Reset (everything) if the watchdog timer expires.
*
* REVISIT: Set WDT_MR_WDRPROC so that only the processor is reset?
*/
regval |= WDT_MR_WDRSTEN;
#endif
#ifdef CONFIG_SAMA5_WDT_DEBUGHALT
/* Halt the watchdog in the debug state */
regval |= WDT_MR_WDDBGHLT;
#endif
#ifdef CONFIG_SAMA5_WDT_IDLEHALT
/* Halt the watchdog in the IDLE mode */
regval |= WDT_MR_WDIDLEHLT;
#endif
sam_putreg(regval, SAM_WDT_MR);
/* NOTE: We had to start the watchdog here (because we cannot re-write the
* MR register). So sam_start will not be able to do anything.
*/
priv->started = true;
wdinfo("Setup: CR: %08x MR: %08x SR: %08x\n",
sam_getreg(SAM_WDT_CR), sam_getreg(SAM_WDT_MR),
sam_getreg(SAM_WDT_SR));
return OK;
}
/****************************************************************************
* Name: sam_capture
*
* Description:
* Don't reset on watchdog timer timeout; instead, call this user provider
* timeout handler. NOTE: Providing handler==NULL will restore the reset
* behavior.
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* newhandler - The new watchdog expiration function pointer. If this
* function pointer is NULL, then the reset-on-expiration
* behavior is restored,
*
* Returned Value:
* The previous watchdog expiration function pointer or NULL is there was
* no previous function pointer, i.e., if the previous behavior was
* reset-on-expiration (NULL is also returned if an error occurs).
*
****************************************************************************/
static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower,
xcpt_t handler)
{
#ifndef CONFIG_SAMA5_WDT_INTERRUPT
wderr("ERROR: Not configured for this mode\n");
return NULL;
#else
FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower;
irqstate_t flags;
xcpt_t oldhandler;
DEBUGASSERT(priv);
wdinfo("Entry: handler=%p\n", handler);
/* Get the old handler return value */
flags = enter_critical_section();
oldhandler = priv->handler;
/* Save the new handler */
priv->handler = handler;
/* Are we attaching or detaching the handler? */
if (handler)
{
/* Attaching... Enable the WDT interrupt */
up_enable_irq(SAM_IRQ_WDT);
}
else
{
/* Detaching... Disable the WDT interrupt */
up_disable_irq(SAM_IRQ_WDT);
}
leave_critical_section(flags);
return oldhandler;
#endif
}
/****************************************************************************
* Name: sam_ioctl
*
* Description:
* Any ioctl commands that are not recognized by the "upper-half" driver
* are forwarded to the lower half driver through this method.
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* cmd - The ioctol command value
* arg - The optional argument that accompanies the 'cmd'. The
* interpretation of this argument depends on the particular
* command.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
unsigned long arg)
{
wdinfo("cmd=%d arg=%ld\n", cmd, arg);
/* No ioctls are supported */
return -ENOTTY;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: sam_wdt_initialize
*
* Description:
* Initialize the WDT watchdog time. The watchdog timer is initialized and
* registered as 'devpath. The initial state of the watchdog time is
* disabled.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
int sam_wdt_initialize(void)
{
FAR struct sam_lowerhalf_s *priv = &g_wdtdev;
wdinfo("Entry: CR: %08x MR: %08x SR: %08x\n",
sam_getreg(SAM_WDT_CR), sam_getreg(SAM_WDT_MR),
sam_getreg(SAM_WDT_SR));
/* Check if some previous logic was disabled the watchdog timer. Since the
* MR can be written only one time, we are out of business if that is the
* case.
*/
DEBUGASSERT((sam_getreg(SAM_WDT_MR) & WDT_MR_WDDIS) == 0);
/* No clock setup is required. The Watchdog Timer uses the Slow Clock
* divided by 128 to establish the maximum Watchdog period to be 16 seconds
* (with a typical Slow Clock of 32768 kHz).
*/
/* Initialize the driver state structure. Here we assume: (1) the state
* structure lies in .bss and was zeroed at reset time. (2) This function
* is only called once so it is never necessary to re-zero the structure.
*/
priv->ops = &g_wdgops;
#ifdef CONFIG_SAMA5_WDT_INTERRUPT
/* Attach our WDT interrupt handler (But don't enable it yet) */
irq_attach(SAM_IRQ_WDT, sam_interrupt, NULL);
#endif
/* Register the watchdog driver at the configured location (default
* /dev/watchdog0).
*/
watchdog_register(CONFIG_WATCHDOG_DEVPATH,
(FAR struct watchdog_lowerhalf_s *)priv);
return OK;
}
#endif /* CONFIG_WATCHDOG && CONFIG_SAMA5_WDT */

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/****************************************************************************
* arch/arm/src/sama5/sam_wdt.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_WDT_H
#define __ARCH_ARM_SRC_SAMA5_SAM_WDT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_wdt.h"
#ifdef CONFIG_WATCHDOG
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_wdt_initialize()
*
* Description:
* Perform architecture-specific initialization of the Watchdog hardware.
* This interface should be provided by all configurations using
* to avoid exposed platform-dependent logic.
*
* At a minimum, this function should call watchdog_register().
*
* Input Parameters:
* None
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
int sam_wdt_initialize(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_WATCHDOG */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_WDT_H */

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/****************************************************************************
* arch/arm/src/sama5/sama5d2x_memorymap.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "mmu.h"
#include "hardware/sam_memorymap.h"
#include "sam_lcd.h"
#include "sam_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/* This table describes how to map a set of 1Mb pages to space the physical
* address space of the SAMA5.
*/
#ifndef CONFIG_ARCH_ROMPGTABLE
const struct section_mapping_s g_section_mapping[] =
{
/* SAMA5 Internal Memories */
/* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the
* beginning of the .text region must appear at address at the address
* specified in the VBAR. There are three ways to accomplish this:
*
* 1. By explicitly mapping the beginning of .text region with a page
* table entry so that the virtual address zero maps to the beginning
* of the .text region. VBAR == 0x0000:0000.
*
* 2. A second way is to map the use the AXI MATRIX remap register to
* map physical address zero to the beginning of the text region,
* either internal SRAM or EBI CS 0. Then we can set an identity
* mapping to map the boot region at 0x0000:0000 to virtual address
* 0x0000:00000. VBAR == 0x0000:0000.
*
* This method is used when booting from ISRAM or NOR FLASH. In
* that case, vectors must lie at the beginning of NOFR FLASH.
*
* 3. Set the Cortex-A5 VBAR register so that the vector table address
* is moved to a location other than 0x0000:0000.
*
* This is the method used when booting from SDRAM.
*
* The system always boots from the ROM memory at address 0x0. After
* reset, and until the Remap command is performed, the SRAM is accessible
* at address 0x0020 0000. When the AXI Bus Matrix is remapped, the SRAM is
* also available at address 0x0.
*
* If we are executing out of ISRAM, then the SAMA5 primary bootloader
* probably copied us into ISRAM and set the AXI REMAP0 bit for us.
*
* If we are executing from external SDRAM, then a secondary bootloader
* must have loaded us into SDRAM. In this case, simply set the VBAR
* register to the address of the vector table (not necessary at the
* beginning or SDRAM).
*/
#ifdef CONFIG_ARCH_LOWVECTORS
{ SAM_SRAMREMAP_PSECTION, SAM_SRAMREMAP_VSECTION,
SAM_SRAMREMAP_MMUFLAGS, SAM_SRAMREMAP_NSECTIONS
},
#endif
{ SAM_NFCSRAM_PSECTION, SAM_NFCSRAM_VSECTION,
SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS
},
#ifndef CONFIG_PAGING /* Internal SRAM is already fully mapped */
{ SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION,
SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS
},
#endif
{ SAM_UDPHSRAM_PSECTION, SAM_UDPHSRAM_VSECTION,
SAM_UDPHSRAM_MMUFLAGS, SAM_UDPHSRAM_NSECTIONS
},
{ SAM_UHPOHCI_PSECTION, SAM_UHPOHCI_VSECTION,
SAM_UHPOHCI_MMUFLAGS, SAM_UHPOHCI_NSECTIONS
},
{ SAM_UHPEHCI_PSECTION, SAM_UHPEHCI_VSECTION,
SAM_UHPEHCI_MMUFLAGS, SAM_UHPEHCI_NSECTIONS
},
{ SAM_AXIMX_PSECTION, SAM_AXIMX_VSECTION,
SAM_AXIMX_MMUFLAGS, SAM_AXIMX_NSECTIONS
},
{ SAM_DAP_PSECTION, SAM_DAP_VSECTION,
SAM_DAP_MMUFLAGS, SAM_DAP_NSECTIONS
},
#if defined(CONFIG_ARCH_CHIP_SAMA5D2) && defined(CONFIG_ARCH_L2CACHE)
/* The SAMA5D2 features a second 128-Kbyte SRAM that can be allocated
* either to the L2 cache controller or used as an internal SRAM. After
* reset, this block is connected to the L2 cache controller. The
* SRAM_SEL bit, located in the SFR_L2CC_HRAMC register, is used to
* reassign this memory as system SRAM, making the two 128-Kbyte
* RAMs contiguous.
*/
{ SAM_L2CC_PSECTION, SAM_L2CC_VSECTION,
SAM_L2CC_MMUFLAGS, SAM_L2CC_NSECTIONS
},
#endif
/* SAMA5 CS0 External Memories */
#ifdef CONFIG_SAMA5_EBICS0
{ SAM_EBICS0_PSECTION, SAM_EBICS0_VSECTION,
SAM_EBICS0_MMUFLAGS, SAM_EBICS0_NSECTIONS
},
#endif
/* SAMA5 External SDRAM Memory. The SDRAM is not usable until it has been
* initialized. If we are running out of SDRAM now, we can assume that
* some second level boot loader has properly configured SRAM for us.
* In that case, we set the MMU flags for the final, fully cache-able
* state.
*
* Also, in this case, the mapping for the SDRAM was done in arm_head.S and
* need not be repeated here.
*
* If we are running from ISRAM or NOR flash, then we will need to
* configure the SDRAM ourselves. In this case, we set the MMU flags to
* the strongly ordered, non-cacheable state. We need this direct access
* to SDRAM in order to configure it. Once SDRAM has been initialized, it
* will be re- configured in its final state.
*/
#ifdef NEED_SDRAM_MAPPING
{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
MMU_STRONGLY_ORDERED, SAM_DDRCS_NSECTIONS
},
{ SAM_DDRAESCS_PSECTION, SAM_DDRAESCS_VSECTION,
MMU_STRONGLY_ORDERED, SAM_DDRAESCS_NSECTIONS
},
#endif
/* SAMA5 CS1-3 External Memories */
#ifdef CONFIG_SAMA5_EBICS1
{ SAM_EBICS1_PSECTION, SAM_EBICS1_VSECTION,
SAM_EBICS1_MMUFLAGS, SAM_EBICS1_NSECTIONS
},
#endif
#ifdef CONFIG_SAMA5_EBICS2
{ SAM_EBICS2_PSECTION, SAM_EBICS2_VSECTION,
SAM_EBICS2_MMUFLAGS, SAM_EBICS2_NSECTIONS
},
#endif
#ifdef CONFIG_SAMA5_EBICS3
{ SAM_EBICS3_PSECTION, SAM_EBICS3_VSECTION,
SAM_EBICS3_MMUFLAGS, SAM_EBICS3_NSECTIONS
},
#endif
#ifdef CONFIG_SAMA5_QSPI0AES
{ SAM_QSPI0AES_PSECTION, SAM_QSPI0AES_VSECTION,
SAM_QSPI0AES_MMUFLAGS, SAM_QSPI0AES_NSECTIONS
},
#endif
#ifdef CONFIG_SAMA5_QSPI1AES
{ SAM_QSPI1AES_PSECTION, SAM_QSPI1AES_VSECTION,
SAM_QSPI1AES_MMUFLAGS, SAM_QSPI1AES_NSECTIONS
},
#endif
#ifdef CONFIG_SAMA5_SDMMC0
{ SAM_SDMMC0_PSECTION, SAM_SDMMC0_VSECTION,
SAM_SDMMC0_MMUFLAGS, SAM_SDMMC0_NSECTIONS
},
#endif
#ifdef CONFIG_SAMA5_SDMMC1
{ SAM_SDMMC1_PSECTION, SAM_SDMMC1_VSECTION,
SAM_SDMMC1_MMUFLAGS, SAM_SDMMC1_NSECTIONS
},
#endif
#ifdef CONFIG_SAMA5_HAVE_NAND
{ SAM_NFCCR_PSECTION, SAM_NFCCR_VSECTION,
SAM_NFCCR_MMUFLAGS, SAM_NFCCR_NSECTIONS
},
#endif
#ifdef CONFIG_SAMA5_QSPI0
{ SAM_QSPI0_PSECTION, SAM_QSPI0_VSECTION,
SAM_QSPI0_MMUFLAGS, SAM_QSPI0_NSECTIONS
},
#endif
#ifdef CONFIG_SAMA5_QSPI1
{ SAM_QSPI1_PSECTION, SAM_QSPI1_VSECTION,
SAM_QSPI1_MMUFLAGS, SAM_QSPI1_NSECTIONS
},
#endif
/* SAMA5 Internal Peripherals
*
* Naming of peripheral sections differs between the SAMA5D3 and SAMA5D4.
* There is nothing called SYSC in the SAMA5D4 memory map. The third
* peripheral section is un-named in the SAMA5D4 memory map, but I have
* chosen the name PERIPHC for this usage.
*/
{ SAM_PERIPHA_PSECTION, SAM_PERIPHA_VSECTION,
SAM_PERIPHA_MMUFLAGS, SAM_PERIPHA_NSECTIONS
},
{ SAM_PERIPHB_PSECTION, SAM_PERIPHB_VSECTION,
SAM_PERIPHB_MMUFLAGS, SAM_PERIPHB_NSECTIONS
},
{ SAM_PERIPHC_PSECTION, SAM_PERIPHC_VSECTION,
SAM_PERIPHC_MMUFLAGS, SAM_PERIPHC_NSECTIONS
},
/* LCDC Framebuffer. This entry reprograms a part of one of the above
* regions, making it non-cacheable and non-buffereable.
*
* If SDRAM will be reconfigured, then we will defer setup of the
* framebuffer until after the SDRAM remapping since the framebuffer
* probablyresides in SDRAM.
*/
#if defined(CONFIG_SAMA5_LCDC) && !defined(NEED_SDRAM_REMAPPING)
{ CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE,
MMU_IOFLAGS, SAMA5_LCDC_FBNSECTIONS
},
#endif
};
/* The number of entries in the mapping table */
#define NMAPPINGS \
(sizeof(g_section_mapping) / sizeof(struct section_mapping_s))
const size_t g_num_mappings = NMAPPINGS;
#endif /* CONFIG_ARCH_ROMPGTABLE */
/* SAMA5 External SDRAM Memory. Final configuration. The SDRAM was
* configured in a temporary state to support low-level ininitialization.
* After the SDRAM has been fully initialized, this structure is used to
* set the SDRM in its final, fully cache-able state.
*/
#ifdef NEED_SDRAM_REMAPPING
const struct section_mapping_s g_operational_mapping[] =
{
/* This entry reprograms the SDRAM entry, making it cacheable and
* bufferable.
*/
{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
SAM_DDRCS_MMUFLAGS, SAM_DDRCS_NSECTIONS
},
{ SAM_DDRAESCS_PSECTION, SAM_DDRAESCS_VSECTION,
SAM_DDRAESCS_MMUFLAGS, SAM_DDRAESCS_NSECTIONS
},
/* LCDC Framebuffer. This entry reprograms a part of one of the above
* regions, making it non-cacheable and non-buffereable.
*/
#ifdef CONFIG_SAMA5_LCDC
{ CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE,
MMU_IOFLAGS, SAMA5_LCDC_FBNSECTIONS
},
#endif
};
/* The number of entries in the operational mapping table */
#define NREMAPPINGS \
(sizeof(g_operational_mapping) / sizeof(struct section_mapping_s))
const size_t g_num_opmappings = NREMAPPINGS;
#endif /* NEED_SDRAM_REMAPPING */
/****************************************************************************
* Public Functions
****************************************************************************/

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/****************************************************************************
* arch/arm/src/sama5/sama5d2x_periphclks.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAMAD52X_PERIPHCLKS_H
#define __ARCH_ARM_SRC_SAMA5_SAMAD52X_PERIPHCLKS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/irq.h>
#include "hardware/sam_pmc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Helper macros */
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCDR0)
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCDR1)
#define sam_isenabled0(s) (getreg32(SAM_PMC_PCER0) & (1 << (s)) != 0)
#define sam_isenabled1(s) (getreg32(SAM_PMC_PCER1) & (1 << ((s) - 32)) != 0)
#define sam_fiq_enableclk() /* No peripheral clock */
#define sam_arm_enableclk() /* No peripheral clock */
#define sam_pit_enableclk() sam_enableperiph0(SAM_PID_PIT)
#define sam_wdt_enableclk() sam_enableperiph0(SAM_PID_WDT)
#define sam_emac0_enableclk() sam_enableperiph0(SAM_PID_EMAC0)
#define sam_xdmac0_enableclk() sam_enableperiph0(SAM_PID_XDMAC0)
#define sam_xdmac1_enableclk() sam_enableperiph0(SAM_PID_XDMAC1)
#define sam_icm_enableclk() sam_enableperiph0(SAM_PID_ICM)
#define sam_aes_enableclk() sam_enableperiph0(SAM_PID_AES)
#define sam_aesb_enableclk() sam_enableperiph0(SAM_PID_AESB)
#define sam_tdes_enableclk() sam_enableperiph0(SAM_PID_TDES)
#define sam_sha_enableclk() sam_enableperiph0(SAM_PID_SHA)
#define sam_mpddrc_enableclk() sam_enableperiph0(SAM_PID_MPDDRC)
#define sam_matrix1_enableclk() sam_enableperiph0(SAM_PID_MATRIX1)
#define sam_matrix0_enableclk() sam_enableperiph0(SAM_PID_MATRIX0)
#define sam_secumod_enableclk() sam_enableperiph0(SAM_PID_SECUMOD)
#define sam_hsmc_enableclk() sam_enableperiph0(SAM_PID_HSMC)
#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA)
#define sam_flexcom0_enableclk() sam_enableperiph0(SAM_PID_FLEXCOM0)
#define sam_flexcom1_enableclk() sam_enableperiph0(SAM_PID_FLEXCOM1)
#define sam_flexcom2_enableclk() sam_enableperiph0(SAM_PID_FLEXCOM2)
#define sam_flexcom3_enableclk() sam_enableperiph0(SAM_PID_FLEXCOM3)
#define sam_flexcom4_enableclk() sam_enableperiph0(SAM_PID_FLEXCOM4)
#define sam_uart0_enableclk() sam_enableperiph0(SAM_PID_UART0)
#define sam_uart1_enableclk() sam_enableperiph0(SAM_PID_UART1)
#define sam_uart2_enableclk() sam_enableperiph0(SAM_PID_UART2)
#define sam_uart3_enableclk() sam_enableperiph0(SAM_PID_UART3)
#define sam_uart4_enableclk() sam_enableperiph0(SAM_PID_UART4)
#define sam_twi0_enableclk() sam_enableperiph0(SAM_PID_TWI0)
#define sam_twi1_enableclk() sam_enableperiph0(SAM_PID_TWI1)
#define sam_sdmmc0_enableclk() sam_enableperiph0(SAM_PID_SDMMC0)
#define sam_sdmmc1_enableclk() sam_enableperiph1(SAM_PID_SDMMC1)
#define sam_spi0_enableclk() sam_enableperiph1(SAM_PID_SPI0)
#define sam_spi1_enableclk() sam_enableperiph1(SAM_PID_SPI1)
#define sam_tc0_enableclk() sam_enableperiph1(SAM_PID_TC0)
#define sam_tc1_enableclk() sam_enableperiph1(SAM_PID_TC1)
#define sam_pwm_enableclk() sam_enableperiph1(SAM_PID_PWM)
#define sam_adc_enableclk() sam_enableperiph1(SAM_PID_ADC)
#define sam_uhphs_enableclk() sam_enableperiph1(SAM_PID_UHPHS)
#define sam_udphs_enableclk() sam_enableperiph1(SAM_PID_UDPHS)
#define sam_ssc0_enableclk() sam_enableperiph1(SAM_PID_SSC0)
#define sam_ssc1_enableclk() sam_enableperiph1(SAM_PID_SSC1)
#define sam_lcdc_enableclk() sam_enableperiph1(SAM_PID_LCDC)
#define sam_isc_enableclk() sam_enableperiph1(SAM_PID_ISC)
#define sam_trng_enableclk() sam_enableperiph1(SAM_PID_TRNG)
#define sam_pdmic_enableclk() sam_enableperiph1(SAM_PID_PDMIC)
#define sam_irqid_enableclk() sam_enableperiph1(SAM_PID_IRQID)
#define sam_sfc_enableclk() sam_enableperiph1(SAM_PID_SFC)
#define sam_securam_enableclk() sam_enableperiph1(SAM_PID_SECURAM)
#define sam_qspi0_enableclk() sam_enableperiph1(SAM_PID_QSPI0)
#define sam_qspi1_enableclk() sam_enableperiph1(SAM_PID_QSPI1)
#define sam_i2sc0_enableclk() sam_enableperiph1(SAM_PID_I2SC0)
#define sam_i2sc1_enableclk() sam_enableperiph1(SAM_PID_I2SC1)
#define sam_mcan0_enableclk() sam_enableperiph1(SAM_PID_MCAN00)
#define sam_mcan1_enableclk() sam_enableperiph1(SAM_PID_MCAN10)
#define sam_classd_enableclk() sam_enableperiph1(SAM_PID_CLASSD)
#define sam_sfr_enableclk() sam_enableperiph1(SAM_PID_SFR)
#define sam_saic_enableclk() sam_enableperiph1(SAM_PID_SAIC)
#define sam_aic_enableclk() sam_enableperiph1(SAM_PID_AIC)
#define sam_piob_enableclk() /* No peripheral clock */
#define sam_pioc_enableclk() /* No peripheral clock */
#define sam_piod_enableclk() /* No peripheral clock */
#define sam_sys_enableclk() /* No peripheral clock */
#define sam_acc_enableclk() /* No peripheral clock */
#define sam_rxlp_enableclk() /* No peripheral clock */
#define sam_sfrbu_enableclk() /* No peripheral clock */
#define sam_chipid_enableclk() /* No peripheral clock */
#define sam_fiq_disableclk() /* No peripheral clock */
#define sam_arm_disableclk() /* No peripheral clock */
#define sam_pit_disableclk() sam_disableperiph0(SAM_PID_PIT)
#define sam_wdt_disableclk() sam_disableperiph0(SAM_PID_WDT)
#define sam_emac0_disableclk() sam_disableperiph0(SAM_PID_EMAC0)
#define sam_xdmac0_disableclk() sam_disableperiph0(SAM_PID_XDMAC0)
#define sam_xdmac1_disableclk() sam_disableperiph0(SAM_PID_XDMAC1)
#define sam_icm_disableclk() sam_disableperiph0(SAM_PID_ICM)
#define sam_aes_disableclk() sam_disableperiph0(SAM_PID_AES)
#define sam_aesb_disableclk() sam_disableperiph0(SAM_PID_AESB)
#define sam_tdes_disableclk() sam_disableperiph0(SAM_PID_TDES)
#define sam_sha_disableclk() sam_disableperiph0(SAM_PID_SHA)
#define sam_mpddrc_disableclk() sam_disableperiph0(SAM_PID_MPDDRC)
#define sam_matrix1_disableclk() sam_disableperiph0(SAM_PID_MATRIX1)
#define sam_matrix0_disableclk() sam_disableperiph0(SAM_PID_MATRIX0)
#define sam_secumod_disableclk() sam_disableperiph0(SAM_PID_SECUMOD)
#define sam_hsmc_disableclk() sam_disableperiph0(SAM_PID_HSMC)
#define sam_pio_disableclk() sam_disableperiph0(SAM_PID_PIOA)
#define sam_flexcom0_disableclk() sam_disableperiph0(SAM_PID_FLEXCOM0)
#define sam_flexcom1_disableclk() sam_disableperiph0(SAM_PID_FLEXCOM1)
#define sam_flexcom2_disableclk() sam_disableperiph0(SAM_PID_FLEXCOM2)
#define sam_flexcom3_disableclk() sam_disableperiph0(SAM_PID_FLEXCOM3)
#define sam_flexcom4_disableclk() sam_disableperiph0(SAM_PID_FLEXCOM4)
#define sam_uart0_disableclk() sam_disableperiph0(SAM_PID_UART0)
#define sam_uart1_disableclk() sam_disableperiph0(SAM_PID_UART1)
#define sam_uart2_disableclk() sam_disableperiph0(SAM_PID_UART2)
#define sam_uart3_disableclk() sam_disableperiph0(SAM_PID_UART3)
#define sam_uart4_disableclk() sam_disableperiph0(SAM_PID_UART4)
#define sam_twi0_disableclk() sam_disableperiph0(SAM_PID_TWI0)
#define sam_twi1_disableclk() sam_disableperiph0(SAM_PID_TWI1)
#define sam_sdmmc0_disableclk() sam_disableperiph0(SAM_PID_SDMMC0)
#define sam_sdmmc1_disableclk() sam_disableperiph1(SAM_PID_SDMMC1)
#define sam_spi0_disableclk() sam_disableperiph1(SAM_PID_SPI0)
#define sam_spi1_disableclk() sam_disableperiph1(SAM_PID_SPI1)
#define sam_tc0_disableclk() sam_disableperiph1(SAM_PID_TC0)
#define sam_tc1_disableclk() sam_disableperiph1(SAM_PID_TC1)
#define sam_pwm_disableclk() sam_disableperiph1(SAM_PID_PWM)
#define sam_adc_disableclk() sam_disableperiph1(SAM_PID_ADC)
#define sam_uhphs_disableclk() sam_disableperiph1(SAM_PID_UHPHS)
#define sam_udphs_disableclk() sam_disableperiph1(SAM_PID_UDPHS)
#define sam_ssc0_disableclk() sam_disableperiph1(SAM_PID_SSC0)
#define sam_ssc1_disableclk() sam_disableperiph1(SAM_PID_SSC1)
#define sam_lcdc_disableclk() sam_disableperiph1(SAM_PID_LCDC)
#define sam_isc_disableclk() sam_disableperiph1(SAM_PID_ISC)
#define sam_trng_disableclk() sam_disableperiph1(SAM_PID_TRNG)
#define sam_pdmic_disableclk() sam_disableperiph1(SAM_PID_PDMIC)
#define sam_irqid_disableclk() sam_disableperiph1(SAM_PID_IRQID)
#define sam_sfc_disableclk() sam_disableperiph1(SAM_PID_SFC)
#define sam_securam_disableclk() sam_disableperiph1(SAM_PID_SECURAM)
#define sam_qspi0_disableclk() sam_disableperiph1(SAM_PID_QSPI0)
#define sam_qspi1_disableclk() sam_disableperiph1(SAM_PID_QSPI1)
#define sam_i2sc0_disableclk() sam_disableperiph1(SAM_PID_I2SC0)
#define sam_i2sc1_disableclk() sam_disableperiph1(SAM_PID_I2SC1)
#define sam_mcan0_disableclk() sam_disableperiph1(SAM_PID_MCAN00)
#define sam_mcan1_disableclk() sam_disableperiph1(SAM_PID_MCAN10)
#define sam_classd_disableclk() sam_disableperiph1(SAM_PID_CLASSD)
#define sam_sfr_disableclk() sam_disableperiph1(SAM_PID_SFR)
#define sam_saic_disableclk() sam_disableperiph1(SAM_PID_SAIC)
#define sam_aic_disableclk() sam_disableperiph1(SAM_PID_AIC)
#define sam_piob_disableclk() /* No peripheral clock */
#define sam_pioc_disableclk() /* No peripheral clock */
#define sam_piod_disableclk() /* No peripheral clock */
#define sam_sys_disableclk() /* No peripheral clock */
#define sam_acc_disableclk() /* No peripheral clock */
#define sam_rxlp_disableclk() /* No peripheral clock */
#define sam_sfrbu_disableclk() /* No peripheral clock */
#define sam_chipid_disableclk() /* No peripheral clock */
#define sam_fiq_isenabled() (false) /* No peripheral clock */
#define sam_arm_isenabled() (false) /* No peripheral clock */
#define sam_pit_isenabled() sam_isenabled0(SAM_PID_PIT)
#define sam_wdt_isenabled() sam_isenabled0(SAM_PID_WDT)
#define sam_emac0_isenabled() sam_isenabled0(SAM_PID_EMAC0)
#define sam_xdmac0_isenabled() sam_isenabled0(SAM_PID_XDMAC0)
#define sam_xdmac1_isenabled() sam_isenabled0(SAM_PID_XDMAC1)
#define sam_icm_isenabled() sam_isenabled0(SAM_PID_ICM)
#define sam_aes_isenabled() sam_isenabled0(SAM_PID_AES)
#define sam_aesb_isenabled() sam_isenabled0(SAM_PID_AESB)
#define sam_tdes_isenabled() sam_isenabled0(SAM_PID_TDES)
#define sam_sha_isenabled() sam_isenabled0(SAM_PID_SHA)
#define sam_mpddrc_isenabled() sam_isenabled0(SAM_PID_MPDDRC)
#define sam_matrix1_isenabled() sam_isenabled0(SAM_PID_MATRIX1)
#define sam_matrix0_isenabled() sam_isenabled0(SAM_PID_MATRIX0)
#define sam_secumod_isenabled() sam_isenabled0(SAM_PID_SECUMOD)
#define sam_hsmc_isenabled() sam_isenabled0(SAM_PID_HSMC)
#define sam_pio_isenabled() sam_isenabled0(SAM_PID_PIOA)
#define sam_flexcom0_isenabled() sam_isenabled0(SAM_PID_FLEXCOM0)
#define sam_flexcom1_isenabled() sam_isenabled0(SAM_PID_FLEXCOM1)
#define sam_flexcom2_isenabled() sam_isenabled0(SAM_PID_FLEXCOM2)
#define sam_flexcom3_isenabled() sam_isenabled0(SAM_PID_FLEXCOM3)
#define sam_flexcom4_isenabled() sam_isenabled0(SAM_PID_FLEXCOM4)
#define sam_uart0_isenabled() sam_isenabled0(SAM_PID_UART0)
#define sam_uart1_isenabled() sam_isenabled0(SAM_PID_UART1)
#define sam_uart2_isenabled() sam_isenabled0(SAM_PID_UART2)
#define sam_uart3_isenabled() sam_isenabled0(SAM_PID_UART3)
#define sam_uart4_isenabled() sam_isenabled0(SAM_PID_UART4)
#define sam_twi0_isenabled() sam_isenabled0(SAM_PID_TWI0)
#define sam_twi1_isenabled() sam_isenabled0(SAM_PID_TWI1)
#define sam_sdmmc0_isenabled() sam_isenabled0(SAM_PID_SDMMC0)
#define sam_sdmmc1_isenabled() sam_isenabled1(SAM_PID_SDMMC1)
#define sam_spi0_isenabled() sam_isenabled1(SAM_PID_SPI0)
#define sam_spi1_isenabled() sam_isenabled1(SAM_PID_SPI1)
#define sam_tc0_isenabled() sam_isenabled1(SAM_PID_TC0)
#define sam_tc1_isenabled() sam_isenabled1(SAM_PID_TC1)
#define sam_pwm_isenabled() sam_isenabled1(SAM_PID_PWM)
#define sam_adc_isenabled() sam_isenabled1(SAM_PID_ADC)
#define sam_uhphs_isenabled() sam_isenabled1(SAM_PID_UHPHS)
#define sam_udphs_isenabled() sam_isenabled1(SAM_PID_UDPHS)
#define sam_ssc0_isenabled() sam_isenabled1(SAM_PID_SSC0)
#define sam_ssc1_isenabled() sam_isenabled1(SAM_PID_SSC1)
#define sam_lcdc_isenabled() sam_isenabled1(SAM_PID_LCDC)
#define sam_isc_isenabled() sam_isenabled1(SAM_PID_ISC)
#define sam_trng_isenabled() sam_isenabled1(SAM_PID_TRNG)
#define sam_pdmic_isenabled() sam_isenabled1(SAM_PID_PDMIC)
#define sam_irqid_isenabled() sam_isenabled1(SAM_PID_IRQID)
#define sam_sfc_isenabled() sam_isenabled1(SAM_PID_SFC)
#define sam_securam_isenabled() sam_isenabled1(SAM_PID_SECURAM)
#define sam_qspi0_isenabled() sam_isenabled1(SAM_PID_QSPI0)
#define sam_qspi1_isenabled() sam_isenabled1(SAM_PID_QSPI1)
#define sam_i2sc0_isenabled() sam_isenabled1(SAM_PID_I2SC0)
#define sam_i2sc1_isenabled() sam_isenabled1(SAM_PID_I2SC1)
#define sam_mcan0_isenabled() sam_isenabled1(SAM_PID_MCAN00)
#define sam_mcan1_isenabled() sam_isenabled1(SAM_PID_MCAN10)
#define sam_classd_isenabled() sam_isenabled1(SAM_PID_CLASSD)
#define sam_sfr_isenabled() sam_isenabled1(SAM_PID_SFR)
#define sam_saic_isenabled() sam_isenabled1(SAM_PID_SAIC)
#define sam_aic_isenabled() sam_isenabled1(SAM_PID_AIC)
#define sam_piob_isenabled() (false) /* No peripheral clock */
#define sam_pioc_isenabled() (false) /* No peripheral clock */
#define sam_piod_isenabled() (false) /* No peripheral clock */
#define sam_sys_isenabled() (false) /* No peripheral clock */
#define sam_acc_isenabled() (false) /* No peripheral clock */
#define sam_rxlp_isenabled() (false) /* No peripheral clock */
#define sam_sfrbu_isenabled() (false) /* No peripheral clock */
#define sam_chipid_isenabled() (false) /* No peripheral clock */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SAMAD52X_PERIPHCLKS_H */

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@ -0,0 +1,656 @@
/****************************************************************************
* arch/arm/src/sama5/sama5d2x_pio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "arm_arch.h"
#include "hardware/_sama5d2x_pio.h"
#include "chip.h"
#include "sam_periphclks.h"
#include "sam_pio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Macros to convert a pin to a vanilla input */
#define PIO_INPUT_BITS (PIO_INPUT | PIO_CFG_DEFAULT)
#define MK_INPUT(p) (((p) & (PIO_PORT_MASK | PIO_PIN_MASK)) | PIO_INPUT_BITS)
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/* Lookup for non-secure PIOs */
const uintptr_t g_piobase[SAM_NPIO] =
{
SAM_PIO_IOGROUPA_VBASE
#if SAM_NPIO > 1
, SAM_PIO_IOGROUPB_VBASE
#endif
#if SAM_NPIO > 2
, SAM_PIO_IOGROUPC_VBASE
#endif
#if SAM_NPIO > 3
, SAM_PIO_IOGROUPD_VBASE
#endif
};
/* Lookup for non-secure PIOs */
const uintptr_t g_spiobase[SAM_NPIO] =
{
SAM_SPIO_IOGROUPA_VBASE
#if SAM_NPIO > 1
, SAM_SPIO_IOGROUPB_VBASE
#endif
#if SAM_NPIO > 2
, SAM_SPIO_IOGROUPC_VBASE
#endif
#if SAM_NPIO > 3
, SAM_SPIO_IOGROUPD_VBASE
#endif
};
/****************************************************************************
* Private Data
****************************************************************************/
/* Maps a port number to the standard port character */
#if defined(CONFIG_DEBUG_GPIO_INFO) && SAM_NPIO > 0
static const char g_portchar[SAM_NPIO] =
{
'A'
#if SAM_NPIO > 1
, 'B'
#endif
#if SAM_NPIO > 2
, 'C'
#endif
#if SAM_NPIO > 3
, 'D'
#endif
};
#endif
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_issecure
*
* Description:
* Return true if the configuration selects a secure port.
*
****************************************************************************/
static inline bool sam_issecure(pio_pinset_t cfgset)
{
return ((cfgset & PIO_INT_SECURE) != 0);
}
/****************************************************************************
* Name: sam_piobase
*
* Description:
* Return the base address of the PIO register set
*
****************************************************************************/
static uintptr_t sam_piobase(pio_pinset_t cfgset)
{
int port = (cfgset & PIO_PORT_MASK) >> PIO_PORT_SHIFT;
/* Verify that the port number is within range */
if (port < SAM_NPIO)
{
/* Is this a secure or an un-secured PIO? */
if (sam_issecure(cfgset))
{
/* Return the base address of the secure PIO registers */
return sam_spion_vbase(port);
}
else
{
/* Return the base address of the un-secured PIO registers */
return sam_pion_vbase(port);
}
}
return 0;
}
/****************************************************************************
* Name: sam_piopin
*
* Description:
* Return a bitmask corresponding to the bit position in a PIO register
*
****************************************************************************/
static inline uint32_t sam_piopin(pio_pinset_t cfgset)
{
return 1 << ((cfgset & PIO_PIN_MASK) >> PIO_PIN_SHIFT);
}
/****************************************************************************
* Name: sam_configcommon
*
* Description:
* Configure common PIO pin settings based on bit-encoded description of
* the pin.
*
****************************************************************************/
static uint32_t sam_configcommon(pio_pinset_t cfgset)
{
uint32_t regval = 0;
/* Enable/disable the pull-up as requested
* NOTE: Control of the pull-up resistor is possible regardless of the
* configuration of the I/O line (Input, Output, Open-drain).
*/
if ((cfgset & PIO_CFG_PULLUP) != 0)
{
regval |= PIO_CFGR_PUEN;
}
/* Enable/disable the pull-down as requested */
if ((cfgset & PIO_CFG_PULLDOWN) != 0)
{
regval |= PIO_CFGR_PDEN;
}
/* Check if filtering should be enabled.
* NOTE: Input filtering and Schmitt triggering apply only to inputs.
*/
if ((cfgset & PIO_CFG_DEGLITCH) != 0)
{
if ((cfgset & PIO_CFG_DEGLITCH) != 0)
{
regval |= (PIO_CFGR_IFEN | PIO_CFGR_IFSCEN);
}
else
{
regval |= PIO_CFGR_IFEN;
}
}
/* Enable/disable the Schmitt trigger inputs.
* NOTE: Input filtering and Schmitt triggering apply only to inputs.
*/
if ((cfgset & PIO_CFG_SCHMITT) != 0)
{
regval |= PIO_CFGR_SCHMITT;
}
/* Enable the open drain driver if requested.
* NOTE: The open drain apply option applies only to output and
* peripheral pins.
*/
if ((cfgset & PIO_CFG_OPENDRAIN) != 0)
{
regval |= PIO_CFGR_OPD;
}
/* Select I/O drive.
* REVISIT: Doesn't rive strength apply only to output and peripheral
* pins as well?
*/
switch (cfgset & PIO_DRIVE_MASK)
{
default:
case PIO_DRIVE_LOW:
regval |= PIO_CFGR_DRVSTR_LOW;
break;
case PIO_DRIVE_MEDIUM:
regval |= PIO_CFGR_DRVSTR_MED;
break;
case PIO_DRIVE_HIGH:
regval |= PIO_CFGR_DRVSTR_HIGH;
break;
}
return regval;
}
/****************************************************************************
* Name: sam_configinput
*
* Description:
* Configure a PIO input pin based on bit-encoded description of the pin.
*
****************************************************************************/
static inline int sam_configinput(uintptr_t base, uint32_t pin,
pio_pinset_t cfgset)
{
uint32_t regval;
/* Disable interrupts on the pin */
putreg32(pin, base + SAM_PIO_IDR_OFFSET);
/* Select GPIO input */
regval = sam_configcommon(cfgset);
regval = (PIO_CFGR_FUNC_GPIO | PIO_CFGR_DIR_INPUT);
/* Clear some output only bits. Mostly this just simplifies debug. */
putreg32(pin, base + SAM_PIO_CODR_OFFSET);
/* Configure the pin as an input and enable the PIO function */
putreg32(regval, base + SAM_PIO_CFGR_OFFSET);
return OK;
}
/****************************************************************************
* Name: sam_configoutput
*
* Description:
* Configure a PIO output pin based on bit-encoded description of the pin.
*
****************************************************************************/
static inline int sam_configoutput(uintptr_t base, uint32_t pin,
pio_pinset_t cfgset)
{
uint32_t regval;
/* Disable interrupts on the pin */
putreg32(pin, base + SAM_PIO_IDR_OFFSET);
/* Select GPIO output */
regval = sam_configcommon(cfgset);
regval = (PIO_CFGR_FUNC_GPIO | PIO_CFGR_DIR_OUTPUT);
/* Set default value. This is to be done before the pin is configured as
* an output in order to avoid any glitches at the time of the
* configuration.
*/
if ((cfgset & PIO_OUTPUT_SET) != 0)
{
putreg32(pin, base + SAM_PIO_SODR_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_CODR_OFFSET);
}
/* Configure the pin as an output and enable the PIO function */
putreg32(regval, base + SAM_PIO_CFGR_OFFSET);
return OK;
}
/****************************************************************************
* Name: sam_configperiph
*
* Description:
* Configure a PIO pin driven by a peripheral A or B signal based on
* bit-encoded description of the pin.
*
****************************************************************************/
static inline int sam_configperiph(uintptr_t base, uint32_t pin,
pio_pinset_t cfgset)
{
uint32_t regval;
unsigned int periph;
/* Disable interrupts on the pin */
putreg32(pin, base + SAM_PIO_IDR_OFFSET);
/* Select the peripheral function. The Direction bit does not apply to
* peripherals.
*/
regval = sam_configcommon(cfgset);
periph = ((cfgset & PIO_MODE_MASK) - PIO_ANALOG) >> PIO_MODE_SHIFT;
regval |= PIO_CFGR_FUNC_PERIPH(periph);
/* Clear some output only bits. Mostly this just simplifies debug. */
putreg32(pin, base + SAM_PIO_CODR_OFFSET);
/* Configure the pin as a peripheral */
putreg32(regval, base + SAM_PIO_CFGR_OFFSET);
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: sam_configpio
*
* Description:
* Configure a PIO pin based on bit-encoded description of the pin.
*
****************************************************************************/
int sam_configpio(pio_pinset_t cfgset)
{
uintptr_t base;
uint32_t pin;
irqstate_t flags;
int ret;
/* Get the base address and pin mask associated with this pin
* configuration
*/
base = sam_piobase(cfgset);
if (base == 0)
{
return -EINVAL;
}
pin = sam_piopin(cfgset);
/* Disable interrupts to prohibit re-entrance. */
flags = enter_critical_section();
/* Enable writing to PIO registers.
*
* The following registers are write-protected when WPEN is set in
* PIO_WPMR:
* - PIO Mask Register
* - PIO Configuration Register
* The following registers are write-protected when WPEN is set in
* S_PIO_WPMR:
* - Secure PIO Mask Register
* - Secure PIO Configuration Register
* - Secure PIO Slow Clock Divider Debouncing Register
* The following registers are write-protected when WPITEN is set in
* PIO_WPMR:
* - PIO Interrupt Enable Register
* - PIO Interrupt Disable Register
* The following registers are write-protected when WPITEN is set in
* S_PIO_WPMR:
* - Secure PIO Interrupt Enable Register
* - Secure PIO Interrupt Disable Register
*
* I suspect that the default state is the WPMR is unprotected, so these
* operations could probably all be avoided.
*/
putreg32(PIO_WPMR_WPKEY, SAM_PIO_WPMR);
putreg32(PIO_WPMR_WPKEY, SAM_SPIO_WPMR);
/* Select the secure or un-secured PIO operation */
#if 0
if (sam_issecure(cfgset))
{
putreg32(pin, base + SAM_SPIO_SIOSR_OFFSET);
}
else
#endif
{
putreg32(pin, base + SAM_SPIO_SIONR_OFFSET);
}
/* Set the mask register to modify only the specific pin being
* configured.
*/
putreg32(pin, base + SAM_PIO_MSKR_OFFSET);
/* Put the pin in an initial state -- a vanilla input pin */
sam_configinput(base, pin, MK_INPUT(cfgset));
/* Then handle the real pin configuration according to pin type */
switch (cfgset & PIO_MODE_MASK)
{
case PIO_INPUT:
ret = sam_configinput(base, pin, cfgset);
break;
case PIO_OUTPUT:
ret = sam_configoutput(base, pin, cfgset);
break;
case PIO_ANALOG:
/* REVISIT */
ret = OK;
break;
case PIO_PERIPHA:
case PIO_PERIPHB:
case PIO_PERIPHC:
case PIO_PERIPHD:
case PIO_PERIPHE:
case PIO_PERIPHF:
case PIO_PERIPHG:
ret = sam_configperiph(base, pin, cfgset);
break;
default:
ret = -EINVAL;
break;
}
/* Disable writing to PIO registers */
putreg32(PIO_WPMR_WPEN | PIO_WPMR_WPITEN | PIO_WPMR_WPKEY, SAM_PIO_WPMR);
putreg32(PIO_WPMR_WPEN | PIO_WPMR_WPITEN | PIO_WPMR_WPKEY, SAM_SPIO_WPMR);
leave_critical_section(flags);
return ret;
}
/****************************************************************************
* Name: sam_piowrite
*
* Description:
* Write one or zero to the selected PIO pin
*
****************************************************************************/
void sam_piowrite(pio_pinset_t pinset, bool value)
{
uintptr_t base = sam_piobase(pinset);
uint32_t pin = sam_piopin(pinset);
if (base != 0)
{
/* Set or clear the output as requested. NOTE: that there is no
* check if the pin is actually configured as an output so this could,
* potentially, do nothing.
*/
if (value)
{
putreg32(pin, base + SAM_PIO_SODR_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_CODR_OFFSET);
}
}
}
/****************************************************************************
* Name: sam_pioread
*
* Description:
* Read one or zero from the selected PIO pin
*
****************************************************************************/
bool sam_pioread(pio_pinset_t pinset)
{
uintptr_t base = sam_piobase(pinset);
uint32_t pin;
uint32_t regval;
if (base != 0)
{
pin = sam_piopin(pinset);
/* For output PIOs, the ODSR register provides the output value to
* drive the pin. The PDSR register, on the other hand, provides
* the current sensed value on a pin, whether the pin is configured
* as an input, an output or as a peripheral.
*
* There is small delay between the setting in ODSR and PDSR but
* otherwise they should be the same unless something external is
* driving the pin.
*
* Let's assume that PDSR is what the caller wants.
*/
regval = getreg32(base + SAM_PIO_PDSR_OFFSET);
return (regval & pin) != 0;
}
return 0;
}
/****************************************************************************
* Name: sam_pio_forceclk
*
* Description:
* Enable PIO clocking. Needed only for SAMA5D3/D4 compatibility. For the
* SAMA5D2, there is a common clock for all PIO ports and that clock is
* always enabled.
*
****************************************************************************/
void sam_pio_forceclk(pio_pinset_t pinset, bool enable)
{
}
/****************************************************************************
* Function: sam_dumppio
*
* Description:
* Dump all PIO registers associated with the base address of the provided
* pinset.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_GPIO_INFO
int sam_dumppio(uint32_t pinset, const char *msg)
{
irqstate_t flags;
uintptr_t base;
unsigned int port;
bool secure;
/* Get the base address associated with the PIO port */
port = (pinset & PIO_PORT_MASK) >> PIO_PORT_SHIFT;
base = sam_piobase(pinset);
secure = sam_issecure(pinset);
/* The following requires exclusive access to the PIO registers */
flags = enter_critical_section();
if (secure)
{
gpioinfo("SPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
}
else
{
gpioinfo("PIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
}
gpioinfo(" MSKR: %08x CFGR: %08x PDSR: %08x LOCKSR: %08x\n",
getreg32(base + SAM_PIO_MSKR_OFFSET),
getreg32(base + SAM_PIO_CFGR_OFFSET),
getreg32(base + SAM_PIO_PDSR_OFFSET),
getreg32(base + SAM_PIO_LOCKSR_OFFSET));
gpioinfo(" ODSR: %08x IMR: %08x ISR: %08x\n",
getreg32(base + SAM_PIO_ODSR_OFFSET),
getreg32(base + SAM_PIO_IMR_OFFSET),
getreg32(base + SAM_PIO_ISR_OFFSET));
if (secure)
{
gpioinfo(" SCDR: %08x WPMR: %08x WPSR: %08x IOSSR: %08x\n",
getreg32(SAM_SPIO_SCDR),
getreg32(SAM_SPIO_WPMR),
getreg32(SAM_SPIO_WPSR),
getreg32(base + SAM_SPIO_IOSSR_OFFSET));
}
else
{
gpioinfo(" WPMR: %08x WPSR: %08x\n",
getreg32(SAM_PIO_WPMR), getreg32(SAM_PIO_WPSR));
}
leave_critical_section(flags);
return OK;
}
#endif

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/****************************************************************************
* arch/arm/src/sama5/sama5d2x_pio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAMA5D2X_PIO_H
#define __ARCH_ARM_SRC_SAMA5_SAMA5D2X_PIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include "hardware/sam_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#if !defined(CONFIG_SAMA5_PIOA_IRQ) && !defined(CONFIG_SAMA5_PIOB_IRQ) && \
!defined(CONFIG_SAMA5_PIOC_IRQ) && !defined(CONFIG_SAMA5_PIOD_IRQ)
# undef CONFIG_SAMA5_PIO_IRQ
#endif
#define PIO_HAVE_PULLDOWN 1
#define PIO_HAVE_PERIPHCD 1
#define PIO_HAVE_SCHMITT 1
#define PIO_HAVE_DRIVE 1
#define SAM_NPIO 4 /* (4) PIOA-D */
/* Bit-encoded input to sam_configpio() *************************************/
/* 32-bit Encoding:
*
* .... .MMM MM.C CCCC CDDI IISV .PPB BBBB
*/
/* Input/Output mode:
*
* .... .MMM MM.. .... .... .... .... ....
*/
#define PIO_MODE_SHIFT (22) /* Bits 22-26: PIO mode */
#define PIO_MODE_MASK (15 << PIO_MODE_SHIFT)
# define PIO_INPUT (0 << PIO_MODE_SHIFT) /* Input */
# define PIO_OUTPUT (1 << PIO_MODE_SHIFT) /* Output */
# define PIO_ANALOG (2 << PIO_MODE_SHIFT) /* Analog */
# define PIO_PERIPHA (3 << PIO_MODE_SHIFT) /* Controlled by periph A signal */
# define PIO_PERIPHB (4 << PIO_MODE_SHIFT) /* Controlled by periph B signal */
# define PIO_PERIPHC (5 << PIO_MODE_SHIFT) /* Controlled by periph C signal */
# define PIO_PERIPHD (6 << PIO_MODE_SHIFT) /* Controlled by periph D signal */
# define PIO_PERIPHE (7 << PIO_MODE_SHIFT) /* Controlled by periph E signal */
# define PIO_PERIPHF (8 << PIO_MODE_SHIFT) /* Controlled by periph F signal */
# define PIO_PERIPHG (9 << PIO_MODE_SHIFT) /* Controlled by periph G signal */
/* These bits set the configuration of the pin:
* NOTE: No definitions for parallel capture mode
*
* .... .... ...C CCCC C... .... .... ....
*/
#define PIO_CFG_SHIFT (15) /* Bits 15-20: PIO configuration bits */
#define PIO_CFG_MASK (0x3f << PIO_CFG_SHIFT)
# define PIO_CFG_DEFAULT (0x00 << PIO_CFG_SHIFT) /* Default, no attribute */
# define PIO_CFG_PULLUP (0x01 << PIO_CFG_SHIFT) /* Bit 15: Internal pull-up */
# define PIO_CFG_PULLDOWN (0x02 << PIO_CFG_SHIFT) /* Bit 16: Internal pull-down */
# define PIO_CFG_DEGLITCH (0x04 << PIO_CFG_SHIFT) /* Bit 17: Internal input filter (Tmck/2)*/
# define PIO_CFG_SLOWCLK (0x0c << PIO_CFG_SHIFT) /* Bits 17+18: Internal input filter (Tslwclk/2)*/
# define PIO_CFG_OPENDRAIN (0x10 << PIO_CFG_SHIFT) /* Bit 19: Open drain */
# define PIO_CFG_SCHMITT (0x20 << PIO_CFG_SHIFT) /* Bit 20: Schmitt trigger */
/* Drive Strength:
*
* .... .... .... .... .DD. .... .... ....
*/
#define PIO_DRIVE_SHIFT (13) /* Bits 13-14: Drive strength */
#define PIO_DRIVE_MASK (7 << PIO_DRIVE_SHIFT)
# define PIO_DRIVE_LOW (0 << PIO_DRIVE_SHIFT)
# define PIO_DRIVE_MEDIUM (2 << PIO_DRIVE_SHIFT)
# define PIO_DRIVE_HIGH (3 << PIO_DRIVE_SHIFT)
/* Additional interrupt modes:
*
* .... .... .... .... ...I II.. .... ....
*/
#define PIO_INT_SHIFT (10) /* Bits 9-12: PIO interrupt bits */
#define PIO_INT_MASK (7 << PIO_INT_SHIFT)
# define PIO_INT_NONE (0 << PIO_INT_SHIFT)
# define PIO_INT_FALLING (1 << PIO_INT_SHIFT)
# define PIO_INT_RISING (2 << PIO_INT_SHIFT)
# define PIO_INT_BOTHEDGES (3 << PIO_INT_SHIFT)
# define PIO_INT_LOWLEVEL (4 << PIO_INT_SHIFT)
# define PIO_INT_HIGHLEVEL (5 << PIO_INT_SHIFT)
/* If the pin is an interrupt, then this determines if the pin is a secure:
*
* .... .... .... .... .... ..S. .... ....
*/
#define PIO_INT_SECURE (1 << 9) /* Bit 9: Secure PIO */
#define PIO_INT_UNSECURE (0)
/* If the pin is an PIO output, then this identifies the initial output
* value:
*
* .... .... .... .... .... ...V .... ....
*/
#define PIO_OUTPUT_SET (1 << 8) /* Bit 8: Initial value of output */
#define PIO_OUTPUT_CLEAR (0)
/* This identifies the PIO port:
*
* .... .... .... .... .... .... .PP. ....
*/
#define PIO_PORT_SHIFT (5) /* Bit 5-6: Port number */
#define PIO_PORT_MASK (3 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOA (0 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOB (1 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOC (2 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOD (3 << PIO_PORT_SHIFT)
/* This identifies the bit in the port:
*
* .... .... .... .... .... .... ...B BBBB
*/
#define PIO_PIN_SHIFT (0) /* Bits 0-4: PIO number: 0-31 */
#define PIO_PIN_MASK (31 << PIO_PIN_SHIFT)
#define PIO_PIN0 (0 << PIO_PIN_SHIFT)
#define PIO_PIN1 (1 << PIO_PIN_SHIFT)
#define PIO_PIN2 (2 << PIO_PIN_SHIFT)
#define PIO_PIN3 (3 << PIO_PIN_SHIFT)
#define PIO_PIN4 (4 << PIO_PIN_SHIFT)
#define PIO_PIN5 (5 << PIO_PIN_SHIFT)
#define PIO_PIN6 (6 << PIO_PIN_SHIFT)
#define PIO_PIN7 (7 << PIO_PIN_SHIFT)
#define PIO_PIN8 (8 << PIO_PIN_SHIFT)
#define PIO_PIN9 (9 << PIO_PIN_SHIFT)
#define PIO_PIN10 (10 << PIO_PIN_SHIFT)
#define PIO_PIN11 (11 << PIO_PIN_SHIFT)
#define PIO_PIN12 (12 << PIO_PIN_SHIFT)
#define PIO_PIN13 (13 << PIO_PIN_SHIFT)
#define PIO_PIN14 (14 << PIO_PIN_SHIFT)
#define PIO_PIN15 (15 << PIO_PIN_SHIFT)
#define PIO_PIN16 (16 << PIO_PIN_SHIFT)
#define PIO_PIN17 (17 << PIO_PIN_SHIFT)
#define PIO_PIN18 (18 << PIO_PIN_SHIFT)
#define PIO_PIN19 (19 << PIO_PIN_SHIFT)
#define PIO_PIN20 (20 << PIO_PIN_SHIFT)
#define PIO_PIN21 (21 << PIO_PIN_SHIFT)
#define PIO_PIN22 (22 << PIO_PIN_SHIFT)
#define PIO_PIN23 (23 << PIO_PIN_SHIFT)
#define PIO_PIN24 (24 << PIO_PIN_SHIFT)
#define PIO_PIN25 (25 << PIO_PIN_SHIFT)
#define PIO_PIN26 (26 << PIO_PIN_SHIFT)
#define PIO_PIN27 (27 << PIO_PIN_SHIFT)
#define PIO_PIN28 (28 << PIO_PIN_SHIFT)
#define PIO_PIN29 (29 << PIO_PIN_SHIFT)
#define PIO_PIN30 (30 << PIO_PIN_SHIFT)
#define PIO_PIN31 (31 << PIO_PIN_SHIFT)
/****************************************************************************
* Public Types
****************************************************************************/
/* Must be big enough to hold the 32-bit encoding */
typedef uint32_t pio_pinset_t;
#endif /* __ARCH_ARM_SRC_SAMA5_SAMA5D2X_PIO_H */

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/****************************************************************************
* arch/arm/src/sama5/sama5d3x4x_pio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "arm_arch.h"
#include "hardware/_sama5d3x4x_pio.h"
#include "chip.h"
#include "sam_periphclks.h"
#include "sam_pio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Macros to convert a pin to a vanilla input */
#define PIO_INPUT_BITS (PIO_INPUT | PIO_CFG_DEFAULT)
#define MK_INPUT(p) (((p) & (PIO_PORT_MASK | PIO_PIN_MASK)) | PIO_INPUT_BITS)
/****************************************************************************
* Public Data
****************************************************************************/
/* Lookup for (non-secure) PIOs */
const uintptr_t g_piobase[SAM_NPIO] =
{
SAM_PIOA_VBASE
#if SAM_NPIO > 1
, SAM_PIOB_VBASE
#endif
#if SAM_NPIO > 2
, SAM_PIOC_VBASE
#endif
#if SAM_NPIO > 3
, SAM_PIOD_VBASE
#endif
#if SAM_NPIO > 4
, SAM_PIOE_VBASE
#endif
};
/****************************************************************************
* Private Data
****************************************************************************/
/* Maps a port number to the standard port character */
#if defined(CONFIG_DEBUG_GPIO_INFO) && SAM_NPIO > 0
static const char g_portchar[SAM_NPIO] =
{
'A'
#if SAM_NPIO > 1
, 'B'
#endif
#if SAM_NPIO > 2
, 'C'
#endif
#if SAM_NPIO > 3
, 'D'
#endif
#if SAM_NPIO > 4
, 'E'
#endif
};
#endif
/* Map a PIO number to the PIO peripheral identifier (PID) */
#if SAM_NPIO > 0
static const uint8_t g_piopid[SAM_NPIO] =
{
SAM_PID_PIOA
#if SAM_NPIO > 1
, SAM_PID_PIOB
#endif
#if SAM_NPIO > 2
, SAM_PID_PIOC
#endif
#if SAM_NPIO > 3
, SAM_PID_PIOD
#endif
#if SAM_NPIO > 4
, SAM_PID_PIOE
#endif
};
#endif
/* Used to determine if a PIO port is configured to support interrupts */
#if SAM_NPIO > 0
static const bool g_piointerrupt[SAM_NPIO] =
{
#ifdef CONFIG_SAMA5_PIOA_IRQ
true
#else
false
#endif
#if SAM_NPIO > 1
#ifdef CONFIG_SAMA5_PIOB_IRQ
, true
#else
, false
#endif
#endif
#if SAM_NPIO > 2
#ifdef CONFIG_SAMA5_PIOC_IRQ
, true
#else
, false
#endif
#endif
#if SAM_NPIO > 3
#ifdef CONFIG_SAMA5_PIOD_IRQ
, true
#else
, false
#endif
#endif
#if SAM_NPIO > 4
#ifdef CONFIG_SAMA5_PIOE_IRQ
, true
#else
, false
#endif
#endif
};
#endif
/* This is an array of ports that PIO enable forced on */
static uint32_t g_forced[SAM_NPIO];
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_piobase
*
* Description:
* Return the base address of the PIO register set
*
****************************************************************************/
static inline uintptr_t sam_piobase(pio_pinset_t cfgset)
{
int port = (cfgset & PIO_PORT_MASK) >> PIO_PORT_SHIFT;
if (port < SAM_NPIO)
{
return sam_pion_vbase(port);
}
else
{
return 0;
}
}
/****************************************************************************
* Name: sam_piopin
*
* Description:
* Return a bitmask corresponding to the bit position in a PIO register
*
****************************************************************************/
static inline uint32_t sam_piopin(pio_pinset_t cfgset)
{
return 1 << ((cfgset & PIO_PIN_MASK) >> PIO_PIN_SHIFT);
}
/****************************************************************************
* Name: sam_pio_enableclk
*
* Description:
* Enable clocking on the selected PIO
*
****************************************************************************/
static void sam_pio_enableclk(pio_pinset_t cfgset)
{
int port = (cfgset & PIO_PORT_MASK) >> PIO_PORT_SHIFT;
int pid;
if (port < SAM_NPIO)
{
/* Get the peripheral ID associated with the PIO port and enable
* clocking to the PIO block.
*/
pid = g_piopid[port];
if (pid < 32)
{
sam_enableperiph0(pid);
}
else
{
sam_enableperiph1(pid);
}
}
}
/****************************************************************************
* Name: sam_pio_disableclk
*
* Description:
* Disable clocking on the selected PIO if we can. We can that if:
*
* 1) No pins are configured as PIO inputs (peripheral inputs don't need
* clocking, and
* 2) Glitch and debounce filtering are not enabled. Currently, this can
* only happen if the pin is a PIO input, but we may need to
* implement glitch filtering on peripheral inputs as well in the
* future???
* 3) The port is not configured for PIO interrupts. At present, the logic
* always keeps clocking on to ports that are configured for interrupts,
* but that could be dynamically controlled as well be keeping track
* of which PIOs have interrupts enabled.
*
* My! Wouldn't is be much easier to just keep all of the PIO clocks
* enabled? Is there a power management downside?
*
****************************************************************************/
static void sam_pio_disableclk(pio_pinset_t cfgset)
{
int port = (cfgset & PIO_PORT_MASK) >> PIO_PORT_SHIFT;
uintptr_t base;
int pid;
/* Leave clocking enabled for configured interrupt ports or for ports that
* have forced enabling of PIO clocking.
*/
if (port < SAM_NPIO && !g_piointerrupt[port] && g_forced[port] == 0)
{
/* Get the base address of the PIO port */
base = sam_pion_vbase(port);
/* Are any pins configured as PIO inputs?
*
* PSR - A bit set to "1" means that the corresponding pin is a PIO
* OSR - A bit set to "1" means that the corresponding pin is an output
*/
if ((getreg32(base + SAM_PIO_PSR_OFFSET) &
~getreg32(base + SAM_PIO_PSR_OFFSET)) == 0)
{
/* Any remaining configured pins are either not PIOs or all not
* PIO inputs. Disable clocking to this PIO block.
*
* Get the peripheral ID associated with the PIO port and disable
* clocking to the PIO block.
*/
pid = g_piopid[port];
if (pid < 32)
{
sam_disableperiph0(pid);
}
else
{
sam_disableperiph1(pid);
}
}
}
}
/****************************************************************************
* Name: sam_configinput
*
* Description:
* Configure a PIO input pin based on bit-encoded description of the pin.
*
****************************************************************************/
static inline int sam_configinput(uintptr_t base, uint32_t pin,
pio_pinset_t cfgset)
{
#if defined(PIO_HAVE_SCHMITT) || defined(PIO_HAVE_DRIVE)
uint32_t regval;
#endif
#if defined(PIO_HAVE_DRIVE)
uint32_t offset;
uint32_t mask;
uint32_t drive;
int shift;
#endif
/* Disable interrupts on the pin */
putreg32(pin, base + SAM_PIO_IDR_OFFSET);
/* Enable/disable the pull-up as requested */
if ((cfgset & PIO_CFG_PULLUP) != 0)
{
#ifdef PIO_HAVE_PULLDOWN
/* The pull-up on a pin can not be enabled if its pull-down is still
* active. Therefore, we need to disable the pull-down first before
* enabling the pull-up.
*/
putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
#endif
putreg32(pin, base + SAM_PIO_PUER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
}
#ifdef PIO_HAVE_PULLDOWN
/* Enable/disable the pull-down as requested */
if ((cfgset & PIO_CFG_PULLDOWN) != 0)
{
/* The pull-down on a pin can not be enabled if its pull-up is still
* active. Therefore, we need to disable the pull-up first before
* enabling the pull-down.
*/
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
}
#endif
/* Check if filtering should be enabled */
if ((cfgset & PIO_CFG_DEGLITCH) != 0)
{
putreg32(pin, base + SAM_PIO_IFER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_IFDR_OFFSET);
}
#ifdef PIO_HAVE_SCHMITT
/* Enable/disable the Schmitt trigger: Zero enables. Schmitt triggered
* inputs are enabled by default.
*/
regval = getreg32(base + SAM_PIO_SCHMITT_OFFSET);
if ((cfgset & PIO_CFG_SCHMITT) != 0)
{
regval &= ~pin;
}
else
{
regval |= pin;
}
putreg32(regval, base + SAM_PIO_SCHMITT_OFFSET);
#endif
#ifdef PIO_HAVE_DRIVE
/* Configure drive strength */
drive = (cfgset & PIO_DRIVE_MASK) >> PIO_DRIVE_SHIFT;
if (pin < 32)
{
offset = SAM_PIO_DRIVER1_OFFSET;
mask = PIO_DRIVER1_LINE_MASK(pin);
shift = PIO_DRIVER1_LINE_SHIFT(pin);
}
else
{
offset = SAM_PIO_DRIVER2_OFFSET;
mask = PIO_DRIVER2_LINE_MASK(pin);
shift = PIO_DRIVER2_LINE_SHIFT(pin);
}
regval = getreg32(base + offset);
regval &= ~mask;
regval |= drive << shift;
putreg32(regval, base + offset);
#endif
/* Clear some output only bits. Mostly this just simplifies debug. */
putreg32(pin, base + SAM_PIO_MDDR_OFFSET);
putreg32(pin, base + SAM_PIO_CODR_OFFSET);
/* Configure the pin as an input and enable the PIO function */
putreg32(pin, base + SAM_PIO_ODR_OFFSET);
putreg32(pin, base + SAM_PIO_PER_OFFSET);
/* To-Do: If DEGLITCH is selected, need to configure DIFSR, SCIFSR, and
* IFDGSR registers. This would probably best be done with
* another, new API... perhaps sam_configfilter()
*/
/* "Reading the I/O line levels requires the clock of the PIO Controller
* to be enabled, otherwise PIO_PDSR reads the levels present on the I/O
* line at the time the clock was disabled."
*/
sam_pio_enableclk(cfgset);
return OK;
}
/****************************************************************************
* Name: sam_configoutput
*
* Description:
* Configure a PIO output pin based on bit-encoded description of the pin.
*
****************************************************************************/
static inline int sam_configoutput(uintptr_t base, uint32_t pin,
pio_pinset_t cfgset)
{
/* Disable interrupts on the pin */
putreg32(pin, base + SAM_PIO_IDR_OFFSET);
/* Enable/disable the pull-up as requested */
if ((cfgset & PIO_CFG_PULLUP) != 0)
{
#ifdef PIO_HAVE_PULLDOWN
/* The pull-up on a pin can not be enabled if its pull-down is still
* active. Therefore, we need to disable the pull-down first before
* enabling the pull-up.
*/
putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
#endif
putreg32(pin, base + SAM_PIO_PUER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
}
#ifdef PIO_HAVE_PULLDOWN
/* Enable/disable the pull-down as requested */
if ((cfgset & PIO_CFG_PULLDOWN) != 0)
{
/* The pull-down on a pin can not be enabled if its pull-up is still
* active. Therefore, we need to disable the pull-up first before
* enabling the pull-down.
*/
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
}
#endif
/* Disable glitch filtering */
putreg32(pin, base + SAM_PIO_IFDR_OFFSET);
/* Enable the open drain driver if requested */
if ((cfgset & PIO_CFG_OPENDRAIN) != 0)
{
putreg32(pin, base + SAM_PIO_MDER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_MDDR_OFFSET);
}
/* Set default value. This is to be done before the pin is configured as
* an output in order to avoid any glitches at the time of the
* configuration.
*/
if ((cfgset & PIO_OUTPUT_SET) != 0)
{
putreg32(pin, base + SAM_PIO_SODR_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_CODR_OFFSET);
}
/* Configure the pin as an output and enable the PIO function */
putreg32(pin, base + SAM_PIO_OER_OFFSET);
putreg32(pin, base + SAM_PIO_PER_OFFSET);
/* Clocking to the PIO block may no longer be necessary. */
sam_pio_disableclk(cfgset);
return OK;
}
/****************************************************************************
* Name: sam_configperiph
*
* Description:
* Configure a PIO pin driven by a peripheral A or B signal based on
* bit-encoded description of the pin.
*
****************************************************************************/
static inline int sam_configperiph(uintptr_t base, uint32_t pin,
pio_pinset_t cfgset)
{
uint32_t regval;
/* Disable interrupts on the pin */
putreg32(pin, base + SAM_PIO_IDR_OFFSET);
/* Enable/disable the pull-up as requested */
if ((cfgset & PIO_CFG_PULLUP) != 0)
{
#ifdef PIO_HAVE_PULLDOWN
/* The pull-up on a pin can not be enabled if its pull-down is still
* active. Therefore, we need to disable the pull-down first before
* enabling the pull-up.
*/
putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
#endif
putreg32(pin, base + SAM_PIO_PUER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
}
#ifdef PIO_HAVE_PULLDOWN
/* Enable/disable the pull-down as requested */
if ((cfgset & PIO_CFG_PULLDOWN) != 0)
{
/* The pull-down on a pin can not be enabled if its pull-up is still
* active. Therefore, we need to disable the pull-up first before
* enabling the pull-down.
*/
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
}
#endif
/* Disable glitch filtering */
putreg32(pin, base + SAM_PIO_IFDR_OFFSET);
#ifdef PIO_HAVE_PERIPHCD
/* Configure pin, depending upon the peripheral A, B, C or D
*
* PERIPHA: ABCDSR1[n] = 0 ABCDSR2[n] = 0
* PERIPHB: ABCDSR1[n] = 1 ABCDSR2[n] = 0
* PERIPHC: ABCDSR1[n] = 0 ABCDSR2[n] = 1
* PERIPHD: ABCDSR1[n] = 1 ABCDSR2[n] = 1
*/
regval = getreg32(base + SAM_PIO_ABCDSR1_OFFSET);
if ((cfgset & PIO_MODE_MASK) == PIO_PERIPHA ||
(cfgset & PIO_MODE_MASK) == PIO_PERIPHC)
{
regval &= ~pin;
}
else
{
regval |= pin;
}
putreg32(regval, base + SAM_PIO_ABCDSR1_OFFSET);
regval = getreg32(base + SAM_PIO_ABCDSR2_OFFSET);
if ((cfgset & PIO_MODE_MASK) == PIO_PERIPHA ||
(cfgset & PIO_MODE_MASK) == PIO_PERIPHB)
{
regval &= ~pin;
}
else
{
regval |= pin;
}
putreg32(regval, base + SAM_PIO_ABCDSR2_OFFSET);
#else
/* Configure pin, depending upon the peripheral A or B:
*
* PERIPHA: ABSR[n] = 0
* PERIPHB: ABSR[n] = 1
*/
regval = getreg32(base + SAM_PIO_ABSR_OFFSET);
if ((cfgset & PIO_MODE_MASK) == PIO_PERIPHA)
{
regval &= ~pin;
}
else
{
regval |= pin;
}
putreg32(regval, base + SAM_PIO_ABSR_OFFSET);
#endif
/* Disable PIO functionality */
putreg32(pin, base + SAM_PIO_PDR_OFFSET);
/* Clocking to the PIO block may no longer be necessary. */
sam_pio_disableclk(cfgset);
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: sam_configpio
*
* Description:
* Configure a PIO pin based on bit-encoded description of the pin.
*
****************************************************************************/
int sam_configpio(pio_pinset_t cfgset)
{
uintptr_t base;
uint32_t pin;
irqstate_t flags;
int ret;
/* Sanity check */
base = sam_piobase(cfgset);
if (base == 0)
{
return -EINVAL;
}
pin = sam_piopin(cfgset);
/* Disable interrupts to prohibit re-entrance. */
flags = enter_critical_section();
/* Enable writing to PIO registers. The following registers are protected:
*
* - PIO Enable/Disable Registers (PER/PDR)
* - PIO Output Enable/Disable Registers (OER/ODR)
* - PIO Interrupt Security Level Register (ISLR)
* - PIO Input Filter Enable/Disable Registers (IFER/IFDR)
* - PIO Multi-driver Enable/Disable Registers (MDER/MDDR)
* - PIO Pull-Up Enable/Disable Registers (PUER/PUDR)
* - PIO Peripheral ABCD Select Register 1/2 (ABCDSR1/2)
* - PIO Output Write Enable/Disable Registers
* - PIO Pad Pull-Down Enable/Disable Registers (PPER/PPDR)
*
* I suspect that the default state is the WPMR is unprotected, so these
* operations could probably all be avoided.
*/
putreg32(PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET);
/* Put the pin in an initial state -- a vanilla input pin */
sam_configinput(base, pin, MK_INPUT(cfgset));
/* Then handle the real pin configuration according to pin type */
switch (cfgset & PIO_MODE_MASK)
{
case PIO_INPUT:
ret = sam_configinput(base, pin, cfgset);
break;
case PIO_OUTPUT:
ret = sam_configoutput(base, pin, cfgset);
break;
case PIO_PERIPHA:
case PIO_PERIPHB:
#ifdef PIO_HAVE_PERIPHCD
case PIO_PERIPHC:
case PIO_PERIPHD:
#endif
ret = sam_configperiph(base, pin, cfgset);
break;
default:
ret = -EINVAL;
break;
}
/* Disable writing to PIO registers */
putreg32(PIO_WPMR_WPEN | PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET);
leave_critical_section(flags);
return ret;
}
/****************************************************************************
* Name: sam_piowrite
*
* Description:
* Write one or zero to the selected PIO pin
*
****************************************************************************/
void sam_piowrite(pio_pinset_t pinset, bool value)
{
uintptr_t base = sam_piobase(pinset);
uint32_t pin = sam_piopin(pinset);
if (base != 0)
{
/* Set or clear the output as requested. NOTE: that there is no
* check if the pin is actually configured as an output so this could,
* potentially, do nothing.
*/
if (value)
{
putreg32(pin, base + SAM_PIO_SODR_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_CODR_OFFSET);
}
}
}
/****************************************************************************
* Name: sam_pioread
*
* Description:
* Read one or zero from the selected PIO pin
*
****************************************************************************/
bool sam_pioread(pio_pinset_t pinset)
{
uintptr_t base = sam_piobase(pinset);
uint32_t pin;
uint32_t regval;
if (base != 0)
{
pin = sam_piopin(pinset);
/* For output PIOs, the ODSR register provides the output value to
* drive the pin. The PDSR register, on the other hand, provides
* the current sensed value on a pin, whether the pin is configured
* as an input, an output or as a peripheral.
*
* There is small delay between the setting in ODSR and PDSR but
* otherwise they should be the same unless something external is
* driving the pin.
*
* Let's assume that PDSR is what the caller wants.
*/
regval = getreg32(base + SAM_PIO_PDSR_OFFSET);
return (regval & pin) != 0;
}
return 0;
}
/****************************************************************************
* Name: sam_pio_forceclk
*
* Description:
* Enable PIO clocking.
* This logic is overly conservative and does not enable PIO clocking
* unless necessary (PIO input selected, glitch/filtering enable, or PIO
* interrupts enabled). There are, however, certain conditions were we may
* want to force the PIO clock to be enabled.
* An example is reading the input value from an open drain output.
*
* The PIO automatic enable/disable logic is not smart enough enough to
* know about these cases.
* For those cases, sam_pio_forceclk() is provided.
*
****************************************************************************/
void sam_pio_forceclk(pio_pinset_t pinset, bool enable)
{
unsigned int port;
uint32_t pin;
irqstate_t flags;
/* Extract the port number */
port = (pinset & PIO_PORT_MASK) >> PIO_PORT_SHIFT;
pin = sam_piopin(pinset);
/* The remainder of this operation must be atomic */
flags = enter_critical_section();
/* Are we enabling or disabling clocking */
if (enable)
{
/* Indicate that clocking is forced and enable the clock */
g_forced[port] |= pin;
sam_pio_enableclk(pinset);
}
else
{
/* Clocking is no longer forced for this pin */
g_forced[port] &= ~pin;
sam_pio_disableclk(pinset);
}
leave_critical_section(flags);
}
/****************************************************************************
* Function: sam_dumppio
*
* Description:
* Dump all PIO registers associated with the base address of the provided
* pinset.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_GPIO_INFO
int sam_dumppio(uint32_t pinset, const char *msg)
{
irqstate_t flags;
uintptr_t base;
unsigned int port;
/* Get the base address associated with the PIO port */
port = (pinset & PIO_PORT_MASK) >> PIO_PORT_SHIFT;
base = sam_pion_vbase(port);
/* The following requires exclusive access to the PIO registers */
flags = enter_critical_section();
gpioinfo("PIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
#ifdef SAM_PIO_ISLR_OFFSET
gpioinfo(" PSR: %08x ISLR: %08x OSR: %08x IFSR: %08x\n",
getreg32(base + SAM_PIO_PSR_OFFSET),
getreg32(base + SAM_PIO_ISLR_OFFSET),
getreg32(base + SAM_PIO_OSR_OFFSET),
getreg32(base + SAM_PIO_IFSR_OFFSET));
#else
gpioinfo(" PSR: %08x OSR: %08x IFSR: %08x\n",
getreg32(base + SAM_PIO_PSR_OFFSET),
getreg32(base + SAM_PIO_OSR_OFFSET),
getreg32(base + SAM_PIO_IFSR_OFFSET));
#endif
gpioinfo(" ODSR: %08x PDSR: %08x IMR: %08x ISR: %08x\n",
getreg32(base + SAM_PIO_ODSR_OFFSET),
getreg32(base + SAM_PIO_PDSR_OFFSET),
getreg32(base + SAM_PIO_IMR_OFFSET),
getreg32(base + SAM_PIO_ISR_OFFSET));
gpioinfo(" MDSR: %08x PUSR: %08x ABDCSR: %08x %08x\n",
getreg32(base + SAM_PIO_MDSR_OFFSET),
getreg32(base + SAM_PIO_PUSR_OFFSET),
getreg32(base + SAM_PIO_ABCDSR1_OFFSET),
getreg32(base + SAM_PIO_ABCDSR2_OFFSET));
gpioinfo(" IFSCSR: %08x SCDR: %08x PPDSR: %08x OWSR: %08x\n",
getreg32(base + SAM_PIO_IFSCSR_OFFSET),
getreg32(base + SAM_PIO_SCDR_OFFSET),
getreg32(base + SAM_PIO_PPDSR_OFFSET),
getreg32(base + SAM_PIO_OWSR_OFFSET));
#ifdef SAM_PIO_LOCKSR_OFFSET
gpioinfo(" AIMMR: %08x ELSR: %08x FRLHSR: %08x LOCKSR: %08x\n",
getreg32(base + SAM_PIO_AIMMR_OFFSET),
getreg32(base + SAM_PIO_ELSR_OFFSET),
getreg32(base + SAM_PIO_FRLHSR_OFFSET),
getreg32(base + SAM_PIO_LOCKSR_OFFSET));
#else
gpioinfo(" AIMMR: %08x ELSR: %08x FRLHSR: %08x\n",
getreg32(base + SAM_PIO_AIMMR_OFFSET),
getreg32(base + SAM_PIO_ELSR_OFFSET),
getreg32(base + SAM_PIO_FRLHSR_OFFSET));
#endif
gpioinfo("SCHMITT: %08x DRIVER: %08x %08x\n",
getreg32(base + SAM_PIO_SCHMITT_OFFSET),
getreg32(base + SAM_PIO_DRIVER1_OFFSET),
getreg32(base + SAM_PIO_DRIVER2_OFFSET));
gpioinfo(" WPMR: %08x WPSR: %08x\n",
getreg32(base + SAM_PIO_WPMR_OFFSET),
getreg32(base + SAM_PIO_WPSR_OFFSET));
leave_critical_section(flags);
return OK;
}
#endif

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/****************************************************************************
* arch/arm/src/sama5/sama5d3x4x_pio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAMA5D3X4X_PIO_H
#define __ARCH_ARM_SRC_SAMA5_SAMA5D3X4X_PIO_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#if !defined(CONFIG_SAMA5_PIOA_IRQ) && !defined(CONFIG_SAMA5_PIOB_IRQ) && \
!defined(CONFIG_SAMA5_PIOC_IRQ) && !defined(CONFIG_SAMA5_PIOD_IRQ) && \
!defined(CONFIG_SAMA5_PIOE_IRQ) && !defined(CONFIG_SAMA5_PIOF_IRQ)
# undef CONFIG_SAMA5_PIO_IRQ
#endif
#define PIO_HAVE_PULLDOWN 1
#define PIO_HAVE_PERIPHCD 1
#define PIO_HAVE_SCHMITT 1
#define PIO_HAVE_DRIVE 1
#define SAM_NPIO 5 /* (5) PIOA-E */
/* Bit-encoded input to sam_configpio() *************************************/
/* 32-bit Encoding:
*
* .... .... .MMM CCCC CDDI IISV PPPB BBBB
*/
/* Input/Output mode:
*
* .... .... .MMM .... .... .... .... ....
*/
#define PIO_MODE_SHIFT (20) /* Bits 20-22: PIO mode */
#define PIO_MODE_MASK (7 << PIO_MODE_SHIFT)
# define PIO_INPUT (0 << PIO_MODE_SHIFT) /* Input */
# define PIO_OUTPUT (1 << PIO_MODE_SHIFT) /* Output */
# define PIO_PERIPHA (2 << PIO_MODE_SHIFT) /* Controlled by periph A signal */
# define PIO_PERIPHB (3 << PIO_MODE_SHIFT) /* Controlled by periph B signal */
# define PIO_PERIPHC (4 << PIO_MODE_SHIFT) /* Controlled by periph C signal */
# define PIO_PERIPHD (5 << PIO_MODE_SHIFT) /* Controlled by periph D signal */
/* These bits set the configuration of the pin:
* NOTE: No definitions for parallel capture mode
*
* .... .... .... CCCC C... .... .... ....
*/
#define PIO_CFG_SHIFT (15) /* Bits 15-19: PIO configuration bits */
#define PIO_CFG_MASK (31 << PIO_CFG_SHIFT)
# define PIO_CFG_DEFAULT (0 << PIO_CFG_SHIFT) /* Default, no attribute */
# define PIO_CFG_PULLUP (1 << PIO_CFG_SHIFT) /* Bit 15: Internal pull-up */
# define PIO_CFG_PULLDOWN (2 << PIO_CFG_SHIFT) /* Bit 16: Internal pull-down */
# define PIO_CFG_DEGLITCH (4 << PIO_CFG_SHIFT) /* Bit 17: Internal glitch filter */
# define PIO_CFG_OPENDRAIN (8 << PIO_CFG_SHIFT) /* Bit 18: Open drain */
# define PIO_CFG_SCHMITT (16 << PIO_CFG_SHIFT) /* Bit 19: Schmitt trigger */
/* Drive Strength:
*
* .... .... .... .... .DD. .... .... ....
*/
#define PIO_DRIVE_SHIFT (13) /* Bits 13-14: Drive strength */
#define PIO_DRIVE_MASK (7 << PIO_DRIVE_SHIFT)
# define PIO_DRIVE_LOW (0 << PIO_DRIVE_SHIFT)
# define PIO_DRIVE_MEDIUM (2 << PIO_DRIVE_SHIFT)
# define PIO_DRIVE_HIGH (3 << PIO_DRIVE_SHIFT)
/* Additional interrupt modes:
*
* .... .... .... .... ...I II.. .... ....
*/
#define PIO_INT_SHIFT (10) /* Bits 9-12: PIO interrupt bits */
#define PIO_INT_MASK (7 << PIO_INT_SHIFT)
# define _PIO_INT_AIM (1 << 10) /* Bit 10: Additional Interrupt modes */
# define _PIO_INT_LEVEL (1 << 9) /* Bit 9: Level detection interrupt */
# define _PIO_INT_EDGE (0) /* (vs. Edge detection interrupt) */
# define _PIO_INT_RH (1 << 8) /* Bit 9: Rising edge/High level detection interrupt */
# define _PIO_INT_FL (0) /* (vs. Falling edge/Low level detection interrupt) */
# define PIO_INT_HIGHLEVEL (_PIO_INT_AIM | _PIO_INT_LEVEL | _PIO_INT_RH)
# define PIO_INT_LOWLEVEL (_PIO_INT_AIM | _PIO_INT_LEVEL | _PIO_INT_FL)
# define PIO_INT_RISING (_PIO_INT_AIM | _PIO_INT_EDGE | _PIO_INT_RH)
# define PIO_INT_FALLING (_PIO_INT_AIM | _PIO_INT_EDGE | _PIO_INT_FL)
# define PIO_INT_BOTHEDGES (0)
/* If the pin is an interrupt, then this determines if the pin is a secure
* interrupt:
*
* .... .... .... .... .... ..S. .... ....
*/
#ifdef SAMA5_SAIC
# define PIO_INT_SECURE (1 << 9) /* Bit 9: Secure interrupt */
#else
# define PIO_INT_SECURE (0)
#endif
#define PIO_INT_UNSECURE (0)
/* If the pin is an PIO output, then this identifies the initial output
* value:
*
* .... .... .... .... .... ...V .... ....
*/
#define PIO_OUTPUT_SET (1 << 8) /* Bit 8: Initial value of output */
#define PIO_OUTPUT_CLEAR (0)
/* This identifies the PIO port:
*
* .... .... .... .... .... .... PPP. ....
*/
#define PIO_PORT_SHIFT (5) /* Bit 5-7: Port number */
#define PIO_PORT_MASK (7 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOA (0 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOB (1 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOC (2 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOD (3 << PIO_PORT_SHIFT)
# define PIO_PORT_PIOE (4 << PIO_PORT_SHIFT)
/* This identifies the bit in the port:
*
* .... .... .... .... .... .... ...B BBBB
*/
#define PIO_PIN_SHIFT (0) /* Bits 0-4: PIO number: 0-31 */
#define PIO_PIN_MASK (31 << PIO_PIN_SHIFT)
#define PIO_PIN0 (0 << PIO_PIN_SHIFT)
#define PIO_PIN1 (1 << PIO_PIN_SHIFT)
#define PIO_PIN2 (2 << PIO_PIN_SHIFT)
#define PIO_PIN3 (3 << PIO_PIN_SHIFT)
#define PIO_PIN4 (4 << PIO_PIN_SHIFT)
#define PIO_PIN5 (5 << PIO_PIN_SHIFT)
#define PIO_PIN6 (6 << PIO_PIN_SHIFT)
#define PIO_PIN7 (7 << PIO_PIN_SHIFT)
#define PIO_PIN8 (8 << PIO_PIN_SHIFT)
#define PIO_PIN9 (9 << PIO_PIN_SHIFT)
#define PIO_PIN10 (10 << PIO_PIN_SHIFT)
#define PIO_PIN11 (11 << PIO_PIN_SHIFT)
#define PIO_PIN12 (12 << PIO_PIN_SHIFT)
#define PIO_PIN13 (13 << PIO_PIN_SHIFT)
#define PIO_PIN14 (14 << PIO_PIN_SHIFT)
#define PIO_PIN15 (15 << PIO_PIN_SHIFT)
#define PIO_PIN16 (16 << PIO_PIN_SHIFT)
#define PIO_PIN17 (17 << PIO_PIN_SHIFT)
#define PIO_PIN18 (18 << PIO_PIN_SHIFT)
#define PIO_PIN19 (19 << PIO_PIN_SHIFT)
#define PIO_PIN20 (20 << PIO_PIN_SHIFT)
#define PIO_PIN21 (21 << PIO_PIN_SHIFT)
#define PIO_PIN22 (22 << PIO_PIN_SHIFT)
#define PIO_PIN23 (23 << PIO_PIN_SHIFT)
#define PIO_PIN24 (24 << PIO_PIN_SHIFT)
#define PIO_PIN25 (25 << PIO_PIN_SHIFT)
#define PIO_PIN26 (26 << PIO_PIN_SHIFT)
#define PIO_PIN27 (27 << PIO_PIN_SHIFT)
#define PIO_PIN28 (28 << PIO_PIN_SHIFT)
#define PIO_PIN29 (29 << PIO_PIN_SHIFT)
#define PIO_PIN30 (30 << PIO_PIN_SHIFT)
#define PIO_PIN31 (31 << PIO_PIN_SHIFT)
/****************************************************************************
* Public Types
****************************************************************************/
/* Must be big enough to hold the 32-bit encoding */
typedef uint32_t pio_pinset_t;
#endif /* __ARCH_ARM_SRC_SAMA5_SAMA5D3X4X_PIO_H */

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/****************************************************************************
* arch/arm/src/sama5/sama5d3x_memorymap.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "mmu.h"
#include "hardware/sam_memorymap.h"
#include "sam_lcd.h"
#include "sam_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/* This table describes how to map a set of 1Mb pages to space the physical
* address space of the SAMA5.
*/
#ifndef CONFIG_ARCH_ROMPGTABLE
const struct section_mapping_s g_section_mapping[] =
{
/* SAMA5 Internal Memories */
/* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the
* beginning of the .text region must appear at address at the address
* specified in the VBAR. There are three ways to accomplish this:
*
* 1. By explicitly mapping the beginning of .text region with a page
* table entry so that the virtual address zero maps to the beginning
* of the .text region. VBAR == 0x0000:0000.
*
* 2. A second way is to map the use the AXI MATRIX remap register to
* map physical address zero to the beginning of the text region,
* either internal SRAM or EBI CS 0. Then we can set an identity
* mapping to map the boot region at 0x0000:0000 to virtual address
* 0x0000:00000. VBAR == 0x0000:0000.
*
* This method is used when booting from ISRAM or NOR FLASH. In
* that case, vectors must lie at the beginning of NOFR FLASH.
*
* 3. Set the Cortex-A5 VBAR register so that the vector table address
* is moved to a location other than 0x0000:0000.
*
* This is the method used when booting from SDRAM.
*
* - When executing from NOR FLASH, the first level bootloader is supposed
* to provide the AXI MATRIX mapping for us at boot time base on the
* state of the BMS pin. However, I have found that in the test
* environments that I use, I cannot always be assured of that physical
* address mapping.
*
* So we do both here. If we are executing from NOR FLASH, then we
* provide the MMU to map the physical address of FLASH to address
* 0x0000:0000;
*
* - If we are executing out of ISRAM, then the SAMA5 primary bootloader
* probably copied us into ISRAM and set the AXI REMAP bit for us.
*
* - If we are executing from external SDRAM, then a secondary bootloader
* must have loaded us into SDRAM. In this case, simply set the VBAR
* register to the address of the vector table (not necessary at the
* beginning or SDRAM).
*/
#if defined(CONFIG_ARCH_LOWVECTORS) && !defined(CONFIG_SAMA5_BOOT_ISRAM) && \
!defined(CONFIG_SAMA5_BOOT_SDRAM)
{ CONFIG_FLASH_START, 0x00000000,
MMU_ROMFLAGS, 1
},
#else
{ SAM_BOOTMEM_PSECTION, SAM_BOOTMEM_VSECTION,
SAM_BOOTMEM_MMUFLAGS, SAM_BOOTMEM_NSECTIONS
},
#endif
{ SAM_ROM_PSECTION, SAM_ROM_VSECTION,
SAM_ROM_MMUFLAGS, SAM_ROM_NSECTIONS
},
{ SAM_NFCSRAM_PSECTION, SAM_NFCSRAM_VSECTION,
SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS
},
#ifndef CONFIG_PAGING /* Internal SRAM is already fully mapped */
{ SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION,
SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS
},
#endif
{ SAM_SMD_PSECTION, SAM_SMD_VSECTION,
SAM_SMD_MMUFLAGS, SAM_SMD_NSECTIONS
},
{ SAM_UDPHSRAM_PSECTION, SAM_UDPHSRAM_VSECTION,
SAM_UDPHSRAM_MMUFLAGS, SAM_UDPHSRAM_NSECTIONS
},
{ SAM_UHPOHCI_PSECTION, SAM_UHPOHCI_VSECTION,
SAM_UHPOHCI_MMUFLAGS, SAM_UHPOHCI_NSECTIONS
},
{ SAM_UHPEHCI_PSECTION, SAM_UHPEHCI_VSECTION,
SAM_UHPEHCI_MMUFLAGS, SAM_UHPEHCI_NSECTIONS
},
{ SAM_AXIMX_PSECTION, SAM_AXIMX_VSECTION,
SAM_AXIMX_MMUFLAGS, SAM_AXIMX_NSECTIONS
},
{ SAM_DAP_PSECTION, SAM_DAP_VSECTION,
SAM_DAP_MMUFLAGS, SAM_DAP_NSECTIONS
},
/* SAMA5 CS0 External Memories */
#ifdef CONFIG_SAMA5_EBICS0
{ SAM_EBICS0_PSECTION, SAM_EBICS0_VSECTION,
SAM_EBICS0_MMUFLAGS, SAM_EBICS0_NSECTIONS
},
#endif
/* SAMA5 External SDRAM Memory. The SDRAM is not usable until it has been
* initialized. If we are running out of SDRAM now, we can assume that
* some second level boot loader has properly configured SRAM for us.
* In that case, we set the MMU flags for the final, fully cache-able
* state.
*
* Also, in this case, the mapping for the SDRAM was done in arm_head.S
* and need not be repeated here.
*
* If we are running from ISRAM or NOR flash, then we will need to
* configure the SDRAM ourselves. In this case, we set the MMU flags to
* the strongly ordered, non-cacheable state. We need this direct access
* to SDRAM in order to configure it. Once SDRAM has been initialized, it
* will be reconfigured in its final state.
*/
#ifdef NEED_SDRAM_MAPPING
{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
MMU_STRONGLY_ORDERED, SAM_DDRCS_NSECTIONS
},
#endif
/* SAMA5 CS1-3 External Memories */
#ifdef CONFIG_SAMA5_EBICS1
{ SAM_EBICS1_PSECTION, SAM_EBICS1_VSECTION,
SAM_EBICS1_MMUFLAGS, SAM_EBICS1_NSECTIONS
},
#endif
#ifdef CONFIG_SAMA5_EBICS2
{ SAM_EBICS2_PSECTION, SAM_EBICS2_VSECTION,
SAM_EBICS2_MMUFLAGS, SAM_EBICS2_NSECTIONS
},
#endif
#ifdef CONFIG_SAMA5_EBICS3
{ SAM_EBICS3_PSECTION, SAM_EBICS3_VSECTION,
SAM_EBICS3_MMUFLAGS, SAM_EBICS3_NSECTIONS
},
#endif
#ifdef CONFIG_SAMA5_HAVE_NAND
{ SAM_NFCCR_PSECTION, SAM_NFCCR_VSECTION,
SAM_NFCCR_MMUFLAGS, SAM_NFCCR_NSECTIONS
},
#endif
/* SAMA5 Internal Peripherals
*
* Naming of peripheral sections differs between the SAMA5D3 and SAMA5D4.
* There is nothing called SYSC in the SAMA5D4 memory map. The third
* peripheral section is un-named in the SAMA5D4 memory map, but I have
* chosen the name PERIPHC for this usage.
*/
{ SAM_PERIPHA_PSECTION, SAM_PERIPHA_VSECTION,
SAM_PERIPHA_MMUFLAGS, SAM_PERIPHA_NSECTIONS
},
{ SAM_PERIPHB_PSECTION, SAM_PERIPHB_VSECTION,
SAM_PERIPHB_MMUFLAGS, SAM_PERIPHB_NSECTIONS
},
{ SAM_SYSC_PSECTION, SAM_SYSC_VSECTION,
SAM_SYSC_MMUFLAGS, SAM_SYSC_NSECTIONS
},
/* LCDC Framebuffer. This entry reprograms a part of one of the above
* regions, making it non-cacheable and non-buffereable.
*
* If SDRAM will be reconfigured, then we will defer setup of the
* framebuffer until after the SDRAM remapping (since the framebuffer
* problem resides) in SDRAM.
*/
#if defined(CONFIG_SAMA5_LCDC) && !defined(NEED_SDRAM_REMAPPING)
{ CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE,
MMU_IOFLAGS, SAMA5_LCDC_FBNSECTIONS
},
#endif
};
/* The number of entries in the mapping table */
#define NMAPPINGS \
(sizeof(g_section_mapping) / sizeof(struct section_mapping_s))
const size_t g_num_mappings = NMAPPINGS;
#endif /* CONFIG_ARCH_ROMPGTABLE */
/* SAMA5 External SDRAM Memory. Final configuration. The SDRAM was
* configured in a temporary state to support low-level ininitialization.
* After the SDRAM has been fully initialized, this structure is used to
* set the SDRM in its final, fully cache-able state.
*/
#ifdef NEED_SDRAM_REMAPPING
const struct section_mapping_s g_operational_mapping[] =
{
/* This entry reprograms the SDRAM entry, making it cacheable and
* bufferable.
*/
{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
SAM_DDRCS_MMUFLAGS, SAM_DDRCS_NSECTIONS
},
/* LCDC Framebuffer. This entry reprograms a part of one of the above
* regions, making it non-cacheable and non-buffereable.
*/
#ifdef CONFIG_SAMA5_LCDC
{ CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE,
MMU_IOFLAGS, SAMA5_LCDC_FBNSECTIONS
},
#endif
};
/* The number of entries in the operational mapping table */
#define NREMAPPINGS \
(sizeof(g_operational_mapping) / sizeof(struct section_mapping_s))
const size_t g_num_opmappings = NREMAPPINGS;
#endif /* NEED_SDRAM_REMAPPING */
/****************************************************************************
* Public Functions
****************************************************************************/

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/****************************************************************************
* arch/arm/src/sama5/sama5d3x_periphclks.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAMAD53X_PERIPHCLKS_H
#define __ARCH_ARM_SRC_SAMA5_SAMAD53X_PERIPHCLKS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/irq.h>
#include "hardware/sam_pmc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Helper macros */
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCDR0)
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCDR1)
#define sam_isenabled0(s) (getreg32(SAM_PMC_PCER0) & (1 << (s)) != 0)
#define sam_isenabled1(s) (getreg32(SAM_PMC_PCER1) & (1 << ((s) - 32)) != 0)
#define sam_dbgu_enableclk() sam_enableperiph0(SAM_PID_DBGU)
#define sam_pit_enableclk() sam_enableperiph0(SAM_PID_PIT)
#define sam_wdt_enableclk() sam_enableperiph0(SAM_PID_WDT)
#define sam_hsmc_enableclk() sam_enableperiph0(SAM_PID_HSMC)
#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA)
#define sam_piob_enableclk() sam_enableperiph0(SAM_PID_PIOB)
#define sam_pioc_enableclk() sam_enableperiph0(SAM_PID_PIOC)
#define sam_piod_enableclk() sam_enableperiph0(SAM_PID_PIOD)
#define sam_pioe_enableclk() sam_enableperiph0(SAM_PID_PIOE)
#define sam_smd_enableclk() sam_enableperiph0(SAM_PID_SMD)
#define sam_usart0_enableclk() sam_enableperiph0(SAM_PID_USART0)
#define sam_usart1_enableclk() sam_enableperiph0(SAM_PID_USART1)
#define sam_usart2_enableclk() sam_enableperiph0(SAM_PID_USART2)
#define sam_usart3_enableclk() sam_enableperiph0(SAM_PID_USART3)
#define sam_uart0_enableclk() sam_enableperiph0(SAM_PID_UART0)
#define sam_uart1_enableclk() sam_enableperiph0(SAM_PID_UART1)
#define sam_twi0_enableclk() sam_enableperiph0(SAM_PID_TWI0)
#define sam_twi1_enableclk() sam_enableperiph0(SAM_PID_TWI1)
#define sam_twi2_enableclk() sam_enableperiph0(SAM_PID_TWI2)
#define sam_hsmci0_enableclk() sam_enableperiph0(SAM_PID_HSMCI0)
#define sam_hsmci1_enableclk() sam_enableperiph0(SAM_PID_HSMCI1)
#define sam_hsmci2_enableclk() sam_enableperiph0(SAM_PID_HSMCI2)
#define sam_spi0_enableclk() sam_enableperiph0(SAM_PID_SPI0)
#define sam_spi1_enableclk() sam_enableperiph0(SAM_PID_SPI1)
#define sam_tc0_enableclk() sam_enableperiph0(SAM_PID_TC0)
#define sam_tc1_enableclk() sam_enableperiph0(SAM_PID_TC1)
#define sam_pwm_enableclk() sam_enableperiph0(SAM_PID_PWM)
#define sam_adc_enableclk() sam_enableperiph0(SAM_PID_ADC)
#define sam_dmac0_enableclk() sam_enableperiph0(SAM_PID_DMAC0)
#define sam_dmac1_enableclk() sam_enableperiph0(SAM_PID_DMAC1)
#define sam_uhphs_enableclk() sam_enableperiph1(SAM_PID_UHPHS)
#define sam_udphs_enableclk() sam_enableperiph1(SAM_PID_UDPHS)
#define sam_gmac_enableclk() sam_enableperiph1(SAM_PID_GMAC)
#define sam_emac_enableclk() sam_enableperiph1(SAM_PID_EMAC)
#define sam_lcdc_enableclk() sam_enableperiph1(SAM_PID_LCDC)
#define sam_isi_enableclk() sam_enableperiph1(SAM_PID_ISI)
#define sam_ssc0_enableclk() sam_enableperiph1(SAM_PID_SSC0)
#define sam_ssc1_enableclk() sam_enableperiph1(SAM_PID_SSC1)
#define sam_can0_enableclk() sam_enableperiph1(SAM_PID_CAN0)
#define sam_can1_enableclk() sam_enableperiph1(SAM_PID_CAN1)
#define sam_sha_enableclk() sam_enableperiph1(SAM_PID_SHA)
#define sam_aes_enableclk() sam_enableperiph1(SAM_PID_AES)
#define sam_tdes_enableclk() sam_enableperiph1(SAM_PID_TDES)
#define sam_trng_enableclk() sam_enableperiph1(SAM_PID_TRNG)
#define sam_arm_enableclk() sam_enableperiph1(SAM_PID_ARM)
#define sam_aic_enableclk() sam_enableperiph1(SAM_PID_AIC)
#define sam_fuse_enableclk() sam_enableperiph1(SAM_PID_FUSE)
#define sam_mpddrc_enableclk() sam_enableperiph1(SAM_PID_MPDDRC)
#define sam_dbgu_disableclk() sam_disableperiph0(SAM_PID_DBGU)
#define sam_pit_disableclk() sam_disableperiph0(SAM_PID_PIT)
#define sam_wdt_disableclk() sam_disableperiph0(SAM_PID_WDT)
#define sam_hsmc_disableclk() sam_disableperiph0(SAM_PID_HSMC)
#define sam_pioa_disableclk() sam_disableperiph0(SAM_PID_PIOA)
#define sam_piob_disableclk() sam_disableperiph0(SAM_PID_PIOB)
#define sam_pioc_disableclk() sam_disableperiph0(SAM_PID_PIOC)
#define sam_piod_disableclk() sam_disableperiph0(SAM_PID_PIOD)
#define sam_pioe_disableclk() sam_disableperiph0(SAM_PID_PIOE)
#define sam_smd_disableclk() sam_disableperiph0(SAM_PID_SMD)
#define sam_usart0_disableclk() sam_disableperiph0(SAM_PID_USART0)
#define sam_usart1_disableclk() sam_disableperiph0(SAM_PID_USART1)
#define sam_usart2_disableclk() sam_disableperiph0(SAM_PID_USART2)
#define sam_usart3_disableclk() sam_disableperiph0(SAM_PID_USART3)
#define sam_uart0_disableclk() sam_disableperiph0(SAM_PID_UART0)
#define sam_uart1_disableclk() sam_disableperiph0(SAM_PID_UART1)
#define sam_twi0_disableclk() sam_disableperiph0(SAM_PID_TWI0)
#define sam_twi1_disableclk() sam_disableperiph0(SAM_PID_TWI1)
#define sam_twi2_disableclk() sam_disableperiph0(SAM_PID_TWI2)
#define sam_hsmci0_disableclk() sam_disableperiph0(SAM_PID_HSMCI0)
#define sam_hsmci1_disableclk() sam_disableperiph0(SAM_PID_HSMCI1)
#define sam_hsmci2_disableclk() sam_disableperiph0(SAM_PID_HSMCI2)
#define sam_spi0_disableclk() sam_disableperiph0(SAM_PID_SPI0)
#define sam_spi1_disableclk() sam_disableperiph0(SAM_PID_SPI1)
#define sam_tc0_disableclk() sam_disableperiph0(SAM_PID_TC0)
#define sam_tc1_disableclk() sam_disableperiph0(SAM_PID_TC1)
#define sam_pwm_disableclk() sam_disableperiph0(SAM_PID_PWM)
#define sam_adc_disableclk() sam_disableperiph0(SAM_PID_ADC)
#define sam_dmac0_disableclk() sam_disableperiph0(SAM_PID_DMAC0)
#define sam_dmac1_disableclk() sam_disableperiph0(SAM_PID_DMAC1)
#define sam_uhphs_disableclk() sam_disableperiph1(SAM_PID_UHPHS)
#define sam_udphs_disableclk() sam_disableperiph1(SAM_PID_UDPHS)
#define sam_gmac_disableclk() sam_disableperiph1(SAM_PID_GMAC)
#define sam_emac_disableclk() sam_disableperiph1(SAM_PID_EMAC)
#define sam_lcdc_disableclk() sam_disableperiph1(SAM_PID_LCDC)
#define sam_isi_disableclk() sam_disableperiph1(SAM_PID_ISI)
#define sam_ssc0_disableclk() sam_disableperiph1(SAM_PID_SSC0)
#define sam_ssc1_disableclk() sam_disableperiph1(SAM_PID_SSC1)
#define sam_can0_disableclk() sam_disableperiph1(SAM_PID_CAN0)
#define sam_can1_disableclk() sam_disableperiph1(SAM_PID_CAN1)
#define sam_sha_disableclk() sam_disableperiph1(SAM_PID_SHA)
#define sam_aes_disableclk() sam_disableperiph1(SAM_PID_AES)
#define sam_tdes_disableclk() sam_disableperiph1(SAM_PID_TDES)
#define sam_trng_disableclk() sam_disableperiph1(SAM_PID_TRNG)
#define sam_arm_disableclk() sam_disableperiph1(SAM_PID_ARM)
#define sam_aic_disableclk() sam_disableperiph1(SAM_PID_AIC)
#define sam_fuse_disableclk() sam_disableperiph1(SAM_PID_FUSE)
#define sam_mpddrc_disableclk() sam_disableperiph1(SAM_PID_MPDDRC)
#define sam_dbgu_isenabled() sam_isenabled0(SAM_PID_DBGU)
#define sam_pit_isenabled() sam_isenabled0(SAM_PID_PIT)
#define sam_wdt_isenabled() sam_isenabled0(SAM_PID_WDT)
#define sam_hsmc_isenabled() sam_isenabled0(SAM_PID_HSMC)
#define sam_pioa_isenabled() sam_isenabled0(SAM_PID_PIOA)
#define sam_piob_isenabled() sam_isenabled0(SAM_PID_PIOB)
#define sam_pioc_isenabled() sam_isenabled0(SAM_PID_PIOC)
#define sam_piod_isenabled() sam_isenabled0(SAM_PID_PIOD)
#define sam_pioe_isenabled() sam_isenabled0(SAM_PID_PIOE)
#define sam_smd_isenabled() sam_isenabled0(SAM_PID_SMD)
#define sam_usart0_isenabled() sam_isenabled0(SAM_PID_USART0)
#define sam_usart1_isenabled() sam_isenabled0(SAM_PID_USART1)
#define sam_usart2_isenabled() sam_isenabled0(SAM_PID_USART2)
#define sam_usart3_isenabled() sam_isenabled0(SAM_PID_USART3)
#define sam_uart0_isenabled() sam_isenabled0(SAM_PID_UART0)
#define sam_uart1_isenabled() sam_isenabled0(SAM_PID_UART1)
#define sam_twi0_isenabled() sam_isenabled0(SAM_PID_TWI0)
#define sam_twi1_isenabled() sam_isenabled0(SAM_PID_TWI1)
#define sam_twi2_isenabled() sam_isenabled0(SAM_PID_TWI2)
#define sam_hsmci0_isenabled() sam_isenabled0(SAM_PID_HSMCI0)
#define sam_hsmci1_isenabled() sam_isenabled0(SAM_PID_HSMCI1)
#define sam_hsmci2_isenabled() sam_isenabled0(SAM_PID_HSMCI2)
#define sam_spi0_isenabled() sam_isenabled0(SAM_PID_SPI0)
#define sam_spi1_isenabled() sam_isenabled0(SAM_PID_SPI1)
#define sam_tc0_isenabled() sam_isenabled0(SAM_PID_TC0)
#define sam_tc1_isenabled() sam_isenabled0(SAM_PID_TC1)
#define sam_pwm_isenabled() sam_isenabled0(SAM_PID_PWM)
#define sam_adc_isenabled() sam_isenabled0(SAM_PID_ADC)
#define sam_dmac0_isenabled() sam_isenabled0(SAM_PID_DMAC0)
#define sam_dmac1_isenabled() sam_isenabled0(SAM_PID_DMAC1)
#define sam_uhphs_isenabled() sam_isenabled1(SAM_PID_UHPHS)
#define sam_udphs_isenabled() sam_isenabled1(SAM_PID_UDPHS)
#define sam_gmac_isenabled() sam_isenabled1(SAM_PID_GMAC)
#define sam_emac_isenabled() sam_isenabled1(SAM_PID_EMAC)
#define sam_lcdc_isenabled() sam_isenabled1(SAM_PID_LCDC)
#define sam_isi_isenabled() sam_isenabled1(SAM_PID_ISI)
#define sam_ssc0_isenabled() sam_isenabled1(SAM_PID_SSC0)
#define sam_ssc1_isenabled() sam_isenabled1(SAM_PID_SSC1)
#define sam_can0_isenabled() sam_isenabled1(SAM_PID_CAN0)
#define sam_can1_isenabled() sam_isenabled1(SAM_PID_CAN1)
#define sam_sha_isenabled() sam_isenabled1(SAM_PID_SHA)
#define sam_aes_isenabled() sam_isenabled1(SAM_PID_AES)
#define sam_tdes_isenabled() sam_isenabled1(SAM_PID_TDES)
#define sam_trng_isenabled() sam_isenabled1(SAM_PID_TRNG)
#define sam_arm_isenabled() sam_isenabled1(SAM_PID_ARM)
#define sam_aic_isenabled() sam_isenabled1(SAM_PID_AIC)
#define sam_fuse_isenabled() sam_isenabled1(SAM_PID_FUSE)
#define sam_mpddrc_isenabled() sam_isenabled1(SAM_PID_MPDDRC)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SAMAD53X_PERIPHCLKS_H */

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/****************************************************************************
* arch/arm/src/sama5/sama5d4x_memorymap.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "mmu.h"
#include "hardware/sam_memorymap.h"
#include "sam_lcd.h"
#include "sam_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/* This table describes how to map a set of 1Mb pages to space the physical
* address space of the SAMA5.
*/
#ifndef CONFIG_ARCH_ROMPGTABLE
const struct section_mapping_s g_section_mapping[] =
{
/* SAMA5 Internal Memories */
/* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the
* beginning of the .text region must appear at address at the address
* specified in the VBAR. There are three ways to accomplish this:
*
* 1. By explicitly mapping the beginning of .text region with a page
* table entry so that the virtual address zero maps to the beginning
* of the .text region. VBAR == 0x0000:0000.
*
* 2. A second way is to map the use the AXI MATRIX remap register to
* map physical address zero to the beginning of the text region,
* either internal SRAM or EBI CS 0. Then we can set an identity
* mapping to map the boot region at 0x0000:0000 to virtual address
* 0x0000:00000. VBAR == 0x0000:0000.
*
* This method is used when booting from ISRAM or NOR FLASH. In
* that case, vectors must lie at the beginning of NOFR FLASH.
*
* 3. Set the Cortex-A5 VBAR register so that the vector table address
* is moved to a location other than 0x0000:0000.
*
* This is the method used when booting from SDRAM.
*
* - When executing from NOR FLASH, the first level bootloader is supposed
* to provide the AXI MATRIX mapping for us at boot time base on the
* state of the BMS pin. However, I have found that in the test
* environments that I use, I cannot always be assured of that physical
* address mapping.
*
* So we do both here. If we are executing from NOR FLASH, then we
* provide the MMU to map the physical address of FLASH to address
* 0x0000:0000;
*
* - If we are executing out of ISRAM, then the SAMA5 primary bootloader
* probably copied us into ISRAM and set the AXI REMAP bit for us.
*
* - If we are executing from external SDRAM, then a secondary bootloader
* must have loaded us into SDRAM. In this case, simply set the VBAR
* register to the address of the vector table (not necessary at the
* beginning or SDRAM).
*/
#if defined(CONFIG_ARCH_LOWVECTORS) && !defined(CONFIG_SAMA5_BOOT_ISRAM) && \
!defined(CONFIG_SAMA5_BOOT_SDRAM)
{ CONFIG_FLASH_START, 0x00000000,
MMU_ROMFLAGS, 1
},
#else
{ SAM_BOOTMEM_PSECTION, SAM_BOOTMEM_VSECTION,
SAM_BOOTMEM_MMUFLAGS, SAM_BOOTMEM_NSECTIONS
},
#endif
{ SAM_ROM_PSECTION, SAM_ROM_VSECTION,
SAM_ROM_MMUFLAGS, SAM_ROM_NSECTIONS
},
{ SAM_NFCSRAM_PSECTION, SAM_NFCSRAM_VSECTION,
SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS
},
#ifndef CONFIG_PAGING /* Internal SRAM is already fully mapped */
{ SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION,
SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS
},
#endif
{ SAM_VDEC_PSECTION, SAM_VDEC_VSECTION,
SAM_VDEC_MMUFLAGS, SAM_VDEC_NSECTIONS
},
{ SAM_SMD_PSECTION, SAM_SMD_VSECTION,
SAM_SMD_MMUFLAGS, SAM_SMD_NSECTIONS
},
{ SAM_UDPHSRAM_PSECTION, SAM_UDPHSRAM_VSECTION,
SAM_UDPHSRAM_MMUFLAGS, SAM_UDPHSRAM_NSECTIONS
},
{ SAM_UHPOHCI_PSECTION, SAM_UHPOHCI_VSECTION,
SAM_UHPOHCI_MMUFLAGS, SAM_UHPOHCI_NSECTIONS
},
{ SAM_UHPEHCI_PSECTION, SAM_UHPEHCI_VSECTION,
SAM_UHPEHCI_MMUFLAGS, SAM_UHPEHCI_NSECTIONS
},
{ SAM_AXIMX_PSECTION, SAM_AXIMX_VSECTION,
SAM_AXIMX_MMUFLAGS, SAM_AXIMX_NSECTIONS
},
{ SAM_DAP_PSECTION, SAM_DAP_VSECTION,
SAM_DAP_MMUFLAGS, SAM_DAP_NSECTIONS
},
{ SAM_L2CC_PSECTION, SAM_L2CC_VSECTION,
SAM_L2CC_MMUFLAGS, SAM_L2CC_NSECTIONS
},
/* SAMA5 CS0 External Memories */
#ifdef CONFIG_SAMA5_EBICS0
{ SAM_EBICS0_PSECTION, SAM_EBICS0_VSECTION,
SAM_EBICS0_MMUFLAGS, SAM_EBICS0_NSECTIONS
},
#endif
/* SAMA5 External SDRAM Memory.
* The SDRAM is not usable until it has been initialized.
* If we are running out of SDRAM now, we can assume that some second level
* boot loader has properly configured SRAM for us. In that case,
* we set the MMU flags for the final, fully cache-able state.
*
* Also, in this case, the mapping for the SDRAM was done in arm_head.S
* and need not be repeated here.
*
* If we are running from ISRAM or NOR flash, then we will need to
* configure the SDRAM ourselves. In this case, we set the MMU flags to
* the strongly ordered, non-cacheable state. We need this direct access
* to SDRAM in order to configure it. Once SDRAM has been initialized, it
* will be re- configured in its final state.
*/
#ifdef NEED_SDRAM_MAPPING
{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
MMU_STRONGLY_ORDERED, SAM_DDRCS_NSECTIONS
},
#endif
/* SAMA5 CS1-3 External Memories */
#ifdef CONFIG_SAMA5_EBICS1
{ SAM_EBICS1_PSECTION, SAM_EBICS1_VSECTION,
SAM_EBICS1_MMUFLAGS, SAM_EBICS1_NSECTIONS
},
#endif
#ifdef CONFIG_SAMA5_EBICS2
{ SAM_EBICS2_PSECTION, SAM_EBICS2_VSECTION,
SAM_EBICS2_MMUFLAGS, SAM_EBICS2_NSECTIONS
},
#endif
#ifdef CONFIG_SAMA5_EBICS3
{ SAM_EBICS3_PSECTION, SAM_EBICS3_VSECTION,
SAM_EBICS3_MMUFLAGS, SAM_EBICS3_NSECTIONS
},
#endif
#ifdef CONFIG_SAMA5_HAVE_NAND
{ SAM_NFCCR_PSECTION, SAM_NFCCR_VSECTION,
SAM_NFCCR_MMUFLAGS, SAM_NFCCR_NSECTIONS
},
#endif
/* SAMA5 Internal Peripherals
*
* Naming of peripheral sections differs between the SAMA5D3 and SAMA5D4.
* There is nothing called SYSC in the SAMA5D4 memory map. The third
* peripheral section is un-named in the SAMA5D4 memory map, but I have
* chosen the name PERIPHC for this usage.
*/
{ SAM_PERIPHA_PSECTION, SAM_PERIPHA_VSECTION,
SAM_PERIPHA_MMUFLAGS, SAM_PERIPHA_NSECTIONS
},
{ SAM_PERIPHB_PSECTION, SAM_PERIPHB_VSECTION,
SAM_PERIPHB_MMUFLAGS, SAM_PERIPHB_NSECTIONS
},
{ SAM_PERIPHC_PSECTION, SAM_PERIPHC_VSECTION,
SAM_PERIPHC_MMUFLAGS, SAM_PERIPHC_NSECTIONS
},
/* LCDC Framebuffer. This entry reprograms a part of one of the above
* regions, making it non-cacheable and non-buffereable.
*
* If SDRAM will be reconfigured, then we will defer setup of the
* framebuffer until after the SDRAM remapping (since the framebuffer
* problem resides) in SDRAM.
*/
#if defined(CONFIG_SAMA5_LCDC) && !defined(NEED_SDRAM_REMAPPING)
{ CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE,
MMU_IOFLAGS, SAMA5_LCDC_FBNSECTIONS
},
#endif
};
/* The number of entries in the mapping table */
#define NMAPPINGS \
(sizeof(g_section_mapping) / sizeof(struct section_mapping_s))
const size_t g_num_mappings = NMAPPINGS;
#endif /* CONFIG_ARCH_ROMPGTABLE */
/* SAMA5 External SDRAM Memory. Final configuration. The SDRAM was
* configured in a temporary state to support low-level ininitialization.
* After the SDRAM has been fully initialized, this structure is used to
* set the SDRM in its final, fully cache-able state.
*/
#ifdef NEED_SDRAM_REMAPPING
const struct section_mapping_s g_operational_mapping[] =
{
/* This entry reprograms the SDRAM entry, making it cacheable and
* bufferable.
*/
{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
SAM_DDRCS_MMUFLAGS, SAM_DDRCS_NSECTIONS
},
/* LCDC Framebuffer. This entry reprograms a part of one of the above
* regions, making it non-cacheable and non-buffereable.
*/
#ifdef CONFIG_SAMA5_LCDC
{ CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE,
MMU_IOFLAGS, SAMA5_LCDC_FBNSECTIONS
},
#endif
};
/* The number of entries in the operational mapping table */
#define NREMAPPINGS \
(sizeof(g_operational_mapping) / sizeof(struct section_mapping_s))
const size_t g_num_opmappings = NREMAPPINGS;
#endif /* NEED_SDRAM_REMAPPING */
/****************************************************************************
* Public Functions
****************************************************************************/

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/****************************************************************************
* arch/arm/src/sama5/sama5d4x_periphclks.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAMAD54X_PERIPHCLKS_H
#define __ARCH_ARM_SRC_SAMA5_SAMAD54X_PERIPHCLKS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/irq.h>
#include "hardware/sam_pmc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Helper macros */
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCDR0)
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCDR1)
#define sam_isenabled0(s) (getreg32(SAM_PMC_PCER0) & (1 << (s)) != 0)
#define sam_isenabled1(s) (getreg32(SAM_PMC_PCER1) & (1 << ((s) - 32)) != 0)
/* Enable peripheral clocking */
#define sam_arm_enableclk() sam_enableperiph0(SAM_PID_ARM)
#define sam_pit_enableclk() sam_enableperiph0(SAM_PID_PIT)
#define sam_wdt_enableclk() sam_enableperiph0(SAM_PID_WDT)
#define sam_piod_enableclk() sam_enableperiph0(SAM_PID_PIOD)
#define sam_usart0_enableclk() sam_enableperiph0(SAM_PID_USART0)
#define sam_usart1_enableclk() sam_enableperiph0(SAM_PID_USART1)
#define sam_xdmac0_enableclk() sam_enableperiph0(SAM_PID_XDMAC0)
#define sam_icm_enableclk() sam_enableperiph0(SAM_PID_ICM)
#define sam_cpkcc_enableclk() sam_enableperiph0(SAM_PID_CPKCC)
#define sam_aes_enableclk() sam_enableperiph0(SAM_PID_AES)
#define sam_aesb_enableclk() sam_enableperiph0(SAM_PID_AESB)
#define sam_tdes_enableclk() sam_enableperiph0(SAM_PID_TDES)
#define sam_sha_enableclk() sam_enableperiph0(SAM_PID_SHA)
#define sam_mpddrc_enableclk() sam_enableperiph0(SAM_PID_MPDDRC)
#define sam_matrix1_enableclk() sam_enableperiph0(SAM_PID_MATRIX1)
#define sam_matrix0_enableclk() sam_enableperiph0(SAM_PID_MATRIX0)
#define sam_vdec_enableclk() sam_enableperiph0(SAM_PID_VDEC)
#define sam_sbm_enableclk() sam_enableperiph0(SAM_PID_SBM)
#define sam_hsmc_enableclk() sam_enableperiph0(SAM_PID_HSMC)
#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA)
#define sam_piob_enableclk() sam_enableperiph0(SAM_PID_PIOB)
#define sam_pioc_enableclk() sam_enableperiph0(SAM_PID_PIOC)
#define sam_pioe_enableclk() sam_enableperiph0(SAM_PID_PIOE)
#define sam_uart0_enableclk() sam_enableperiph0(SAM_PID_UART0)
#define sam_uart1_enableclk() sam_enableperiph0(SAM_PID_UART1)
#define sam_usart2_enableclk() sam_enableperiph0(SAM_PID_USART2)
#define sam_usart3_enableclk() sam_enableperiph0(SAM_PID_USART3)
#define sam_usart4_enableclk() sam_enableperiph0(SAM_PID_USART4)
#define sam_twi0_enableclk() sam_enableperiph1(SAM_PID_TWI0)
#define sam_twi1_enableclk() sam_enableperiph1(SAM_PID_TWI1)
#define sam_twi2_enableclk() sam_enableperiph1(SAM_PID_TWI2)
#define sam_hsmci0_enableclk() sam_enableperiph1(SAM_PID_HSMCI0)
#define sam_hsmci1_enableclk() sam_enableperiph1(SAM_PID_HSMCI1)
#define sam_spi0_enableclk() sam_enableperiph1(SAM_PID_SPI0)
#define sam_spi1_enableclk() sam_enableperiph1(SAM_PID_SPI1)
#define sam_spi2_enableclk() sam_enableperiph1(SAM_PID_SPI2)
#define sam_tc0_enableclk() sam_enableperiph1(SAM_PID_TC0)
#define sam_tc1_enableclk() sam_enableperiph1(SAM_PID_TC1)
#define sam_tc2_enableclk() sam_enableperiph1(SAM_PID_TC2)
#define sam_pwm_enableclk() sam_enableperiph1(SAM_PID_PWM)
#define sam_adc_enableclk() sam_enableperiph1(SAM_PID_ADC)
#define sam_dbgu_enableclk() sam_enableperiph1(SAM_PID_DBGU)
#define sam_uhphs_enableclk() sam_enableperiph1(SAM_PID_UHPHS)
#define sam_udphs_enableclk() sam_enableperiph1(SAM_PID_UDPHS)
#define sam_ssc0_enableclk() sam_enableperiph1(SAM_PID_SSC0)
#define sam_ssc1_enableclk() sam_enableperiph1(SAM_PID_SSC1)
#define sam_xdmac1_enableclk() sam_enableperiph1(SAM_PID_XDMAC1)
#define sam_lcdc_enableclk() sam_enableperiph1(SAM_PID_LCDC)
#define sam_isi_enableclk() sam_enableperiph1(SAM_PID_ISI)
#define sam_trng_enableclk() sam_enableperiph1(SAM_PID_TRNG)
#define sam_emac0_enableclk() sam_enableperiph1(SAM_PID_EMAC0)
#define sam_emac1_enableclk() sam_enableperiph1(SAM_PID_EMAC1)
#define sam_aicid_enableclk() sam_enableperiph1(SAM_PID_AICID)
#define sam_sfc_enableclk() sam_enableperiph1(SAM_PID_SFC)
#define sam_secureram_enableclk() sam_enableperiph1(SAM_PID_SECURAM)
#define sam_smd_enableclk() sam_enableperiph1(SAM_PID_SMD)
#define sam_twi3_enableclk() sam_enableperiph1(SAM_PID_TWI3)
#define sam_catb_enableclk() sam_enableperiph1(SAM_PID_CATB)
/* The Advanced Interrupt Controller and L2CC cache controllers are
* continuously clocked. The Power Management Controller has no effect on
* their behavior.
*
* (I presume that this is true of the SFR as well since it has no PMC
* bits to control its clocking).
*/
#define sam_sfr_enableclk()
#define sam_aic_enableclk()
#define sam_saic_enableclk()
#define sam_l2cc_enableclk()
/* Disable peripheral clocking */
#define sam_arm_disableclk() sam_disableperiph0(SAM_PID_ARM)
#define sam_pit_disableclk() sam_disableperiph0(SAM_PID_PIT)
#define sam_wdt_disableclk() sam_disableperiph0(SAM_PID_WDT)
#define sam_piod_disableclk() sam_disableperiph0(SAM_PID_PIOD)
#define sam_usart0_disableclk() sam_disableperiph0(SAM_PID_USART0)
#define sam_usart1_disableclk() sam_disableperiph0(SAM_PID_USART1)
#define sam_xdmac0_disableclk() sam_disableperiph0(SAM_PID_XDMAC0)
#define sam_icm_disableclk() sam_disableperiph0(SAM_PID_ICM)
#define sam_cpkcc_disableclk() sam_disableperiph0(SAM_PID_CPKCC)
#define sam_aes_disableclk() sam_disableperiph0(SAM_PID_AES)
#define sam_aesb_disableclk() sam_disableperiph0(SAM_PID_AESB)
#define sam_tdes_disableclk() sam_disableperiph0(SAM_PID_TDES)
#define sam_sha_disableclk() sam_disableperiph0(SAM_PID_SHA)
#define sam_mpddrc_disableclk() sam_disableperiph0(SAM_PID_MPDDRC)
#define sam_matrix1_disableclk() sam_disableperiph0(SAM_PID_MATRIX1)
#define sam_matrix0_disableclk() sam_disableperiph0(SAM_PID_MATRIX0)
#define sam_vdec_disableclk() sam_disableperiph0(SAM_PID_VDEC)
#define sam_sbm_disableclk() sam_disableperiph0(SAM_PID_SBM)
#define sam_hsmc_disableclk() sam_disableperiph0(SAM_PID_HSMC)
#define sam_pioa_disableclk() sam_disableperiph0(SAM_PID_PIOA)
#define sam_piob_disableclk() sam_disableperiph0(SAM_PID_PIOB)
#define sam_pioc_disableclk() sam_disableperiph0(SAM_PID_PIOC)
#define sam_pioe_disableclk() sam_disableperiph0(SAM_PID_PIOE)
#define sam_uart0_disableclk() sam_disableperiph0(SAM_PID_UART0)
#define sam_uart1_disableclk() sam_disableperiph0(SAM_PID_UART1)
#define sam_usart2_disableclk() sam_disableperiph0(SAM_PID_USART2)
#define sam_usart3_disableclk() sam_disableperiph0(SAM_PID_USART3)
#define sam_usart4_disableclk() sam_disableperiph0(SAM_PID_USART4)
#define sam_twi0_disableclk() sam_disableperiph1(SAM_PID_TWI0)
#define sam_twi1_disableclk() sam_disableperiph1(SAM_PID_TWI1)
#define sam_twi2_disableclk() sam_disableperiph1(SAM_PID_TWI2)
#define sam_hsmci0_disableclk() sam_disableperiph1(SAM_PID_HSMCI0)
#define sam_hsmci1_disableclk() sam_disableperiph1(SAM_PID_HSMCI1)
#define sam_spi0_disableclk() sam_disableperiph1(SAM_PID_SPI0)
#define sam_spi1_disableclk() sam_disableperiph1(SAM_PID_SPI1)
#define sam_spi2_disableclk() sam_disableperiph1(SAM_PID_SPI2)
#define sam_tc0_disableclk() sam_disableperiph1(SAM_PID_TC0)
#define sam_tc1_disableclk() sam_disableperiph1(SAM_PID_TC1)
#define sam_tc2_disableclk() sam_disableperiph1(SAM_PID_TC2)
#define sam_pwm_disableclk() sam_disableperiph1(SAM_PID_PWM)
#define sam_adc_disableclk() sam_disableperiph1(SAM_PID_ADC)
#define sam_dbgu_disableclk() sam_disableperiph1(SAM_PID_DBGU)
#define sam_uhphs_disableclk() sam_disableperiph1(SAM_PID_UHPHS)
#define sam_udphs_disableclk() sam_disableperiph1(SAM_PID_UDPHS)
#define sam_ssc0_disableclk() sam_disableperiph1(SAM_PID_SSC0)
#define sam_ssc1_disableclk() sam_disableperiph1(SAM_PID_SSC1)
#define sam_xdmac1_disableclk() sam_disableperiph1(SAM_PID_XDMAC1)
#define sam_lcdc_disableclk() sam_disableperiph1(SAM_PID_LCDC)
#define sam_isi_disableclk() sam_disableperiph1(SAM_PID_ISI)
#define sam_trng_disableclk() sam_disableperiph1(SAM_PID_TRNG)
#define sam_emac0_disableclk() sam_disableperiph1(SAM_PID_EMAC0)
#define sam_emac1_disableclk() sam_disableperiph1(SAM_PID_EMAC1)
#define sam_aicid_disableclk() sam_disableperiph1(SAM_PID_AICID)
#define sam_sfc_disableclk() sam_disableperiph1(SAM_PID_SFC)
#define sam_secureram_disableclk() sam_disableperiph1(SAM_PID_SECURAM)
#define sam_smd_disableclk() sam_disableperiph1(SAM_PID_SMD)
#define sam_twi3_disableclk() sam_disableperiph1(SAM_PID_TWI3)
#define sam_catb_disableclk() sam_disableperiph1(SAM_PID_CATB)
/* The Advanced Interrupt Controller and L2CC cache controllers are
* continuously clocked. The Power Management Controller has no effect on
* their behavior.
*
* (I presume that this is true of the SFR as well since it has no PMC
* bits to control its clocking).
*/
#define sam_sfr_disableclk()
#define sam_aic_disableclk()
#define sam_saic_disableclk()
#define sam_l2cc_disableclk()
/* Test if peripheral clocking is enabled */
#define sam_arm_isenabled() sam_isenabled0(SAM_PID_ARM)
#define sam_pit_isenabled() sam_isenabled0(SAM_PID_PIT)
#define sam_wdt_isenabled() sam_isenabled0(SAM_PID_WDT)
#define sam_piod_isenabled() sam_isenabled0(SAM_PID_PIOD)
#define sam_usart0_isenabled() sam_isenabled0(SAM_PID_USART0)
#define sam_usart1_isenabled() sam_isenabled0(SAM_PID_USART1)
#define sam_xdmac0_isenabled() sam_isenabled0(SAM_PID_XDMAC0)
#define sam_icm_isenabled() sam_isenabled0(SAM_PID_ICM)
#define sam_cpkcc_isenabled() sam_isenabled0(SAM_PID_CPKCC)
#define sam_aes_isenabled() sam_isenabled0(SAM_PID_AES)
#define sam_aesb_isenabled() sam_isenabled0(SAM_PID_AESB)
#define sam_tdes_isenabled() sam_isenabled0(SAM_PID_TDES)
#define sam_sha_isenabled() sam_isenabled0(SAM_PID_SHA)
#define sam_mpddrc_isenabled() sam_isenabled0(SAM_PID_MPDDRC)
#define sam_matrix1_isenabled() sam_isenabled0(SAM_PID_MATRIX1)
#define sam_matrix0_isenabled() sam_isenabled0(SAM_PID_MATRIX0)
#define sam_vdec_isenabled() sam_isenabled0(SAM_PID_VDEC)
#define sam_sbm_isenabled() sam_isenabled0(SAM_PID_SBM)
#define sam_hsmc_isenabled() sam_isenabled0(SAM_PID_HSMC)
#define sam_pioa_isenabled() sam_isenabled0(SAM_PID_PIOA)
#define sam_piob_isenabled() sam_isenabled0(SAM_PID_PIOB)
#define sam_pioc_isenabled() sam_isenabled0(SAM_PID_PIOC)
#define sam_pioe_isenabled() sam_isenabled0(SAM_PID_PIOE)
#define sam_uart0_isenabled() sam_isenabled0(SAM_PID_UART0)
#define sam_uart1_isenabled() sam_isenabled0(SAM_PID_UART1)
#define sam_usart2_isenabled() sam_isenabled0(SAM_PID_USART2)
#define sam_usart3_isenabled() sam_isenabled0(SAM_PID_USART3)
#define sam_usart4_isenabled() sam_isenabled0(SAM_PID_USART4)
#define sam_twi0_isenabled() sam_isenabled1(SAM_PID_TWI0)
#define sam_twi1_isenabled() sam_isenabled1(SAM_PID_TWI1)
#define sam_twi2_isenabled() sam_isenabled1(SAM_PID_TWI2)
#define sam_hsmci0_isenabled() sam_isenabled1(SAM_PID_HSMCI0)
#define sam_hsmci1_isenabled() sam_isenabled1(SAM_PID_HSMCI1)
#define sam_spi0_isenabled() sam_isenabled1(SAM_PID_SPI0)
#define sam_spi1_isenabled() sam_isenabled1(SAM_PID_SPI1)
#define sam_spi2_isenabled() sam_isenabled1(SAM_PID_SPI2)
#define sam_tc0_isenabled() sam_isenabled1(SAM_PID_TC0)
#define sam_tc1_isenabled() sam_isenabled1(SAM_PID_TC1)
#define sam_tc2_isenabled() sam_isenabled1(SAM_PID_TC2)
#define sam_pwm_isenabled() sam_isenabled1(SAM_PID_PWM)
#define sam_adc_isenabled() sam_isenabled1(SAM_PID_ADC)
#define sam_dbgu_isenabled() sam_isenabled1(SAM_PID_DBGU)
#define sam_uhphs_isenabled() sam_isenabled1(SAM_PID_UHPHS)
#define sam_udphs_isenabled() sam_isenabled1(SAM_PID_UDPHS)
#define sam_ssc0_isenabled() sam_isenabled1(SAM_PID_SSC0)
#define sam_ssc1_isenabled() sam_isenabled1(SAM_PID_SSC1)
#define sam_xdmac1_isenabled() sam_isenabled1(SAM_PID_XDMAC1)
#define sam_lcdc_isenabled() sam_isenabled1(SAM_PID_LCDC)
#define sam_isi_isenabled() sam_isenabled1(SAM_PID_ISI)
#define sam_trng_isenabled() sam_isenabled1(SAM_PID_TRNG)
#define sam_emac0_isenabled() sam_isenabled1(SAM_PID_EMAC0)
#define sam_emac1_isenabled() sam_isenabled1(SAM_PID_EMAC1)
#define sam_aicid_isenabled() sam_isenabled1(SAM_PID_AICID)
#define sam_sfc_isenabled() sam_isenabled1(SAM_PID_SFC)
#define sam_secureram_isenabled() sam_isenabled1(SAM_PID_SECURAM)
#define sam_smd_isenabled() sam_isenabled1(SAM_PID_SMD)
#define sam_twi3_isenabled() sam_isenabled1(SAM_PID_TWI3)
#define sam_catb_isenabled() sam_isenabled1(SAM_PID_CATB)
/* The Advanced Interrupt Controller and L2CC cache controllers are
* continuously clocked. The Power Management Controller has no effect on
* their behavior.
*
* (I presume that this is true of the SFR as well since it has no PMC
* bits to control its clocking).
*/
#define sam_sfr_isenabled() (true)
#define sam_aic_isenabled() (true)
#define sam_saic_isenabled() (true)
#define sam_l2cc_isenabled() (true)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SAMAD54X_PERIPHCLKS_H */

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#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
comment "Atmel SAMD/L Configuration Options"
choice
prompt "Atmel SAMD/L Chip Selection"
default ARCH_CHIP_SAMD20J18 if ARCH_CHIP_SAMD2X
default ARCH_CHIP_SAMD21J18A if ARCH_CHIP_SAML2X
depends on ARCH_CHIP_SAMD2X || ARCH_CHIP_SAML2X
config ARCH_CHIP_SAMD20E14
bool "SAMD20E14"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD20
select ARCH_FAMILY_SAMD20E
---help---
Flash 16KB SRAM 2KB
config ARCH_CHIP_SAMD20E15
bool "SAMD20E15"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD20
select ARCH_FAMILY_SAMD20E
---help---
Flash 32KB SRAM 4KB
config ARCH_CHIP_SAMD20E16
bool "SAMD20E16"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD20
select ARCH_FAMILY_SAMD20E
---help---
Flash 64KB SRAM 8KB
config ARCH_CHIP_SAMD20E17
bool "SAMD20E17"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD20
select ARCH_FAMILY_SAMD20E
---help---
Flash 128KB SRAM 16KB
config ARCH_CHIP_SAMD20E18
bool "SAMD20E18"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD20
select ARCH_FAMILY_SAMD20E
---help---
Flash 256KB SRAM 32KB
config ARCH_CHIP_SAMD20G14
bool "SAMD20G14"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD20
select ARCH_FAMILY_SAMD20G
---help---
Flash 16KB SRAM 2KB
config ARCH_CHIP_SAMD20G15
bool "SAMD20G15"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD20
select ARCH_FAMILY_SAMD20G
---help---
Flash 32KB SRAM 4KB
config ARCH_CHIP_SAMD20G16
bool "SAMD20G16"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD20
select ARCH_FAMILY_SAMD20G
---help---
Flash 64KB SRAM 8KB
config ARCH_CHIP_SAMD20G17
bool "SAMD20G17"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD20
select ARCH_FAMILY_SAMD20G
---help---
Flash 128KB SRAM 16KB
config ARCH_CHIP_SAMD20G18
bool "SAMD20G18"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD20
select ARCH_FAMILY_SAMD20G
---help---
Flash 256KB SRAM 32KB
config ARCH_CHIP_SAMD20J14
bool "SAMD20J14"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD20
select ARCH_FAMILY_SAMD20J
---help---
Flash 16KB SRAM 2KB
config ARCH_CHIP_SAMD20J15
bool "SAMD20J15"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD20
select ARCH_FAMILY_SAMD20J
---help---
Flash 32KB SRAM 4KB
config ARCH_CHIP_SAMD20J16
bool "SAMD20J16"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD20
select ARCH_FAMILY_SAMD20J
---help---
Flash 64KB SRAM 8KB
config ARCH_CHIP_SAMD20J17
bool "SAMD20J17"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD20
select ARCH_FAMILY_SAMD20J
---help---
Flash 128KB SRAM 16KB
config ARCH_CHIP_SAMD20J18
bool "SAMD20J18"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD20
select ARCH_FAMILY_SAMD20J
---help---
Flash 256KB SRAM 32KB
config ARCH_CHIP_SAMD21E15A
bool "SAMD21E15A"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD21
select ARCH_FAMILY_SAMD21E
---help---
Flash 32KB SRAM 4KB
config ARCH_CHIP_SAMD21E15B
bool "SAMD21E15B"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD21
select ARCH_FAMILY_SAMD21E
---help---
Flash 32KB SRAM 4KB RWW FLASH 1KB
config ARCH_CHIP_SAMD21E16A
bool "SAMD21E16A"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD21
select ARCH_FAMILY_SAMD21E
---help---
Flash 64KB SRAM 8KB
config ARCH_CHIP_SAMD21E16B
bool "SAMD21E16B"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD21
select ARCH_FAMILY_SAMD21E
---help---
Flash 64KB SRAM 8KB RWW FLASH 2KB
config ARCH_CHIP_SAMD21E17A
bool "SAMD21E17A"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD21
select ARCH_FAMILY_SAMD21E
---help---
Flash 128KB SRAM 16KB
config ARCH_CHIP_SAMD21E18A
bool "SAMD21E18A"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD21
select ARCH_FAMILY_SAMD21E
---help---
Flash 256KB SRAM 32KB
config ARCH_CHIP_SAMD21G15A
bool "SAMD21G15A"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD21
select ARCH_FAMILY_SAMD21G
---help---
Flash 32KB SRAM 4KB
config ARCH_CHIP_SAMD21G15B
bool "SAMD21G15B"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD21
select ARCH_FAMILY_SAMD21G
---help---
Flash 32KB SRAM 4KB RWW FLASH 1KB
config ARCH_CHIP_SAMD21G16A
bool "SAMD21G16A"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD21
select ARCH_FAMILY_SAMD21G
---help---
Flash 64KB SRAM 8KB
config ARCH_CHIP_SAMD21G16B
bool "SAMD21G16B"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD21
select ARCH_FAMILY_SAMD21E
---help---
Flash 64KB SRAM 8KB RWW FLASH 2KB
config ARCH_CHIP_SAMD21G17A
bool "SAMD21G17A"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD21
select ARCH_FAMILY_SAMD21G
---help---
Flash 128KB SRAM 16KB
config ARCH_CHIP_SAMD21G18A
bool "SAMD21G18A"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD21
select ARCH_FAMILY_SAMD21G
---help---
Flash 256KB SRAM 32KB
config ARCH_CHIP_SAMD21J15A
bool "SAMD21J15A"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD21
select ARCH_FAMILY_SAMD21J
---help---
Flash 32KB SRAM 4KB
config ARCH_CHIP_SAMD21J15B
bool "SAMD21J15B"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD21
select ARCH_FAMILY_SAMD21J
---help---
Flash 32KB SRAM 4KB RWW FLASH 1KB
config ARCH_CHIP_SAMD21J16A
bool "SAMD21J16A"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD21
select ARCH_FAMILY_SAMD21J
---help---
Flash 64KB SRAM 8KB
config ARCH_CHIP_SAMD21J16B
bool "SAMD21J16B"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD21
select ARCH_FAMILY_SAMD21J
---help---
Flash 64KB SRAM 8KB RWW FLASH 2KB
config ARCH_CHIP_SAMD21J17A
bool "SAMD21J17A"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD21
select ARCH_FAMILY_SAMD21E
---help---
Flash 128KB SRAM 16KB
config ARCH_CHIP_SAMD21J18A
bool "SAMD21J18A"
depends on ARCH_CHIP_SAMD2X
select ARCH_FAMILY_SAMD21
select ARCH_FAMILY_SAMD21J
---help---
Flash 256KB SRAM 32KB
config ARCH_CHIP_SAML21E15
bool "SAML21E15"
depends on ARCH_CHIP_SAML2X
select ARCH_FAMILY_SAML21
select ARCH_FAMILY_SAML21E
---help---
Flash 32KB SRAM 4KB
config ARCH_CHIP_SAML21E16
bool "SAML21E16"
depends on ARCH_CHIP_SAML2X
select ARCH_FAMILY_SAML21
select ARCH_FAMILY_SAML21E
---help---
Flash 64KB SRAM 8KB
config ARCH_CHIP_SAML21E17
bool "SAML21E17"
depends on ARCH_CHIP_SAML2X
select ARCH_FAMILY_SAML21
select ARCH_FAMILY_SAML21E
---help---
Flash 128KB SRAM 16KB
config ARCH_CHIP_SAML21E18
bool "SAML21E18"
depends on ARCH_CHIP_SAML2X
select ARCH_FAMILY_SAML21
select ARCH_FAMILY_SAML21E
---help---
Flash 256KB SRAM 32KB
config ARCH_CHIP_SAML21G16
bool "SAML21G16"
depends on ARCH_CHIP_SAML2X
select ARCH_FAMILY_SAML21
select ARCH_FAMILY_SAML21G
---help---
Flash 64KB SRAM 4KB
config ARCH_CHIP_SAML21G17
bool "SAML21G17"
depends on ARCH_CHIP_SAML2X
select ARCH_FAMILY_SAML21
select ARCH_FAMILY_SAML21G
---help---
Flash 128KB SRAM 16KB
config ARCH_CHIP_SAML21G18
bool "SAML21G18"
depends on ARCH_CHIP_SAML2X
select ARCH_FAMILY_SAML21
select ARCH_FAMILY_SAML21G
---help---
Flash 256KB SRAM 32KB
config ARCH_CHIP_SAML21J16
bool "SAML21J16"
depends on ARCH_CHIP_SAML2X
select ARCH_FAMILY_SAML21
select ARCH_FAMILY_SAML21J
---help---
Flash 64KB SRAM 4KB
config ARCH_CHIP_SAML21J17
bool "SAML21J17"
depends on ARCH_CHIP_SAML2X
select ARCH_FAMILY_SAML21
select ARCH_FAMILY_SAML21J
---help---
Flash 128KB SRAM 16KB
config ARCH_CHIP_SAML21J18
bool "SAML21J18"
depends on ARCH_CHIP_SAML2X
select ARCH_FAMILY_SAML21
select ARCH_FAMILY_SAML21J
---help---
Flash 256KB SRAM 32KB
endchoice
config ARCH_FAMILY_SAMD20
bool
default n
select SAMD2L2_HAVE_TC2
select SAMD2L2_HAVE_TC3
select SAMD2L2_HAVE_TC5
config ARCH_FAMILY_SAMD20E
bool
default n
config ARCH_FAMILY_SAMD20G
bool
default n
select SAMD2L2_HAVE_SERCOM4
select SAMD2L2_HAVE_SERCOM5
config ARCH_FAMILY_SAMD20J
bool
default n
select SAMD2L2_HAVE_SERCOM4
select SAMD2L2_HAVE_SERCOM5
select SAMD2L2_HAVE_TC6
select SAMD2L2_HAVE_TC7
config ARCH_FAMILY_SAMD21
bool
default n
select SAMD2L2_HAVE_DMAC
select SAMD2L2_HAVE_USB
config ARCH_FAMILY_SAMD21E
bool
default n
config ARCH_FAMILY_SAMD21G
bool
default n
select SAMD2L2_HAVE_SERCOM4
select SAMD2L2_HAVE_SERCOM5
config ARCH_FAMILY_SAMD21J
bool
default n
select SAMD2L2_HAVE_SERCOM4
select SAMD2L2_HAVE_SERCOM5
select SAMD2L2_HAVE_TC2
select SAMD2L2_HAVE_TC3
select SAMD2L2_HAVE_TC5
config ARCH_FAMILY_SAML21
bool
default n
select SAMD2L2_HAVE_DMAC
select SAMD2L2_HAVE_USB
config ARCH_FAMILY_SAML21E
bool
default n
config ARCH_FAMILY_SAML21G
bool
default n
select SAMD2L2_HAVE_SERCOM4
select SAMD2L2_HAVE_SERCOM5
config ARCH_FAMILY_SAML21J
bool
default n
select SAMD2L2_HAVE_SERCOM4
select SAMD2L2_HAVE_SERCOM5
select SAMD2L2_HAVE_TC2
select SAMD2L2_HAVE_TC3
select SAMD2L2_HAVE_TC5
menu "SAMD/L Peripheral Support"
config SAMD2L2_HAVE_DMAC
bool
default n
config SAMD2L2_HAVE_SERCOM4
bool
default n
config SAMD2L2_HAVE_SERCOM5
bool
default n
config SAMD2L2_HAVE_TC5
bool
default n
config SAMD2L2_HAVE_TC2
bool
default n
config SAMD2L2_HAVE_TC3
bool
default n
config SAMD2L2_HAVE_TC6
bool
default n
config SAMD2L2_HAVE_TC7
bool
default n
config SAMD2L2_HAVE_USB
bool
default n
config SAMD2L2_AC
bool "Analog Comparator"
default n
config SAMD2L2_ADC
bool "Analog-to-Digital Converter"
default n
config SAMD2L2_DAC
bool "Digital-to-Analog Converter"
default n
config SAMD2L2_DMAC
bool "DMA Controller"
default n
select ARCH_DMA
depends on SAMD2L2_HAVE_DMAC && EXPERIMENTAL
config SAMD2L2_EVSYS
bool "Event System"
default n
config SAMD2L2_NVMCTRL
bool "Non-Volatile Memory Controller"
default n
config SAMD2L2_PTC
bool "Peripheral Touch Controller"
default n
config SAMD2L2_RTC
bool "Real Time Counter"
default n
config SAMD2L2_SERCOM0
bool "Serial Communication Interface 0"
default n
config SAMD2L2_SERCOM1
bool "Serial Communication Interface 1"
default n
config SAMD2L2_SERCOM2
bool "Serial Communication Interface 2"
default n
config SAMD2L2_SERCOM3
bool "Serial Communication Interface 3"
default n
config SAMD2L2_SERCOM4
bool "Serial Communication Interface 4"
default n
depends on SAMD2L2_HAVE_SERCOM4
config SAMD2L2_SERCOM5
bool "Serial Communication Interface 5"
default n
depends on SAMD2L2_HAVE_SERCOM5
config SAMD2L2_TC0
bool "Timer/Counter 0"
default n
config SAMD2L2_TC1
bool "Timer/Counter 1"
default n
config SAMD2L2_TC2
bool "Timer/Counter 2"
default n
depends on SAMD2L2_HAVE_TC2
config SAMD2L2_TC3
bool "Timer/Counter 3"
default n
depends on SAMD2L2_HAVE_TC3
config SAMD2L2_TC4
bool "Timer/Counter 4"
default n
config SAMD2L2_TC5
bool "Timer/Counter 5"
default n
depends on SAMD2L2_HAVE_TC5
config SAMD2L2_TC6
bool "Timer/Counter 6"
default n
depends on SAMD2L2_HAVE_TC6
config SAMD2L2_TC7
bool "Timer/Counter 7"
default n
depends on SAMD2L2_HAVE_TC7
config SAMD2L2_USB
bool "USB"
default n
depends on SAMD2L2_HAVE_USB
config SAMD2L2_EIC
bool "External Interrupt Controller"
default n
config SAMD2L2_WDT
bool "Watchdog Timer"
default n
endmenu
config SAMD2L2_DMAC_NDESC
int "Number of additional DMA Descriptors"
default 0
depends on SAMD2L2_DMAC
---help---
This provides the number of additional DMA descriptors that can be
use to support multi-linked DMA transfers. A minimum of 16
descriptors will always be allocated (16 for the base descriptor which
overlap the writeback descriptors). If this value is set to zero,
then only single block DMA transfers can be supported.
Each additional DMA descriptor will require 16-bytes for LPRAM
memory.
choice
prompt "SERCOM0 mode"
default SAMD2L2_SERCOM0_ISUSART
depends on SAMD2L2_SERCOM0
config SAMD2L2_SERCOM0_ISI2C
bool "I2C"
select I2C
select SAMD2L2_HAVE_I2C
config SAMD2L2_SERCOM0_ISSPI
bool "SPI"
select SAMD2L2_HAVE_SPI
config SAMD2L2_SERCOM0_ISUSART
bool "USART"
select USART0_SERIALDRIVER
endchoice
if USART0_SERIALDRIVER
config USART0_RS485MODE
bool "RS-485 on USART0"
default n
---help---
Enable RS-485 interface on USART0. Your board config will have to
provide GPIO_USART0_RS485_DIR pin definition. Currently it cannot be
used with USART0_RXDMA.
config USART0_RS485_DIR_POLARITY
int "USART0 RS-485 DIR pin polarity"
default 1
range 0 1
depends on USART0_RS485MODE
---help---
Polarity of DIR pin for RS-485 on USART0. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
endif # USART0_SERIALDRIVER
choice
prompt "SERCOM1 mode"
default SAMD2L2_SERCOM1_ISUSART
depends on SAMD2L2_SERCOM1
config SAMD2L2_SERCOM1_ISI2C
bool "I2C"
select I2C
select SAMD2L2_HAVE_I2C
config SAMD2L2_SERCOM1_ISSPI
bool "SPI"
select SAMD2L2_HAVE_SPI
config SAMD2L2_SERCOM1_ISUSART
bool "USART"
select USART1_SERIALDRIVER
endchoice
if USART1_SERIALDRIVER
config USART1_RS485MODE
bool "RS-485 on USART1"
default n
---help---
Enable RS-485 interface on USART1. Your board config will have to
provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be
used with USART1_RXDMA.
config USART1_RS485_DIR_POLARITY
int "USART1 RS-485 DIR pin polarity"
default 1
range 0 1
depends on USART1_RS485MODE
---help---
Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
endif # USART1_SERIALDRIVER
choice
prompt "SERCOM2 mode"
default SAMD2L2_SERCOM2_ISUSART
depends on SAMD2L2_SERCOM2
config SAMD2L2_SERCOM2_ISI2C
bool "I2C"
select I2C
select SAMD2L2_HAVE_I2C
config SAMD2L2_SERCOM2_ISSPI
bool "SPI"
select SAMD2L2_HAVE_SPI
config SAMD2L2_SERCOM2_ISUSART
bool "USART"
select USART2_SERIALDRIVER
endchoice
if USART2_SERIALDRIVER
config USART2_RS485MODE
bool "RS-485 on USART2"
default n
---help---
Enable RS-485 interface on USART2. Your board config will have to
provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be
used with USART2_RXDMA.
config USART2_RS485_DIR_POLARITY
int "USART2 RS-485 DIR pin polarity"
default 1
range 0 1
depends on USART2_RS485MODE
---help---
Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
endif # USART2_SERIALDRIVER
choice
prompt "SERCOM3 mode"
default SAMD2L2_SERCOM3_ISUSART
depends on SAMD2L2_SERCOM3
config SAMD2L2_SERCOM3_ISI2C
bool "I2C"
select I2C
select SAMD2L2_HAVE_I2C
config SAMD2L2_SERCOM3_ISSPI
bool "SPI"
select SAMD2L2_HAVE_SPI
config SAMD2L2_SERCOM3_ISUSART
bool "USART"
select USART3_SERIALDRIVER
endchoice
if USART3_SERIALDRIVER
config USART3_RS485MODE
bool "RS-485 on USART3"
default n
---help---
Enable RS-485 interface on USART3. Your board config will have to
provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be
used with USART3_RXDMA.
config USART3_RS485_DIR_POLARITY
int "USART3 RS-485 DIR pin polarity"
default 1
range 0 1
depends on USART3_RS485MODE
---help---
Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
endif # USART3_SERIALDRIVER
choice
prompt "SERCOM4 mode"
default SAMD2L2_SERCOM4_ISUSART
depends on SAMD2L2_SERCOM4
config SAMD2L2_SERCOM4_ISI2C
bool "I2C"
select I2C
select SAMD2L2_HAVE_I2C
config SAMD2L2_SERCOM4_ISSPI
bool "SPI"
select SAMD2L2_HAVE_SPI
config SAMD2L2_SERCOM4_ISUSART
bool "USART"
select USART4_SERIALDRIVER
endchoice
if USART4_SERIALDRIVER
config USART4_RS485MODE
bool "RS-485 on USART4"
default n
---help---
Enable RS-485 interface on USART4. Your board config will have to
provide GPIO_USART4_RS485_DIR pin definition. Currently it cannot be
used with USART4_RXDMA.
config USART4_RS485_DIR_POLARITY
int "USART4 RS-485 DIR pin polarity"
default 1
range 0 1
depends on USART4_RS485MODE
---help---
Polarity of DIR pin for RS-485 on USART4. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
endif # USART4_SERIALDRIVER
choice
prompt "SERCOM5 mode"
default SAMD2L2_SERCOM5_ISUSART
depends on SAMD2L2_SERCOM5
config SAMD2L2_SERCOM5_ISI2C
bool "I2C"
select I2C
select SAMD2L2_HAVE_I2C
config SAMD2L2_SERCOM5_ISSPI
bool "SPI"
select SAMD2L2_HAVE_SPI
config SAMD2L2_SERCOM5_ISUSART
bool "USART"
select USART5_SERIALDRIVER
endchoice
if USART5_SERIALDRIVER
config USART5_RS485MODE
bool "RS-485 on USART5"
default n
---help---
Enable RS-485 interface on USART5. Your board config will have to
provide GPIO_USART5_RS485_DIR pin definition. Currently it cannot be
used with USART5_RXDMA.
config USART5_RS485_DIR_POLARITY
int "USART5 RS-485 DIR pin polarity"
default 1
range 0 1
depends on USART5_RS485MODE
---help---
Polarity of DIR pin for RS-485 on USART5. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
endif # USART5_SERIALDRIVER
config SAMD2L2_HAVE_SPI
bool
select SPI
menu "SPI options"
depends on SAMD2L2_HAVE_SPI
config SAMD2L2_SPI_DMA
bool "SPI DMA"
default n
depends on SAMD2L2_DMAC && EXPERIMENTAL
---help---
Use DMA for SPI SERCOM peripherals.
config SAMD2L2_SPI_REGDEBUG
bool "SPI register-Level Debug"
default n
depends on DEBUG_SPI_INFO
---help---
Enable very low-level register access debug. Depends on DEBUG_SPI.
endmenu # SPI options
config SAMD2L2_HAVE_I2C
bool
select I2C
menu "I2C options"
depends on SAMD2L2_HAVE_I2C
config SAMD2L2_I2C_REGDEBUG
bool "I2C register-Level Debug"
default n
depends on DEBUG_I2C_INFO
---help---
Enable very low-level register access debug. Depends on DEBUG_I2C.
endmenu # I2C options
menu "USB options"
depends on SAMD2L2_HAVE_USB
config SAMD2L2_USB_ENABLE_PPEP
bool "Enable Ping-Pong Endpoints"
default n
---help---
To maximize throughput, an endpoint can be configured for ping-pong
operation. When this is done the input and output endpoint with the same
address are used in the same direction. The CPU or DMA Controller can
then read/write one data buffer while the USB module writes/reads from
the other buffer. This gives double buffered communication.
config SAMD2L2_USB_REGDEBUG
bool "USB register-Level Debug"
default n
depends on DEBUG_USB_INFO
---help---
Enable very low-level register access debug. Depends on
CONFIG_DEBUG_USB_INFO.
endmenu # USB options

102
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@ -0,0 +1,102 @@
############################################################################
# arch/arm/src/samd2l2/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
CMN_ASRCS = arm_exception.S arm_saveusercontext.S arm_fullcontextrestore.S
CMN_ASRCS += arm_switchcontext.S vfork.S
CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c arm_copyfullstate.c
CMN_CSRCS += arm_createstack.c arm_mdelay.c arm_udelay.c arm_exit.c
CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_systemreset.c arm_unblocktask.c arm_usestack.c arm_doirq.c
CMN_CSRCS += arm_hardfault.c arm_svcall.c arm_vectors.c arm_vfork.c
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += arm_dumpnvic.c
endif
CHIP_CSRCS = sam_irq.c sam_lowputc.c sam_port.c sam_sercom.c sam_serial.c
CHIP_CSRCS += sam_start.c sam_usart.c
# Configuration-dependent SAM D/L files
ifeq ($(CONFIG_ARCH_FAMILY_SAMD20),y)
CHIP_CSRCS += samd_clockconfig.c samd_gclk.c
else ifeq ($(CONFIG_ARCH_FAMILY_SAMD21),y)
CHIP_CSRCS += samd_clockconfig.c samd_gclk.c
else ifeq ($(CONFIG_ARCH_FAMILY_SAML21),y)
CHIP_CSRCS += saml_clockconfig.c saml_gclk.c
endif
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += sam_idle.c
endif
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += sam_timerisr.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += sam_userspace.c
endif
ifeq ($(CONFIG_ARCH_IRQPRIO),y)
CHIP_CSRCS += sam_irqprio.c
endif
ifeq ($(CONFIG_SAMD2L2_ADC),y)
CHIP_CSRCS += sam_adc.c
endif
ifeq ($(CONFIG_SAMD2L2_DMAC),y)
CHIP_CSRCS += sam_dmac.c
endif
ifeq ($(CONFIG_SAMD2L2_HAVE_SPI),y)
CHIP_CSRCS += sam_spi.c
endif
ifeq ($(CONFIG_SAMD2L2_HAVE_I2C),y)
CHIP_CSRCS += sam_i2c_master.c
endif
ifeq ($(CONFIG_SAMD2L2_USB),y)
CHIP_CSRCS += sam_usb.c
endif
ifeq ($(CONFIG_SAMD2L2_EIC),y)
CHIP_CSRCS += sam_eic.c
endif
ifeq ($(CONFIG_SAMD2L2_AC),y)
CHIP_CSRCS += sam_ac.c
endif

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/****************************************************************************
* arch/arm/src/samd2l2/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_H
#define __ARCH_ARM_SRC_SAMD2L2_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Include the chip capabilities file */
#include <arch/samd2l2/chip.h>
/* Define the number of interrupt vectors that need to be supported for this
* chip
*/
#define ARMV6M_PERIPHERAL_INTERRUPTS 25
/* Include the memory map file. Other chip hardware files should then
* include this file for the proper setup.
*/
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
# include "hardware/samd20_memorymap.h"
#elif defined(CONFIG_ARCH_FAMILY_SAMD21)
# include "hardware/samd21_memorymap.h"
#elif defined(CONFIG_ARCH_FAMILY_SAML21)
# include "hardware/saml21_memorymap.h"
#else
# error Unrecognized SAMD/L architecture
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd20_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_MEMORYMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* System Memory Map */
#define SAM_FLASH_BASE 0x00000000 /* Embedded FLASH memory space (<= 256KB) */
#define SAM_CALIB_BASE 0x00800000 /* Calibration and auxiliary space */
#define SAM_SRAM_BASE 0x20000000 /* Embedded SRAM memory space (<= 64KB) */
#define SAM_AHBA_BASE 0x40000000 /* AHB-APB Bridge A (64KB) */
#define SAM_AHBB_BASE 0x41000000 /* AHB-APB Bridge B (64KB) */
#define SAM_AHBC_BASE 0x42000000 /* AHB-APB Bridge C (64KB) */
/* Calibration and Auxiliary Space */
#define SAM_LOCKBIT_BASE 0x00802000 /* LOCKBIT Base Address */
#define SAM_AUX0_BASE 0x00804000 /* AUX0 offset address */
#define SAM_AUX1_BASE 0x00806000 /* AUX1 offset address */
# define SAM_AUX1_AREA1 0x00806000 /* Area 1 offset address (reserved, 64 bits) */
# define SAM_AUX1_AREA2 0x00806008 /* Area 2 Device configuration area (64 bits) */
# define SAM_AUX1_AREA3 0x00806010 /* Area 3 offset address (reserved, 128 bits) */
# define SAM_AUX1_AREA4 0x00806020 /* Area 4 Software calibration area (256 bits) */
#define SAM_NVMCALIB_AREA SAM_AUX1_AREA4 /* Use same name of SAML21 */
/* AHB-APB Bridge A */
#define SAM_PAC0_BASE 0x40000000 /* Peripheral Access Controller 0 */
#define SAM_PM_BASE 0x40000400 /* Power Manager */
#define SAM_SYSCTRL_BASE 0x40000800 /* System Controller */
#define SAM_GCLK_BASE 0x40000c00 /* Generic Clock Controller */
#define SAM_WDT_BASE 0x40001000 /* Watchdog Timer */
#define SAM_RTC_BASE 0x40001400 /* Real-Time Counter */
#define SAM_EIC_BASE 0x40001800 /* External Interrupt Controller */
/* AHB-APB Bridge B */
#define SAM_PAC1_BASE 0x41000000 /* Peripheral Access Controller 1 */
#define SAM_DSU_BASE 0x41002000 /* Device Service Unit */
#define SAM_NVMCTRL_BASE 0x41004000 /* Non-Volatile Memory Controller */
#define SAM_PORT_BASE 0x41004400 /* Ports */
/* AHB-APB Bridge C */
#define SAM_PAC2_BASE 0x42000000 /* Peripheral Access Controller 2 */
#define SAM_EVSYS_BASE 0x42000400 /* Event System */
#define SAM_SERCOM0_BASE 0x42000800 /* Serial Communication Interface 0 */
#define SAM_SERCOM1_BASE 0x42000c00 /* Serial Communication Interface 1 */
#define SAM_SERCOM2_BASE 0x42001000 /* Serial Communication Interface 2 */
#define SAM_SERCOM3_BASE 0x42001400 /* Serial Communication Interface 3 */
#define SAM_SERCOM4_BASE 0x42001800 /* Serial Communication Interface 4 */
#define SAM_SERCOM5_BASE 0x42001c00 /* Serial Communication Interface 5 */
#define SAM_TC0_BASE 0x42002000 /* Timer/Counter 0 */
#define SAM_TC1_BASE 0x42002400 /* Timer/Counter 1 */
#define SAM_TC2_BASE 0x42002800 /* Timer/Counter 2 */
#define SAM_TC3_BASE 0x42002c00 /* Timer/Counter 3 */
#define SAM_TC4_BASE 0x42003000 /* Timer/Counter 4 */
#define SAM_TC5_BASE 0x42003400 /* Timer/Counter 5 */
#define SAM_TC6_BASE 0x42003800 /* Timer/Counter 6 */
#define SAM_TC7_BASE 0x42003c00 /* Timer/Counter 7 */
#define SAM_ADC_BASE 0x42004000 /* Analog-to-Digital Converter */
#define SAM_AC_BASE 0x42004400 /* Analog Comparator*/
#define SAM_DAC_BASE 0x42004800 /* Digital-to-Analog Converter */
#define SAM_PTC_BASE 0x42004c00 /* Peripheral Touch Controller */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_MEMORYMAP_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd20_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_PINMAP_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_PINMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* GPIO pin definitions *****************************************************/
/* Alternate Pin Functions.
*
* Alternative pin selections are provided with a numeric suffix like _1, _2,
* etc. Drivers, however, will use the pin selection without the numeric
* suffix. Additional definitions are required in the board.h file.
* For example, if we wanted the SERCOM0 PAD0 on PA8, then the following
* definition should appear in the board.h header file for that board:
*
* #define PORT_SERCOM0_PAD0 PORT_SERCOM0_PAD0_1
*
* The driver will then automatically configure PA8 as the SERCOM0 PAD0
* pin.
*/
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as
* frequency, open-drain/push-pull, and pull-up/down! Just the basics are
* defined for most pins in this file.
*/
/* Analog comparator */
#define PORT_AC_CMP0_1 (PORT_FUNCH | PORTA | PORT_PIN12)
#define PORT_AC_CMP0_2 (PORT_FUNCH | PORTA | PORT_PIN18)
#define PORT_AC_CMP1_1 (PORT_FUNCH | PORTA | PORT_PIN13)
#define PORT_AC_CMP1_2 (PORT_FUNCH | PORTA | PORT_PIN19)
/* ADC voltage references */
#define PORT_ADC_VREFA (PORT_FUNCB | PORTA | PORT_PIN3)
#define PORT_ADC_VREFB (PORT_FUNCB | PORTA | PORT_PIN4)
#define PORT_AIN0_1 (PORT_FUNCB | PORTA | PORT_PIN2)
#define PORT_AIN0_2 (PORT_FUNCB | PORTA | PORT_PIN4)
#define PORT_AIN1_1 (PORT_FUNCB | PORTA | PORT_PIN3)
#define PORT_AIN1_2 (PORT_FUNCB | PORTA | PORT_PIN5)
#define PORT_AIN2_1 (PORT_FUNCB | PORTA | PORT_PIN6)
#define PORT_AIN2_2 (PORT_FUNCB | PORTB | PORT_PIN8)
#define PORT_AIN3_1 (PORT_FUNCB | PORTA | PORT_PIN7)
#define PORT_AIN3_2 (PORT_FUNCB | PORTB | PORT_PIN9)
#define PORT_AIN4 (PORT_FUNCB | PORTA | PORT_PIN4)
#define PORT_AIN5 (PORT_FUNCB | PORTA | PORT_PIN5)
#define PORT_AIN6 (PORT_FUNCB | PORTA | PORT_PIN6)
#define PORT_AIN7 (PORT_FUNCB | PORTA | PORT_PIN7)
#define PORT_AIN8 (PORT_FUNCB | PORTB | PORT_PIN0)
#define PORT_AIN9 (PORT_FUNCB | PORTB | PORT_PIN1)
#define PORT_AIN10 (PORT_FUNCB | PORTB | PORT_PIN2)
#define PORT_AIN11 (PORT_FUNCB | PORTB | PORT_PIN3)
#define PORT_AIN12 (PORT_FUNCB | PORTB | PORT_PIN4)
#define PORT_AIN13 (PORT_FUNCB | PORTB | PORT_PIN5)
#define PORT_AIN14 (PORT_FUNCB | PORTB | PORT_PIN6)
#define PORT_AIN15 (PORT_FUNCB | PORTB | PORT_PIN7)
#define PORT_AIN16 (PORT_FUNCB | PORTA | PORT_PIN8)
#define PORT_AIN17 (PORT_FUNCB | PORTA | PORT_PIN9)
#define PORT_AIN18 (PORT_FUNCB | PORTA | PORT_PIN10)
#define PORT_AIN19 (PORT_FUNCB | PORTA | PORT_PIN11)
/* DAC */
#define PORT_DAC_VREFA (PORT_FUNCB | PORTA | PORT_PIN3)
#define PORT_DAC_VOUT (PORT_FUNCB | PORTA | PORT_PIN2)
/* External interrupts */
#define PORT_EXTINT0_1 (PORT_FUNCA | PORTA | PORT_PIN0)
#define PORT_EXTINT0_2 (PORT_FUNCA | PORTA | PORT_PIN16)
#define PORT_EXTINT0_3 (PORT_FUNCA | PORTB | PORT_PIN0)
#define PORT_EXTINT0_4 (PORT_FUNCA | PORTB | PORT_PIN16)
#define PORT_EXTINT1_1 (PORT_FUNCA | PORTA | PORT_PIN1)
#define PORT_EXTINT1_2 (PORT_FUNCA | PORTA | PORT_PIN17)
#define PORT_EXTINT1_3 (PORT_FUNCA | PORTB | PORT_PIN1)
#define PORT_EXTINT1_4 (PORT_FUNCA | PORTB | PORT_PIN17)
#define PORT_EXTINT2_1 (PORT_FUNCA | PORTA | PORT_PIN18)
#define PORT_EXTINT2_2 (PORT_FUNCA | PORTA | PORT_PIN2)
#define PORT_EXTINT2_3 (PORT_FUNCA | PORTB | PORT_PIN2)
#define PORT_EXTINT3_1 (PORT_FUNCA | PORTA | PORT_PIN19)
#define PORT_EXTINT3_2 (PORT_FUNCA | PORTA | PORT_PIN3)
#define PORT_EXTINT3_3 (PORT_FUNCA | PORTB | PORT_PIN3)
#define PORT_EXTINT4_1 (PORT_FUNCA | PORTA | PORT_PIN20)
#define PORT_EXTINT4_2 (PORT_FUNCA | PORTA | PORT_PIN4)
#define PORT_EXTINT4_3 (PORT_FUNCA | PORTB | PORT_PIN4)
#define PORT_EXTINT5_1 (PORT_FUNCA | PORTA | PORT_PIN21)
#define PORT_EXTINT5_2 (PORT_FUNCA | PORTA | PORT_PIN5)
#define PORT_EXTINT5_3 (PORT_FUNCA | PORTB | PORT_PIN5)
#define PORT_EXTINT6_1 (PORT_FUNCA | PORTA | PORT_PIN22)
#define PORT_EXTINT6_2 (PORT_FUNCA | PORTA | PORT_PIN6)
#define PORT_EXTINT6_3 (PORT_FUNCA | PORTB | PORT_PIN22)
#define PORT_EXTINT6_4 (PORT_FUNCA | PORTB | PORT_PIN6)
#define PORT_EXTINT7_1 (PORT_FUNCA | PORTA | PORT_PIN23)
#define PORT_EXTINT7_2 (PORT_FUNCA | PORTA | PORT_PIN7)
#define PORT_EXTINT7_3 (PORT_FUNCA | PORTB | PORT_PIN23)
#define PORT_EXTINT7_4 (PORT_FUNCA | PORTB | PORT_PIN7)
#define PORT_EXTINT8_1 (PORT_FUNCA | PORTA | PORT_PIN28)
#define PORT_EXTINT8_2 (PORT_FUNCA | PORTB | PORT_PIN8)
#define PORT_EXTINT9_1 (PORT_FUNCA | PORTA | PORT_PIN9)
#define PORT_EXTINT9_2 (PORT_FUNCA | PORTB | PORT_PIN9)
#define PORT_EXTINT10_1 (PORT_FUNCA | PORTA | PORT_PIN10)
#define PORT_EXTINT10_2 (PORT_FUNCA | PORTA | PORT_PIN30)
#define PORT_EXTINT10_3 (PORT_FUNCA | PORTB | PORT_PIN10)
#define PORT_EXTINT11_1 (PORT_FUNCA | PORTA | PORT_PIN11)
#define PORT_EXTINT11_2 (PORT_FUNCA | PORTA | PORT_PIN31)
#define PORT_EXTINT11_3 (PORT_FUNCA | PORTB | PORT_PIN11)
#define PORT_EXTINT12_1 (PORT_FUNCA | PORTA | PORT_PIN12)
#define PORT_EXTINT12_2 (PORT_FUNCA | PORTA | PORT_PIN24)
#define PORT_EXTINT12_3 (PORT_FUNCA | PORTB | PORT_PIN12)
#define PORT_EXTINT13_1 (PORT_FUNCA | PORTA | PORT_PIN13)
#define PORT_EXTINT13_2 (PORT_FUNCA | PORTA | PORT_PIN25)
#define PORT_EXTINT13_3 (PORT_FUNCA | PORTB | PORT_PIN13)
#define PORT_EXTINT14_1 (PORT_FUNCA | PORTA | PORT_PIN14)
#define PORT_EXTINT14_2 (PORT_FUNCA | PORTB | PORT_PIN14)
#define PORT_EXTINT14_3 (PORT_FUNCA | PORTB | PORT_PIN30)
#define PORT_EXTINT15_1 (PORT_FUNCA | PORTA | PORT_PIN15)
#define PORT_EXTINT15_2 (PORT_FUNCA | PORTA | PORT_PIN27)
#define PORT_EXTINT15_3 (PORT_FUNCA | PORTB | PORT_PIN15)
#define PORT_EXTINT15_4 (PORT_FUNCA | PORTB | PORT_PIN31)
/* Generic clock controller I/O */
#define PORT_GCLK_IO0_1 (PORT_FUNCH | PORTA | PORT_PIN14)
#define PORT_GCLK_IO0_2 (PORT_FUNCH | PORTA | PORT_PIN27)
#define PORT_GCLK_IO0_3 (PORT_FUNCH | PORTA | PORT_PIN28)
#define PORT_GCLK_IO0_4 (PORT_FUNCH | PORTA | PORT_PIN30)
#define PORT_GCLK_IO0_5 (PORT_FUNCH | PORTB | PORT_PIN14)
#define PORT_GCLK_IO0_6 (PORT_FUNCH | PORTB | PORT_PIN22)
#define PORT_GCLK_IO1_1 (PORT_FUNCH | PORTA | PORT_PIN15)
#define PORT_GCLK_IO1_2 (PORT_FUNCH | PORTB | PORT_PIN15)
#define PORT_GCLK_IO1_3 (PORT_FUNCH | PORTB | PORT_PIN23)
#define PORT_GCLK_IO2_1 (PORT_FUNCH | PORTA | PORT_PIN16)
#define PORT_GCLK_IO2_2 (PORT_FUNCH | PORTB | PORT_PIN16)
#define PORT_GCLK_IO3_1 (PORT_FUNCH | PORTA | PORT_PIN17)
#define PORT_GCLK_IO3_2 (PORT_FUNCH | PORTB | PORT_PIN17)
#define PORT_GCLK_IO4_1 (PORT_FUNCH | PORTA | PORT_PIN10)
#define PORT_GCLK_IO4_2 (PORT_FUNCH | PORTA | PORT_PIN20)
#define PORT_GCLK_IO4_3 (PORT_FUNCH | PORTB | PORT_PIN10)
#define PORT_GCLK_IO5_1 (PORT_FUNCH | PORTA | PORT_PIN11)
#define PORT_GCLK_IO5_2 (PORT_FUNCH | PORTA | PORT_PIN21)
#define PORT_GCLK_IO5_3 (PORT_FUNCH | PORTB | PORT_PIN11)
#define PORT_GCLK_IO6_1 (PORT_FUNCH | PORTA | PORT_PIN22)
#define PORT_GCLK_IO6_2 (PORT_FUNCH | PORTB | PORT_PIN12)
#define PORT_GCLK_IO7_1 (PORT_FUNCH | PORTA | PORT_PIN23)
#define PORT_GCLK_IO7_2 (PORT_FUNCH | PORTB | PORT_PIN13)
/* Non maskable interrupt */
#define PORT_NMI (PORT_FUNCA | PORTA | PORT_PIN8)
/* Serial communication interface (SERCOM) */
#define PORT_SERCOM0_PAD0_1 (PORT_FUNCC | PORTA | PORT_PIN8)
#define PORT_SERCOM0_PAD0_2 (PORT_FUNCD | PORTA | PORT_PIN4)
#define PORT_SERCOM0_PAD1_1 (PORT_FUNCC | PORTA | PORT_PIN9)
#define PORT_SERCOM0_PAD1_2 (PORT_FUNCD | PORTA | PORT_PIN5)
#define PORT_SERCOM0_PAD2_1 (PORT_FUNCC | PORTA | PORT_PIN10)
#define PORT_SERCOM0_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN6)
#define PORT_SERCOM0_PAD3_1 (PORT_FUNCC | PORTA | PORT_PIN11)
#define PORT_SERCOM0_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN7)
#define PORT_SERCOM1_PAD0_1 (PORT_FUNCC | PORTA | PORT_PIN16)
#define PORT_SERCOM1_PAD0_2 (PORT_FUNCD | PORTA | PORT_PIN0)
#define PORT_SERCOM1_PAD1_1 (PORT_FUNCC | PORTA | PORT_PIN17)
#define PORT_SERCOM1_PAD1_2 (PORT_FUNCD | PORTA | PORT_PIN1)
#define PORT_SERCOM1_PAD2_1 (PORT_FUNCC | PORTA | PORT_PIN18)
#define PORT_SERCOM1_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN30)
#define PORT_SERCOM1_PAD3_1 (PORT_FUNCC | PORTA | PORT_PIN19)
#define PORT_SERCOM1_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN31)
#define PORT_SERCOM2_PAD0_1 (PORT_FUNCC | PORTA | PORT_PIN12)
#define PORT_SERCOM2_PAD0_2 (PORT_FUNCD | PORTA | PORT_PIN8)
#define PORT_SERCOM2_PAD1_1 (PORT_FUNCC | PORTA | PORT_PIN13)
#define PORT_SERCOM2_PAD1_2 (PORT_FUNCD | PORTA | PORT_PIN9)
#define PORT_SERCOM2_PAD2_1 (PORT_FUNCC | PORTA | PORT_PIN14)
#define PORT_SERCOM2_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN10)
#define PORT_SERCOM2_PAD3_1 (PORT_FUNCC | PORTA | PORT_PIN15)
#define PORT_SERCOM2_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN11)
#define PORT_SERCOM3_PAD0_1 (PORT_FUNCC | PORTA | PORT_PIN22)
#define PORT_SERCOM3_PAD0_2 (PORT_FUNCD | PORTA | PORT_PIN16)
#define PORT_SERCOM3_PAD1_1 (PORT_FUNCC | PORTA | PORT_PIN23)
#define PORT_SERCOM3_PAD1_2 (PORT_FUNCD | PORTA | PORT_PIN17)
#define PORT_SERCOM3_PAD2_1 (PORT_FUNCC | PORTA | PORT_PIN24)
#define PORT_SERCOM3_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN18)
#define PORT_SERCOM3_PAD2_3 (PORT_FUNCD | PORTA | PORT_PIN20)
#define PORT_SERCOM3_PAD3_1 (PORT_FUNCC | PORTA | PORT_PIN25)
#define PORT_SERCOM3_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN19)
#define PORT_SERCOM3_PAD3_3 (PORT_FUNCD | PORTA | PORT_PIN21)
#define PORT_SERCOM4_PAD0_1 (PORT_FUNCC | PORTB | PORT_PIN12)
#define PORT_SERCOM4_PAD0_2 (PORT_FUNCD | PORTA | PORT_PIN12)
#define PORT_SERCOM4_PAD0_3 (PORT_FUNCD | PORTB | PORT_PIN8)
#define PORT_SERCOM4_PAD1_1 (PORT_FUNCC | PORTB | PORT_PIN13)
#define PORT_SERCOM4_PAD1_2 (PORT_FUNCD | PORTA | PORT_PIN13)
#define PORT_SERCOM4_PAD1_3 (PORT_FUNCD | PORTB | PORT_PIN9)
#define PORT_SERCOM4_PAD2_1 (PORT_FUNCC | PORTB | PORT_PIN14)
#define PORT_SERCOM4_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN14)
#define PORT_SERCOM4_PAD2_3 (PORT_FUNCD | PORTB | PORT_PIN10)
#define PORT_SERCOM4_PAD3_1 (PORT_FUNCC | PORTB | PORT_PIN15)
#define PORT_SERCOM4_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN15)
#define PORT_SERCOM4_PAD3_3 (PORT_FUNCD | PORTB | PORT_PIN11)
#define PORT_SERCOM5_PAD0_1 (PORT_FUNCC | PORTB | PORT_PIN16)
#define PORT_SERCOM5_PAD0_2 (PORT_FUNCD | PORTA | PORT_PIN22)
#define PORT_SERCOM5_PAD0_3 (PORT_FUNCD | PORTB | PORT_PIN2)
#define PORT_SERCOM5_PAD0_4 (PORT_FUNCD | PORTB | PORT_PIN30)
#define PORT_SERCOM5_PAD1_1 (PORT_FUNCC | PORTB | PORT_PIN17)
#define PORT_SERCOM5_PAD1_2 (PORT_FUNCD | PORTA | PORT_PIN23)
#define PORT_SERCOM5_PAD1_3 (PORT_FUNCD | PORTB | PORT_PIN3)
#define PORT_SERCOM5_PAD1_4 (PORT_FUNCD | PORTB | PORT_PIN31)
#define PORT_SERCOM5_PAD2_1 (PORT_FUNCC | PORTA | PORT_PIN20)
#define PORT_SERCOM5_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN24)
#define PORT_SERCOM5_PAD2_3 (PORT_FUNCD | PORTB | PORT_PIN0)
#define PORT_SERCOM5_PAD2_4 (PORT_FUNCD | PORTB | PORT_PIN22)
#define PORT_SERCOM5_PAD3_1 (PORT_FUNCC | PORTA | PORT_PIN21)
#define PORT_SERCOM5_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN25)
#define PORT_SERCOM5_PAD3_3 (PORT_FUNCD | PORTB | PORT_PIN1)
#define PORT_SERCOM5_PAD3_4 (PORT_FUNCD | PORTB | PORT_PIN23)
/* JTAG/SWI */
#define PORT_SWCLK (PORT_FUNCG | PORTA | PORT_PIN30)
#define PORT_SWDIO (PORT_FUNCG | PORTA | PORT_PIN31)
/* Timer/Counters */
#define PORT_TC0_WO0_1 (PORT_FUNCE | PORTA | PORT_PIN8)
#define PORT_TC0_WO0_2 (PORT_FUNCF | PORTA | PORT_PIN4)
#define PORT_TC0_WO0_3 (PORT_FUNCF | PORTB | PORT_PIN30)
#define PORT_TC0_WO1_1 (PORT_FUNCE | PORTA | PORT_PIN9)
#define PORT_TC0_WO1_2 (PORT_FUNCF | PORTA | PORT_PIN5)
#define PORT_TC0_WO1_3 (PORT_FUNCF | PORTB | PORT_PIN31)
#define PORT_TC1_WO0_1 (PORT_FUNCE | PORTA | PORT_PIN10)
#define PORT_TC1_WO0_2 (PORT_FUNCF | PORTA | PORT_PIN30)
#define PORT_TC1_WO0_3 (PORT_FUNCF | PORTA | PORT_PIN6)
#define PORT_TC1_WO1_1 (PORT_FUNCE | PORTA | PORT_PIN11)
#define PORT_TC1_WO1_2 (PORT_FUNCF | PORTA | PORT_PIN31)
#define PORT_TC1_WO1_3 (PORT_FUNCF | PORTA | PORT_PIN7)
#define PORT_TC2_WO0_1 (PORT_FUNCE | PORTA | PORT_PIN12)
#define PORT_TC2_WO0_2 (PORT_FUNCF | PORTA | PORT_PIN0)
#define PORT_TC2_WO0_3 (PORT_FUNCF | PORTA | PORT_PIN16)
#define PORT_TC2_WO1_1 (PORT_FUNCE | PORTA | PORT_PIN13)
#define PORT_TC2_WO1_2 (PORT_FUNCF | PORTA | PORT_PIN1)
#define PORT_TC2_WO1_3 (PORT_FUNCF | PORTA | PORT_PIN17)
#define PORT_TC3_WO0_1 (PORT_FUNCE | PORTA | PORT_PIN14)
#define PORT_TC3_WO0_2 (PORT_FUNCF | PORTA | PORT_PIN18)
#define PORT_TC3_WO1_1 (PORT_FUNCE | PORTA | PORT_PIN15)
#define PORT_TC3_WO1_2 (PORT_FUNCF | PORTA | PORT_PIN19)
#define PORT_TC4_WO0_1 (PORT_FUNCE | PORTB | PORT_PIN12)
#define PORT_TC4_WO0_2 (PORT_FUNCF | PORTA | PORT_PIN22)
#define PORT_TC4_WO0_3 (PORT_FUNCF | PORTB | PORT_PIN8)
#define PORT_TC4_WO1_1 (PORT_FUNCE | PORTB | PORT_PIN13)
#define PORT_TC4_WO1_2 (PORT_FUNCF | PORTA | PORT_PIN23)
#define PORT_TC4_WO1_3 (PORT_FUNCF | PORTB | PORT_PIN9)
#define PORT_TC5_WO0_1 (PORT_FUNCE | PORTB | PORT_PIN14)
#define PORT_TC5_WO0_2 (PORT_FUNCF | PORTA | PORT_PIN24)
#define PORT_TC5_WO0_3 (PORT_FUNCF | PORTB | PORT_PIN10)
#define PORT_TC5_WO1_1 (PORT_FUNCE | PORTB | PORT_PIN15)
#define PORT_TC5_WO1_2 (PORT_FUNCF | PORTA | PORT_PIN25)
#define PORT_TC5_WO1_3 (PORT_FUNCF | PORTB | PORT_PIN11)
#define PORT_TC6_WO0_1 (PORT_FUNCE | PORTB | PORT_PIN16)
#define PORT_TC6_WO0_2 (PORT_FUNCF | PORTB | PORT_PIN2)
#define PORT_TC6_WO1_1 (PORT_FUNCE | PORTB | PORT_PIN17)
#define PORT_TC6_WO1_2 (PORT_FUNCF | PORTB | PORT_PIN3)
#define PORT_TC7_WO0_1 (PORT_FUNCE | PORTA | PORT_PIN20)
#define PORT_TC7_WO0_2 (PORT_FUNCF | PORTB | PORT_PIN0)
#define PORT_TC7_WO0_3 (PORT_FUNCF | PORTB | PORT_PIN22)
#define PORT_TC7_WO1_1 (PORT_FUNCE | PORTA | PORT_PIN21)
#define PORT_TC7_WO1_2 (PORT_FUNCF | PORTB | PORT_PIN1)
#define PORT_TC7_WO1_3 (PORT_FUNCF | PORTB | PORT_PIN23)
/* Peripheral touch controller */
#define PORT_PTC_X0 (PORT_FUNCB | PORTA | PORT_PIN8)
#define PORT_PTC_X1 (PORT_FUNCB | PORTA | PORT_PIN9)
#define PORT_PTC_X2 (PORT_FUNCB | PORTA | PORT_PIN10)
#define PORT_PTC_X3 (PORT_FUNCB | PORTA | PORT_PIN11)
#define PORT_PTC_X4 (PORT_FUNCB | PORTA | PORT_PIN16)
#define PORT_PTC_X5 (PORT_FUNCB | PORTA | PORT_PIN17)
#define PORT_PTC_X6 (PORT_FUNCB | PORTA | PORT_PIN18)
#define PORT_PTC_X7 (PORT_FUNCB | PORTA | PORT_PIN19)
#define PORT_PTC_X8 (PORT_FUNCB | PORTA | PORT_PIN20)
#define PORT_PTC_X9 (PORT_FUNCB | PORTA | PORT_PIN21)
#define PORT_PTC_X10 (PORT_FUNCB | PORTA | PORT_PIN22)
#define PORT_PTC_X11 (PORT_FUNCB | PORTA | PORT_PIN23)
#define PORT_PTC_X12 (PORT_FUNCB | PORTB | PORT_PIN12)
#define PORT_PTC_X13 (PORT_FUNCB | PORTB | PORT_PIN13)
#define PORT_PTC_X14 (PORT_FUNCB | PORTB | PORT_PIN14)
#define PORT_PTC_X15 (PORT_FUNCB | PORTB | PORT_PIN15)
#define PORT_PTC_Y0 (PORT_FUNCB | PORTA | PORT_PIN2)
#define PORT_PTC_Y1 (PORT_FUNCB | PORTA | PORT_PIN3)
#define PORT_PTC_Y2 (PORT_FUNCB | PORTA | PORT_PIN4)
#define PORT_PTC_Y3 (PORT_FUNCB | PORTA | PORT_PIN5)
#define PORT_PTC_Y4 (PORT_FUNCB | PORTA | PORT_PIN6)
#define PORT_PTC_Y5 (PORT_FUNCB | PORTA | PORT_PIN7)
#define PORT_PTC_Y6 (PORT_FUNCB | PORTB | PORT_PIN0)
#define PORT_PTC_Y7 (PORT_FUNCB | PORTB | PORT_PIN1)
#define PORT_PTC_Y8 (PORT_FUNCB | PORTB | PORT_PIN2)
#define PORT_PTC_Y9 (PORT_FUNCB | PORTB | PORT_PIN3)
#define PORT_PTC_Y10 (PORT_FUNCB | PORTB | PORT_PIN4)
#define PORT_PTC_Y11 (PORT_FUNCB | PORTB | PORT_PIN5)
#define PORT_PTC_Y12 (PORT_FUNCB | PORTB | PORT_PIN6)
#define PORT_PTC_Y13 (PORT_FUNCB | PORTB | PORT_PIN7)
#define PORT_PTC_Y14 (PORT_FUNCB | PORTB | PORT_PIN8)
#define PORT_PTC_Y15 (PORT_FUNCB | PORTB | PORT_PIN9)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_PINMAP_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd21_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_MEMORYMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* System Memory Map */
#define SAM_FLASH_BASE 0x00000000 /* Embedded FLASH memory space (<= 256KB) */
#define SAM_FLASHRWW_BASE 0x00100000 /* Embedded FLASH RWW memory space (<= 2KB) */
#define SAM_CALIB_BASE 0x00800000 /* Calibration and auxiliary space */
#define SAM_SRAM_BASE 0x20000000 /* Embedded SRAM memory space (<= 64KB) */
#define SAM_AHBA_BASE 0x40000000 /* AHB-APB Bridge A (64KB) */
#define SAM_AHBB_BASE 0x41000000 /* AHB-APB Bridge B (64KB) */
#define SAM_AHBC_BASE 0x42000000 /* AHB-APB Bridge C (64KB) */
/* Calibration and Auxiliary Space */
#define SAM_AUTOCAL_BASE 0x00800000 /* Automatic Calibration row */
#define SAM_AUX0_BASE 0x00804000 /* AUX0 offset address */
#define SAM_AUX1_BASE 0x00806000 /* AUX1 offset address */
# define SAM_AUX1_AREA1 0x00806000 /* Area 1 offset address (reserved, 64 bits) */
# define SAM_AUX1_AREA2 0x00806008 /* Area 2 Device configuration area (64 bits) */
# define SAM_AUX1_AREA3 0x00806010 /* Area 3 offset address (reserved, 128 bits) */
# define SAM_AUX1_AREA4 0x00806020 /* Area 4 Software calibration area (256 bits) */
#define SAM_NVMCALIB_AREA SAM_AUX1_AREA4 /* Use same name of SAML21 */
/* AHB-APB Bridge A */
#define SAM_PAC0_BASE 0x40000000 /* Peripheral Access Controller 0 */
#define SAM_PM_BASE 0x40000400 /* Power Manager */
#define SAM_SYSCTRL_BASE 0x40000800 /* System Controller */
#define SAM_GCLK_BASE 0x40000c00 /* Generic Clock Controller */
#define SAM_WDT_BASE 0x40001000 /* Watchdog Timer */
#define SAM_RTC_BASE 0x40001400 /* Real-Time Counter */
#define SAM_EIC_BASE 0x40001800 /* External Interrupt Controller */
/* AHB-APB Bridge B */
#define SAM_PAC1_BASE 0x41000000 /* Peripheral Access Controller 1 */
#define SAM_DSU_BASE 0x41002000 /* Device Service Unit */
#define SAM_NVMCTRL_BASE 0x41004000 /* Non-Volatile Memory Controller */
#define SAM_PORT_BASE 0x41004400 /* Ports */
#define SAM_DMAC_BASE 0x41004800 /* DMA Controller */
#define SAM_USB_BASE 0x41005000 /* USB */
#define SAM_MTB_BASE 0x41006000 /* Micro Trace Buffer (MTB) */
/* AHB-APB Bridge C */
#define SAM_PAC2_BASE 0x42000000 /* Peripheral Access Controller 2 */
#define SAM_EVSYS_BASE 0x42000400 /* Event System */
#define SAM_SERCOM0_BASE 0x42000800 /* Serial Communication Interface 0 */
#define SAM_SERCOM1_BASE 0x42000c00 /* Serial Communication Interface 1 */
#define SAM_SERCOM2_BASE 0x42001000 /* Serial Communication Interface 2 */
#define SAM_SERCOM3_BASE 0x42001400 /* Serial Communication Interface 3 */
#define SAM_SERCOM4_BASE 0x42001800 /* Serial Communication Interface 4 */
#define SAM_SERCOM5_BASE 0x42001c00 /* Serial Communication Interface 5 */
#define SAM_TCC0_BASE 0x42002000 /* Timer/Counter Control 0 */
#define SAM_TCC1_BASE 0x42002400 /* Timer/Counter Control 1 */
#define SAM_TCC2_BASE 0x42002800 /* Timer/Counter Control 2 */
#define SAM_TC3_BASE 0x42002c00 /* Timer/Counter 3 */
#define SAM_TC4_BASE 0x42003000 /* Timer/Counter 4 */
#define SAM_TC5_BASE 0x42003400 /* Timer/Counter 5 */
#define SAM_TC6_BASE 0x42003800 /* Timer/Counter 6 */
#define SAM_TC7_BASE 0x42003c00 /* Timer/Counter 7 */
#define SAM_ADC_BASE 0x42004000 /* Analog-to-Digital Converter */
#define SAM_AC_BASE 0x42004400 /* Analog Comparator*/
#define SAM_DAC_BASE 0x42004800 /* Digital-to-Analog Converter */
#define SAM_PTC_BASE 0x42004c00 /* Peripheral Touch Controller */
#define SAM_I2S_BASE 0x42005000 /* Inter IC Sound */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_MEMORYMAP_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd21_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_PINMAP_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_PINMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* GPIO pin definitions *****************************************************/
/* Alternate Pin Functions.
*
* Alternative pin selections are provided with a numeric suffix like _1, _2,
* etc. Drivers, however, will use the pin selection without the numeric
* suffix. Additional definitions are required in the board.h file.
* For example, if we wanted the SERCOM0 PAD0 on PA8, then the following
* definition should appear in the board.h header file for that board:
*
* #define PORT_SERCOM0_PAD0 PORT_SERCOM0_PAD0_1
*
* The driver will then automatically configure PA8 as the SERCOM0 PAD0 pin.
*/
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as
* frequency, open-drain/push-pull, and pull-up/down! Just the basics are
* defined for most pins in this file.
*/
/* Analog comparator */
#define PORT_AC_CMP0_1 (PORT_FUNCH | PORTA | PORT_PIN12)
#define PORT_AC_CMP0_2 (PORT_FUNCH | PORTA | PORT_PIN18)
#define PORT_AC_CMP1_1 (PORT_FUNCH | PORTA | PORT_PIN13)
#define PORT_AC_CMP1_2 (PORT_FUNCH | PORTA | PORT_PIN19)
/* ADC voltage references */
#define PORT_ADC_VREFA (PORT_FUNCB | PORTA | PORT_PIN3)
#define PORT_ADC_VREFB (PORT_FUNCB | PORTA | PORT_PIN4)
#define PORT_AIN0_1 (PORT_FUNCB | PORTA | PORT_PIN2)
#define PORT_AIN0_2 (PORT_FUNCB | PORTA | PORT_PIN4)
#define PORT_AIN1_1 (PORT_FUNCB | PORTA | PORT_PIN3)
#define PORT_AIN1_2 (PORT_FUNCB | PORTA | PORT_PIN5)
#define PORT_AIN2_1 (PORT_FUNCB | PORTA | PORT_PIN6)
#define PORT_AIN2_2 (PORT_FUNCB | PORTB | PORT_PIN8)
#define PORT_AIN3_1 (PORT_FUNCB | PORTA | PORT_PIN7)
#define PORT_AIN3_2 (PORT_FUNCB | PORTB | PORT_PIN9)
#define PORT_AIN4 (PORT_FUNCB | PORTA | PORT_PIN4)
#define PORT_AIN5 (PORT_FUNCB | PORTA | PORT_PIN5)
#define PORT_AIN6 (PORT_FUNCB | PORTA | PORT_PIN6)
#define PORT_AIN7 (PORT_FUNCB | PORTA | PORT_PIN7)
#define PORT_AIN8 (PORT_FUNCB | PORTB | PORT_PIN0)
#define PORT_AIN9 (PORT_FUNCB | PORTB | PORT_PIN1)
#define PORT_AIN10 (PORT_FUNCB | PORTB | PORT_PIN2)
#define PORT_AIN11 (PORT_FUNCB | PORTB | PORT_PIN3)
#define PORT_AIN12 (PORT_FUNCB | PORTB | PORT_PIN4)
#define PORT_AIN13 (PORT_FUNCB | PORTB | PORT_PIN5)
#define PORT_AIN14 (PORT_FUNCB | PORTB | PORT_PIN6)
#define PORT_AIN15 (PORT_FUNCB | PORTB | PORT_PIN7)
#define PORT_AIN16 (PORT_FUNCB | PORTA | PORT_PIN8)
#define PORT_AIN17 (PORT_FUNCB | PORTA | PORT_PIN9)
#define PORT_AIN18 (PORT_FUNCB | PORTA | PORT_PIN10)
#define PORT_AIN19 (PORT_FUNCB | PORTA | PORT_PIN11)
/* DAC */
#define PORT_DAC_VREFA (PORT_FUNCB | PORTA | PORT_PIN3)
#define PORT_DAC_VOUT (PORT_FUNCB | PORTA | PORT_PIN2)
/* External interrupts */
#define PORT_EXTINT0_1 (PORT_FUNCA | PORTA | PORT_PIN0)
#define PORT_EXTINT0_2 (PORT_FUNCA | PORTA | PORT_PIN16)
#define PORT_EXTINT0_3 (PORT_FUNCA | PORTB | PORT_PIN0)
#define PORT_EXTINT0_4 (PORT_FUNCA | PORTB | PORT_PIN16)
#define PORT_EXTINT1_1 (PORT_FUNCA | PORTA | PORT_PIN1)
#define PORT_EXTINT1_2 (PORT_FUNCA | PORTA | PORT_PIN17)
#define PORT_EXTINT1_3 (PORT_FUNCA | PORTB | PORT_PIN1)
#define PORT_EXTINT1_4 (PORT_FUNCA | PORTB | PORT_PIN17)
#define PORT_EXTINT2_1 (PORT_FUNCA | PORTA | PORT_PIN18)
#define PORT_EXTINT2_2 (PORT_FUNCA | PORTA | PORT_PIN2)
#define PORT_EXTINT2_3 (PORT_FUNCA | PORTB | PORT_PIN2)
#define PORT_EXTINT3_1 (PORT_FUNCA | PORTA | PORT_PIN19)
#define PORT_EXTINT3_2 (PORT_FUNCA | PORTA | PORT_PIN3)
#define PORT_EXTINT3_3 (PORT_FUNCA | PORTB | PORT_PIN3)
#define PORT_EXTINT4_1 (PORT_FUNCA | PORTA | PORT_PIN20)
#define PORT_EXTINT4_2 (PORT_FUNCA | PORTA | PORT_PIN4)
#define PORT_EXTINT4_3 (PORT_FUNCA | PORTB | PORT_PIN4)
#define PORT_EXTINT5_1 (PORT_FUNCA | PORTA | PORT_PIN21)
#define PORT_EXTINT5_2 (PORT_FUNCA | PORTA | PORT_PIN5)
#define PORT_EXTINT5_3 (PORT_FUNCA | PORTB | PORT_PIN5)
#define PORT_EXTINT6_1 (PORT_FUNCA | PORTA | PORT_PIN22)
#define PORT_EXTINT6_2 (PORT_FUNCA | PORTA | PORT_PIN6)
#define PORT_EXTINT6_3 (PORT_FUNCA | PORTB | PORT_PIN22)
#define PORT_EXTINT6_4 (PORT_FUNCA | PORTB | PORT_PIN6)
#define PORT_EXTINT7_1 (PORT_FUNCA | PORTA | PORT_PIN23)
#define PORT_EXTINT7_2 (PORT_FUNCA | PORTA | PORT_PIN7)
#define PORT_EXTINT7_3 (PORT_FUNCA | PORTB | PORT_PIN23)
#define PORT_EXTINT7_4 (PORT_FUNCA | PORTB | PORT_PIN7)
#define PORT_EXTINT8_1 (PORT_FUNCA | PORTA | PORT_PIN28)
#define PORT_EXTINT8_2 (PORT_FUNCA | PORTB | PORT_PIN8)
#define PORT_EXTINT9_1 (PORT_FUNCA | PORTA | PORT_PIN9)
#define PORT_EXTINT9_2 (PORT_FUNCA | PORTB | PORT_PIN9)
#define PORT_EXTINT10_1 (PORT_FUNCA | PORTA | PORT_PIN10)
#define PORT_EXTINT10_2 (PORT_FUNCA | PORTA | PORT_PIN30)
#define PORT_EXTINT10_3 (PORT_FUNCA | PORTB | PORT_PIN10)
#define PORT_EXTINT11_1 (PORT_FUNCA | PORTA | PORT_PIN11)
#define PORT_EXTINT11_2 (PORT_FUNCA | PORTA | PORT_PIN31)
#define PORT_EXTINT11_3 (PORT_FUNCA | PORTB | PORT_PIN11)
#define PORT_EXTINT12_1 (PORT_FUNCA | PORTA | PORT_PIN12)
#define PORT_EXTINT12_2 (PORT_FUNCA | PORTA | PORT_PIN24)
#define PORT_EXTINT12_3 (PORT_FUNCA | PORTB | PORT_PIN12)
#define PORT_EXTINT13_1 (PORT_FUNCA | PORTA | PORT_PIN13)
#define PORT_EXTINT13_2 (PORT_FUNCA | PORTA | PORT_PIN25)
#define PORT_EXTINT13_3 (PORT_FUNCA | PORTB | PORT_PIN13)
#define PORT_EXTINT14_1 (PORT_FUNCA | PORTA | PORT_PIN14)
#define PORT_EXTINT14_2 (PORT_FUNCA | PORTB | PORT_PIN14)
#define PORT_EXTINT14_3 (PORT_FUNCA | PORTB | PORT_PIN30)
#define PORT_EXTINT15_1 (PORT_FUNCA | PORTA | PORT_PIN15)
#define PORT_EXTINT15_2 (PORT_FUNCA | PORTA | PORT_PIN27)
#define PORT_EXTINT15_3 (PORT_FUNCA | PORTB | PORT_PIN15)
#define PORT_EXTINT15_4 (PORT_FUNCA | PORTB | PORT_PIN31)
/* Generic clock controller I/O */
#define PORT_GCLK_IO0_1 (PORT_FUNCH | PORTA | PORT_PIN14)
#define PORT_GCLK_IO0_2 (PORT_FUNCH | PORTA | PORT_PIN27)
#define PORT_GCLK_IO0_3 (PORT_FUNCH | PORTA | PORT_PIN28)
#define PORT_GCLK_IO0_4 (PORT_FUNCH | PORTA | PORT_PIN30)
#define PORT_GCLK_IO0_5 (PORT_FUNCH | PORTB | PORT_PIN14)
#define PORT_GCLK_IO0_6 (PORT_FUNCH | PORTB | PORT_PIN22)
#define PORT_GCLK_IO1_1 (PORT_FUNCH | PORTA | PORT_PIN15)
#define PORT_GCLK_IO1_2 (PORT_FUNCH | PORTB | PORT_PIN15)
#define PORT_GCLK_IO1_3 (PORT_FUNCH | PORTB | PORT_PIN23)
#define PORT_GCLK_IO2_1 (PORT_FUNCH | PORTA | PORT_PIN16)
#define PORT_GCLK_IO2_2 (PORT_FUNCH | PORTB | PORT_PIN16)
#define PORT_GCLK_IO3_1 (PORT_FUNCH | PORTA | PORT_PIN17)
#define PORT_GCLK_IO3_2 (PORT_FUNCH | PORTB | PORT_PIN17)
#define PORT_GCLK_IO4_1 (PORT_FUNCH | PORTA | PORT_PIN10)
#define PORT_GCLK_IO4_2 (PORT_FUNCH | PORTA | PORT_PIN20)
#define PORT_GCLK_IO4_3 (PORT_FUNCH | PORTB | PORT_PIN10)
#define PORT_GCLK_IO5_1 (PORT_FUNCH | PORTA | PORT_PIN11)
#define PORT_GCLK_IO5_2 (PORT_FUNCH | PORTA | PORT_PIN21)
#define PORT_GCLK_IO5_3 (PORT_FUNCH | PORTB | PORT_PIN11)
#define PORT_GCLK_IO6_1 (PORT_FUNCH | PORTA | PORT_PIN22)
#define PORT_GCLK_IO6_2 (PORT_FUNCH | PORTB | PORT_PIN12)
#define PORT_GCLK_IO7_1 (PORT_FUNCH | PORTA | PORT_PIN23)
#define PORT_GCLK_IO7_2 (PORT_FUNCH | PORTB | PORT_PIN13)
/* Inter IC Sound (I2S) */
#define PORT_I2S_FS0_1 (PORT_FUNCG | PORTA | PORT_PIN11)
#define PORT_I2S_FS0_2 (PORT_FUNCG | PORTA | PORT_PIN21)
#define PORT_I2S_FS1 (PORT_FUNCG | PORTB | PORT_PIN12)
#define PORT_I2S_MCK0_1 (PORT_FUNCG | PORTA | PORT_PIN9)
#define PORT_I2S_MCK0_2 (PORT_FUNCG | PORTB | PORT_PIN17)
#define PORT_I2S_MCK1 (PORT_FUNCG | PORTB | PORT_PIN10)
#define PORT_I2S_SCK0_1 (PORT_FUNCG | PORTA | PORT_PIN10)
#define PORT_I2S_SCK0_2 (PORT_FUNCG | PORTA | PORT_PIN20)
#define PORT_I2S_SCK1 (PORT_FUNCG | PORTB | PORT_PIN11)
#define PORT_I2S_SD0_1 (PORT_FUNCG | PORTA | PORT_PIN19)
#define PORT_I2S_SD0_2 (PORT_FUNCG | PORTA | PORT_PIN7)
#define PORT_I2S_SD1_1 (PORT_FUNCG | PORTA | PORT_PIN8)
#define PORT_I2S_SD1_2 (PORT_FUNCG | PORTB | PORT_PIN16)
/* Non maskable interrupt */
#define PORT_NMI (PORT_FUNCA | PORTA | PORT_PIN8)
/* Serial communication interface (SERCOM) */
#define PORT_SERCOM0_PAD0_1 (PORT_FUNCC | PORTA | PORT_PIN8)
#define PORT_SERCOM0_PAD0_2 (PORT_FUNCD | PORTA | PORT_PIN4)
#define PORT_SERCOM0_PAD1_1 (PORT_FUNCC | PORTA | PORT_PIN9)
#define PORT_SERCOM0_PAD1_2 (PORT_FUNCD | PORTA | PORT_PIN5)
#define PORT_SERCOM0_PAD2_1 (PORT_FUNCC | PORTA | PORT_PIN10)
#define PORT_SERCOM0_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN6)
#define PORT_SERCOM0_PAD3_1 (PORT_FUNCC | PORTA | PORT_PIN11)
#define PORT_SERCOM0_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN7)
#define PORT_SERCOM1_PAD0_1 (PORT_FUNCC | PORTA | PORT_PIN16)
#define PORT_SERCOM1_PAD0_2 (PORT_FUNCD | PORTA | PORT_PIN0)
#define PORT_SERCOM1_PAD1_1 (PORT_FUNCC | PORTA | PORT_PIN17)
#define PORT_SERCOM1_PAD1_2 (PORT_FUNCD | PORTA | PORT_PIN1)
#define PORT_SERCOM1_PAD2_1 (PORT_FUNCC | PORTA | PORT_PIN18)
#define PORT_SERCOM1_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN30)
#define PORT_SERCOM1_PAD3_1 (PORT_FUNCC | PORTA | PORT_PIN19)
#define PORT_SERCOM1_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN31)
#define PORT_SERCOM2_PAD0_1 (PORT_FUNCC | PORTA | PORT_PIN12)
#define PORT_SERCOM2_PAD0_2 (PORT_FUNCD | PORTA | PORT_PIN8)
#define PORT_SERCOM2_PAD1_1 (PORT_FUNCC | PORTA | PORT_PIN13)
#define PORT_SERCOM2_PAD1_2 (PORT_FUNCD | PORTA | PORT_PIN9)
#define PORT_SERCOM2_PAD2_1 (PORT_FUNCC | PORTA | PORT_PIN14)
#define PORT_SERCOM2_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN10)
#define PORT_SERCOM2_PAD3_1 (PORT_FUNCC | PORTA | PORT_PIN15)
#define PORT_SERCOM2_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN11)
#define PORT_SERCOM3_PAD0_1 (PORT_FUNCC | PORTA | PORT_PIN22)
#define PORT_SERCOM3_PAD0_2 (PORT_FUNCD | PORTA | PORT_PIN16)
#define PORT_SERCOM3_PAD1_1 (PORT_FUNCC | PORTA | PORT_PIN23)
#define PORT_SERCOM3_PAD1_2 (PORT_FUNCD | PORTA | PORT_PIN17)
#define PORT_SERCOM3_PAD2_1 (PORT_FUNCC | PORTA | PORT_PIN24)
#define PORT_SERCOM3_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN18)
#define PORT_SERCOM3_PAD2_3 (PORT_FUNCD | PORTA | PORT_PIN20)
#define PORT_SERCOM3_PAD3_1 (PORT_FUNCC | PORTA | PORT_PIN25)
#define PORT_SERCOM3_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN19)
#define PORT_SERCOM3_PAD3_3 (PORT_FUNCD | PORTA | PORT_PIN21)
#define PORT_SERCOM4_PAD0_1 (PORT_FUNCC | PORTB | PORT_PIN12)
#define PORT_SERCOM4_PAD0_2 (PORT_FUNCD | PORTA | PORT_PIN12)
#define PORT_SERCOM4_PAD0_3 (PORT_FUNCD | PORTB | PORT_PIN8)
#define PORT_SERCOM4_PAD1_1 (PORT_FUNCC | PORTB | PORT_PIN13)
#define PORT_SERCOM4_PAD1_2 (PORT_FUNCD | PORTA | PORT_PIN13)
#define PORT_SERCOM4_PAD1_3 (PORT_FUNCD | PORTB | PORT_PIN9)
#define PORT_SERCOM4_PAD2_1 (PORT_FUNCC | PORTB | PORT_PIN14)
#define PORT_SERCOM4_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN14)
#define PORT_SERCOM4_PAD2_3 (PORT_FUNCD | PORTB | PORT_PIN10)
#define PORT_SERCOM4_PAD3_1 (PORT_FUNCC | PORTB | PORT_PIN15)
#define PORT_SERCOM4_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN15)
#define PORT_SERCOM4_PAD3_3 (PORT_FUNCD | PORTB | PORT_PIN11)
#define PORT_SERCOM5_PAD0_1 (PORT_FUNCC | PORTB | PORT_PIN16)
#define PORT_SERCOM5_PAD0_2 (PORT_FUNCD | PORTA | PORT_PIN22)
#define PORT_SERCOM5_PAD0_3 (PORT_FUNCD | PORTB | PORT_PIN2)
#define PORT_SERCOM5_PAD0_4 (PORT_FUNCD | PORTB | PORT_PIN30)
#define PORT_SERCOM5_PAD1_1 (PORT_FUNCC | PORTB | PORT_PIN17)
#define PORT_SERCOM5_PAD1_2 (PORT_FUNCD | PORTA | PORT_PIN23)
#define PORT_SERCOM5_PAD1_3 (PORT_FUNCD | PORTB | PORT_PIN3)
#define PORT_SERCOM5_PAD1_4 (PORT_FUNCD | PORTB | PORT_PIN31)
#define PORT_SERCOM5_PAD2_1 (PORT_FUNCC | PORTA | PORT_PIN20)
#define PORT_SERCOM5_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN24)
#define PORT_SERCOM5_PAD2_3 (PORT_FUNCD | PORTB | PORT_PIN0)
#define PORT_SERCOM5_PAD2_4 (PORT_FUNCD | PORTB | PORT_PIN22)
#define PORT_SERCOM5_PAD3_1 (PORT_FUNCC | PORTA | PORT_PIN21)
#define PORT_SERCOM5_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN25)
#define PORT_SERCOM5_PAD3_3 (PORT_FUNCD | PORTB | PORT_PIN1)
#define PORT_SERCOM5_PAD3_4 (PORT_FUNCD | PORTB | PORT_PIN23)
/* JTAG/SWI */
#define PORT_SWCLK (PORT_FUNCG | PORTA | PORT_PIN30)
#define PORT_SWDIO (PORT_FUNCG | PORTA | PORT_PIN31)
/* Timer/Counters */
#define PORT_TC3_WO0_1 (PORT_FUNCE | PORTA | PORT_PIN14)
#define PORT_TC3_WO0_2 (PORT_FUNCE | PORTA | PORT_PIN18)
#define PORT_TC3_WO1_1 (PORT_FUNCE | PORTA | PORT_PIN15)
#define PORT_TC3_WO1_2 (PORT_FUNCE | PORTA | PORT_PIN19)
#define PORT_TC4_WO0_1 (PORT_FUNCE | PORTA | PORT_PIN22)
#define PORT_TC4_WO0_2 (PORT_FUNCE | PORTB | PORT_PIN12)
#define PORT_TC4_WO0_3 (PORT_FUNCE | PORTB | PORT_PIN8)
#define PORT_TC4_WO1_1 (PORT_FUNCE | PORTA | PORT_PIN23)
#define PORT_TC4_WO1_2 (PORT_FUNCE | PORTB | PORT_PIN13)
#define PORT_TC4_WO1_3 (PORT_FUNCE | PORTB | PORT_PIN9)
#define PORT_TC5_WO0_1 (PORT_FUNCE | PORTA | PORT_PIN24)
#define PORT_TC5_WO0_2 (PORT_FUNCE | PORTB | PORT_PIN10)
#define PORT_TC5_WO0_3 (PORT_FUNCE | PORTB | PORT_PIN14)
#define PORT_TC5_WO1_1 (PORT_FUNCE | PORTA | PORT_PIN25)
#define PORT_TC5_WO1_2 (PORT_FUNCE | PORTB | PORT_PIN11)
#define PORT_TC5_WO1_3 (PORT_FUNCE | PORTB | PORT_PIN15)
#define PORT_TC6_WO0_1 (PORT_FUNCE | PORTB | PORT_PIN16)
#define PORT_TC6_WO0_2 (PORT_FUNCE | PORTB | PORT_PIN2)
#define PORT_TC6_WO1_1 (PORT_FUNCE | PORTB | PORT_PIN17)
#define PORT_TC6_WO1_2 (PORT_FUNCE | PORTB | PORT_PIN3)
#define PORT_TC7_WO0_1 (PORT_FUNCE | PORTA | PORT_PIN20)
#define PORT_TC7_WO0_2 (PORT_FUNCE | PORTB | PORT_PIN0)
#define PORT_TC7_WO0_3 (PORT_FUNCE | PORTB | PORT_PIN22)
#define PORT_TC7_WO1_1 (PORT_FUNCE | PORTA | PORT_PIN21)
#define PORT_TC7_WO1_2 (PORT_FUNCE | PORTB | PORT_PIN1)
#define PORT_TC7_WO1_3 (PORT_FUNCE | PORTB | PORT_PIN23)
/* Timer/Counters for Control */
#define PORT_TCC0_WO0_1 (PORT_FUNCE | PORTA | PORT_PIN4)
#define PORT_TCC0_WO0_2 (PORT_FUNCE | PORTA | PORT_PIN8)
#define PORT_TCC0_WO0_3 (PORT_FUNCE | PORTB | PORT_PIN30)
#define PORT_TCC0_WO1_1 (PORT_FUNCE | PORTA | PORT_PIN5)
#define PORT_TCC0_WO1_2 (PORT_FUNCE | PORTA | PORT_PIN9)
#define PORT_TCC0_WO1_3 (PORT_FUNCE | PORTB | PORT_PIN31)
#define PORT_TCC0_WO2_1 (PORT_FUNCF | PORTA | PORT_PIN18)
#define PORT_TCC0_WO2_2 (PORT_FUNCE | PORTA | PORT_PIN10)
#define PORT_TCC0_WO3_1 (PORT_FUNCF | PORTA | PORT_PIN11)
#define PORT_TCC0_WO3_2 (PORT_FUNCF | PORTA | PORT_PIN19)
#define PORT_TCC0_WO4_1 (PORT_FUNCF | PORTA | PORT_PIN14)
#define PORT_TCC0_WO4_2 (PORT_FUNCF | PORTA | PORT_PIN22)
#define PORT_TCC0_WO4_3 (PORT_FUNCF | PORTB | PORT_PIN10)
#define PORT_TCC0_WO4_4 (PORT_FUNCF | PORTB | PORT_PIN16)
#define PORT_TCC0_WO5_1 (PORT_FUNCF | PORTA | PORT_PIN15)
#define PORT_TCC0_WO5_2 (PORT_FUNCF | PORTA | PORT_PIN23)
#define PORT_TCC0_WO5_3 (PORT_FUNCF | PORTB | PORT_PIN11)
#define PORT_TCC0_WO5_4 (PORT_FUNCF | PORTB | PORT_PIN17)
#define PORT_TCC0_WO6_1 (PORT_FUNCF | PORTA | PORT_PIN12)
#define PORT_TCC0_WO6_2 (PORT_FUNCF | PORTA | PORT_PIN16)
#define PORT_TCC0_WO6_3 (PORT_FUNCF | PORTA | PORT_PIN20)
#define PORT_TCC0_WO6_4 (PORT_FUNCF | PORTB | PORT_PIN12)
#define PORT_TCC0_WO7_1 (PORT_FUNCF | PORTA | PORT_PIN13)
#define PORT_TCC0_WO7_2 (PORT_FUNCF | PORTA | PORT_PIN17)
#define PORT_TCC0_WO7_3 (PORT_FUNCF | PORTA | PORT_PIN21)
#define PORT_TCC0_WO7_4 (PORT_FUNCF | PORTB | PORT_PIN13)
#define PORT_TCC1_WO0_1 (PORT_FUNCE | PORTA | PORT_PIN10)
#define PORT_TCC1_WO0_2 (PORT_FUNCE | PORTA | PORT_PIN30)
#define PORT_TCC1_WO0_3 (PORT_FUNCE | PORTA | PORT_PIN6)
#define PORT_TCC1_WO1_1 (PORT_FUNCE | PORTA | PORT_PIN11)
#define PORT_TCC1_WO1_2 (PORT_FUNCE | PORTA | PORT_PIN31)
#define PORT_TCC1_WO1_3 (PORT_FUNCE | PORTA | PORT_PIN7)
#define PORT_TCC1_WO2_1 (PORT_FUNCF | PORTA | PORT_PIN24)
#define PORT_TCC1_WO2_2 (PORT_FUNCF | PORTA | PORT_PIN8)
#define PORT_TCC1_WO2_3 (PORT_FUNCF | PORTB | PORT_PIN30)
#define PORT_TCC1_WO3_1 (PORT_FUNCF | PORTA | PORT_PIN25)
#define PORT_TCC1_WO3_2 (PORT_FUNCF | PORTA | PORT_PIN9)
#define PORT_TCC1_WO3_3 (PORT_FUNCF | PORTB | PORT_PIN31)
#define PORT_TCC2_WO0_1 (PORT_FUNCE | PORTA | PORT_PIN0)
#define PORT_TCC2_WO0_2 (PORT_FUNCE | PORTA | PORT_PIN12)
#define PORT_TCC2_WO0_3 (PORT_FUNCE | PORTA | PORT_PIN16)
#define PORT_TCC2_WO1_1 (PORT_FUNCE | PORTA | PORT_PIN1)
#define PORT_TCC2_WO1_2 (PORT_FUNCE | PORTA | PORT_PIN13)
#define PORT_TCC2_WO1_3 (PORT_FUNCE | PORTA | PORT_PIN17)
/* USB */
#define PORT_USB_DM (PORT_FUNCG | PORTA | PORT_PIN24)
#define PORT_USB_DP (PORT_FUNCG | PORTA | PORT_PIN25)
#define PORT_USB_SOF (PORT_FUNCG | PORTA | PORT_PIN23)
/* Peripheral touch controller */
#define PORT_PTC_X0 (PORT_PTC_FUNCB | PORTA | PORT_PTC_PIN8)
#define PORT_PTC_X1 (PORT_PTC_FUNCB | PORTA | PORT_PTC_PIN9)
#define PORT_PTC_X2 (PORT_PTC_FUNCB | PORTA | PORT_PTC_PIN10)
#define PORT_PTC_X3 (PORT_PTC_FUNCB | PORTA | PORT_PTC_PIN11)
#define PORT_PTC_X4 (PORT_PTC_FUNCB | PORTA | PORT_PTC_PIN16)
#define PORT_PTC_X5 (PORT_PTC_FUNCB | PORTA | PORT_PTC_PIN17)
#define PORT_PTC_X6 (PORT_PTC_FUNCB | PORTA | PORT_PTC_PIN18)
#define PORT_PTC_X7 (PORT_PTC_FUNCB | PORTA | PORT_PTC_PIN19)
#define PORT_PTC_X8 (PORT_PTC_FUNCB | PORTA | PORT_PTC_PIN20)
#define PORT_PTC_X9 (PORT_PTC_FUNCB | PORTA | PORT_PTC_PIN21)
#define PORT_PTC_X10 (PORT_PTC_FUNCB | PORTA | PORT_PTC_PIN22)
#define PORT_PTC_X11 (PORT_PTC_FUNCB | PORTA | PORT_PTC_PIN23)
#define PORT_PTC_X12 (PORT_PTC_FUNCB | PORTB | PORT_PTC_PIN12)
#define PORT_PTC_X13 (PORT_PTC_FUNCB | PORTB | PORT_PTC_PIN13)
#define PORT_PTC_X14 (PORT_PTC_FUNCB | PORTB | PORT_PTC_PIN14)
#define PORT_PTC_X15 (PORT_PTC_FUNCB | PORTB | PORT_PTC_PIN15)
#define PORT_PTC_Y0 (PORT_PTC_FUNCB | PORTA | PORT_PTC_PIN2)
#define PORT_PTC_Y1 (PORT_PTC_FUNCB | PORTA | PORT_PTC_PIN3)
#define PORT_PTC_Y2 (PORT_PTC_FUNCB | PORTA | PORT_PTC_PIN4)
#define PORT_PTC_Y3 (PORT_PTC_FUNCB | PORTA | PORT_PTC_PIN5)
#define PORT_PTC_Y4 (PORT_PTC_FUNCB | PORTA | PORT_PTC_PIN6)
#define PORT_PTC_Y5 (PORT_PTC_FUNCB | PORTA | PORT_PTC_PIN7)
#define PORT_PTC_Y6 (PORT_PTC_FUNCB | PORTB | PORT_PTC_PIN0)
#define PORT_PTC_Y7 (PORT_PTC_FUNCB | PORTB | PORT_PTC_PIN1)
#define PORT_PTC_Y8 (PORT_PTC_FUNCB | PORTB | PORT_PTC_PIN2)
#define PORT_PTC_Y9 (PORT_PTC_FUNCB | PORTB | PORT_PTC_PIN3)
#define PORT_PTC_Y10 (PORT_PTC_FUNCB | PORTB | PORT_PTC_PIN4)
#define PORT_PTC_Y11 (PORT_PTC_FUNCB | PORTB | PORT_PTC_PIN5)
#define PORT_PTC_Y12 (PORT_PTC_FUNCB | PORTB | PORT_PTC_PIN6)
#define PORT_PTC_Y13 (PORT_PTC_FUNCB | PORTB | PORT_PTC_PIN7)
#define PORT_PTC_Y14 (PORT_PTC_FUNCB | PORTB | PORT_PTC_PIN8)
#define PORT_PTC_Y15 (PORT_PTC_FUNCB | PORTB | PORT_PTC_PIN9)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_PINMAP_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_ac.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Matt Thompson <matt@extent3d.com>
*
* References:
* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_AC_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_AC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_ARCH_FAMILY_SAMD21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* AC register offsets ******************************************************/
#define SAM_AC_CTRLA_OFFSET 0x0000 /* Control A Register */
#define SAM_AC_CTRLB_OFFSET 0x0001 /* Control B Register */
#define SAM_AC_EVCTRL_OFFSET 0x0002 /* Event Control Register */
#define SAM_AC_INTENCLR_OFFSET 0x0004 /* Interrupt Enable Clear Register */
#define SAM_AC_INTENSET_OFFSET 0x0005 /* Interrupt Enable Set Register */
#define SAM_AC_INTFLAG_OFFSET 0x0006 /* Interrupt Flag Status and Clear Register */
#define SAM_AC_STATUSA_OFFSET 0x0008 /* Status A Register */
#define SAM_AC_STATUSB_OFFSET 0x0009 /* Status B Register */
#define SAM_AC_STATUSC_OFFSET 0x000A /* Status C Register */
#define SAM_AC_WINCTRL_OFFSET 0x000C /* Window Control Register */
#define SAM_AC_COMPCTRL0_OFFSET 0x0010 /* Comparator 0 Control Register */
#define SAM_AC_COMPCTRL1_OFFSET 0x0014 /* Comparator 1 Control Register */
#define SAM_AC_SCALER0_OFFSET 0x0020 /* Scaler 0 Register */
#define SAM_AC_SCALER1_OFFSET 0x0021 /* Scaler 1 Register */
/* AC register addresses ****************************************************/
#define SAM_AC_CTRLA (SAM_AC_BASE+SAM_AC_CTRLA_OFFSET)
#define SAM_AC_CTRLB (SAM_AC_BASE+SAM_AC_CTRLB_OFFSET)
#define SAM_AC_EVCTRL (SAM_AC_BASE+SAM_AC_EVCTRL_OFFSET)
#define SAM_AC_INTENCLR (SAM_AC_BASE+SAM_AC_INTENCLR_OFFSET)
#define SAM_AC_INTENSET (SAM_AC_BASE+SAM_AC_INTENSET_OFFSET)
#define SAM_AC_INTFLAG (SAM_AC_BASE+SAM_AC_INTFLAG_OFFSET)
#define SAM_AC_STATUSA (SAM_AC_BASE+SAM_AC_STATUSA_OFFSET)
#define SAM_AC_STATUSB (SAM_AC_BASE+SAM_AC_STATUSB_OFFSET)
#define SAM_AC_STATUSC (SAM_AC_BASE+SAM_AC_STATUSC_OFFSET)
#define SAM_AC_WINCTRL (SAM_AC_BASE+SAM_AC_WINCTRL_OFFSET)
#define SAM_AC_COMPCTRL0 (SAM_AC_BASE+SAM_AC_COMPCTRL0_OFFSET)
#define SAM_AC_COMPCTRL1 (SAM_AC_BASE+SAM_AC_COMPCTRL1_OFFSET)
#define SAM_AC_SCALER0 (SAM_AC_BASE+SAM_AC_SCALER0_OFFSET)
#define SAM_AC_SCALER1 (SAM_AC_BASE+SAM_AC_SCALER1_OFFSET)
/* AC register bit definitions **********************************************/
/* Control A Register */
#define AC_CTRLA_SWRTS (1 << 0) /* Bit 0: Software reset */
#define AC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable AC */
#define AC_CTRLA_RUNSTDBY (1 << 2) /* Bit 2: Run in standby */
#define AC_CTRLA_LPMUX (1 << 7) /* Bit 7: Low-Power Mux */
/* Control B Register */
#define AC_CTRLB_START0 (1 << 0) /* Bit 0: Comparator 0 start */
#define AC_CTRLB_START1 (1 << 1) /* Bit 1: Comparator 1 start */
/* Event Control Register */
#define AC_EVCTRL_COMPEO0 (1 << 0) /* Bit 0: Comparator 0 Event Output enable */
#define AC_EVCTRL_COMPEO1 (1 << 1) /* Bit 1: Comparator 1 Event Output enable */
#define AC_EVCTRL_WINEO0 (1 << 4) /* Bit 4: Window 0 Event Output enable */
#define AC_EVCTRL_COMPEI0 (1 << 8) /* Bit 8: Comparator 0 Event Input enable */
#define AC_EVCTRL_COMPEI1 (1 << 9) /* Bit 9: Comparator 1 Event Input enable */
/* Common bit definitions for Interrupt Enable Clear Register, Interrupt
* Enable Set Register, and Interrupt Flag Status and Clear Register
*/
#define AC_INT_COMP0 (1 << 0) /* Bit 0: Comparator 0 */
#define AC_INT_COMP1 (1 << 1) /* Bit 1: Comparator 1 */
#define AC_INT_WIN0 (1 << 4) /* Bit 4: Window 0 */
#define AC_INT_ALL 0x13
/* Status A Register */
#define AC_STATUSA_STATE0 (1 << 0) /* Bit 0: State 0 - Output state of comparator 0 */
#define AC_STATUSA_STATE1 (1 << 1) /* Bit 1: State 1 - Output state of comparator 1 */
#define AC_STATUSA_WSTATE_SHIFT (4)
#define AC_STATUSA_WSTATE_MASK (3 << AC_STATUSA_WSTATE_SHIFT)
# define AC_STATUSA_WSTATE_ABOVE (0 << AC_STATUSA_WSTATE_SHIFT)
# define AC_STATUSA_WSTATE_INSIDE (1 << AC_STATUSA_WSTATE_SHIFT)
# define AC_STATUSA_WSTATE_BELOW (2 << AC_STATUSA_WSTATE_SHIFT)
/* Status B Register */
#define AC_STATUSB_READY0 (1 << 0) /* Bit 0: Ready 0 - Comparator 0 ready status */
#define AC_STATUSB_READY1 (1 << 1) /* Bit 1: Ready 1 - Comparator 1 ready status */
#define AC_STATUSB_SYNCBUSY (1 << 7) /* Bit 7: Synchronoziation ready */
/* Status C Register */
/* Window Control Register */
#define AC_WINCTRL_WEN0 (1 << 0) /* Bit 0: Window enable (both comparators) */
#define AC_WINCTRL_WINTSEL_SHIFT (1)
#define AC_WINCTRL_WINTSEL_MASK (3 << AC_WINCTRL_WINTSEL_SHIFT)
# define AC_WINCTRL_WINTSEL_ABOVE (0 << AC_WINCTRL_WINTSEL_SHIFT)
# define AC_WINCTRL_WINTSEL_INSIDE (1 << AC_WINCTRL_WINTSEL_SHIFT)
# define AC_WINCTRL_WINTSEL_BELOW (2 << AC_WINCTRL_WINTSEL_SHIFT)
# define AC_WINCTRL_WINTSEL_OUTSIDE (3 << AC_WINCTRL_WINTSEL_SHIFT)
/* Comparator Control Registers */
#define AC_COMPCTRL_ENABLE (1 << 0) /* Bit 0: Enable Comparator */
#define AC_COMPCTRL_SINGLE (1 << 1) /* Bit 1: Single Shot Mode */
#define AC_COMPCTRL_SPEED_SHIFT (2)
#define AC_COMPCTRL_SPEED_MASK (3 << AC_COMPCTRL_SPEED_SHIFT)
# define AC_COMPCTRL_SPEED_LOW (0 << AC_COMPCTRL_SPEED_SHIFT)
# define AC_COMPCTRL_SPEED_HIGH (1 << AC_COMPCTRL_SPEED_SHIFT)
#define AC_COMPCTRL_INTSEL_SHIFT (5)
#define AC_COMPCTRL_INTSEL_MASK (3 << AC_COMPCTRL_INTSEL_SHIFT)
# define AC_COMPCTRL_INTSEL_TOGGLE (0 << AC_COMPCTRL_INTSEL_SHIFT)
# define AC_COMPCTRL_INTSEL_RISING (1 << AC_COMPCTRL_INTSEL_SHIFT)
# define AC_COMPCTRL_INTSEL_FALLING (2 << AC_COMPCTRL_INTSEL_SHIFT)
# define AC_COMPCTRL_INTSEL_EOC (3 << AC_COMPCTRL_INTSEL_SHIFT)
#define AC_COMPCTRL_MUXNEG_SHIFT (8)
#define AC_COMPCTRL_MUXNEG_MASK (7 << AC_COMPCTRL_MUXNEG_SHIFT)
# define AC_COMPCTRL_MUXNEG_PIN0 (0 << AC_COMPCTRL_MUXNEG_SHIFT)
# define AC_COMPCTRL_MUXNEG_PIN1 (1 << AC_COMPCTRL_MUXNEG_SHIFT)
# define AC_COMPCTRL_MUXNEG_PIN2 (2 << AC_COMPCTRL_MUXNEG_SHIFT)
# define AC_COMPCTRL_MUXNEG_PIN3 (3 << AC_COMPCTRL_MUXNEG_SHIFT)
# define AC_COMPCTRL_MUXNEG_GND (4 << AC_COMPCTRL_MUXNEG_SHIFT)
# define AC_COMPCTRL_MUXNEG_VSCALE (5 << AC_COMPCTRL_MUXNEG_SHIFT)
# define AC_COMPCTRL_MUXNEG_BANDGAP (6 << AC_COMPCTRL_MUXNEG_SHIFT)
# define AC_COMPCTRL_MUXNEG_DAC (7 << AC_COMPCTRL_MUXNEG_SHIFT)
#define AC_COMPCTRL_MUXPOS_SHIFT (12)
#define AC_COMPCTRL_MUXPOS_MASK (3 << AC_COMPCTRL_MUXPOS_SHIFT)
# define AC_COMPCTRL_MUXPOS_PIN0 (0 << AC_COMPCTRL_MUXPOS_SHIFT)
# define AC_COMPCTRL_MUXPOS_PIN1 (1 << AC_COMPCTRL_MUXPOS_SHIFT)
# define AC_COMPCTRL_MUXPOS_PIN2 (2 << AC_COMPCTRL_MUXPOS_SHIFT)
# define AC_COMPCTRL_MUXPOS_PIN3 (3 << AC_COMPCTRL_MUXPOS_SHIFT)
#define AC_COMPCTRL_SWAP (1 << 13) /* Bit 13: Swap Inputs and Invert */
#define AC_COMPCTRL_OUT_SHIFT (16)
#define AC_COMPCTRL_OUT_MASK (3 << AC_COMPCTRL_OUT_SHIFT)
# define AC_COMPCTRL_OUT_OFF (0 << AC_COMPCTRL_OUT_SHIFT)
# define AC_COMPCTRL_OUT_ASYNC (1 << AC_COMPCTRL_OUT_SHIFT)
# define AC_COMPCTRL_OUT_SYNC (2 << AC_COMPCTRL_OUT_SHIFT)
#define AC_COMPCTRL_HYST (1 << 19) /* Bit 19: Hysteresis Enable */
#define AC_COMPCTRL_FLEN_SHIFT (24)
#define AC_COMPCTRL_FLEN_MASK (7 << AC_COMPCTRL_FLEN_SHIFT)
# define AC_COMPCTRL_FLEN_OFF (0 << AC_COMPCTRL_FLEN_SHIFT)
# define AC_COMPCTRL_FLEN_MAJ3 (1 << AC_COMPCTRL_FLEN_SHIFT)
# define AC_COMPCTRL_FLEN_MAJ5 (2 << AC_COMPCTRL_FLEN_SHIFT)
/* Scaler Registers */
#define AC_COMPCTRL_SCALER_MASK (0x3f)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_AC_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_adc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Alexander Vasiljev <alexvasiljev@gmail.com>
*
* References:
* "Microchip SAM D21 Family Datasheet", Rev D - 9/2018
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_ADC_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_ADC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_ARCH_FAMILY_SAMD21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* ADC register offsets *****************************************************/
#define SAM_ADC_CTRLA_OFFSET 0x0000 /* Control A Register */
#define SAM_ADC_REFCTL_OFFSET 0x0001 /* Reference Control Register */
#define SAM_ADC_AVGCTRL_OFFSET 0x0002 /* Average Control Register */
#define SAM_ADC_SAMPCTRL_OFFSET 0x0003 /* Sampling Time Control Register */
#define SAM_ADC_CTRLB_OFFSET 0x0004 /* Control B Register */
#define SAM_ADC_WINCTRL_OFFSET 0x0008 /* Window Monitor Control Register */
#define SAM_ADC_SWTRIG_OFFSET 0x000C /* Software Trigger Register */
#define SAM_ADC_INPUTCTRL_OFFSET 0x0010 /* Input Control Register */
#define SAM_ADC_EVCTRL_OFFSET 0x0014 /* Event Control Register */
#define SAM_ADC_INTENCLR_OFFSET 0x0016 /* Interrupt Enable Clear Register */
#define SAM_ADC_INTENSET_OFFSET 0x0017 /* Interrupt Enable Set Register */
#define SAM_ADC_INTFLAG_OFFSET 0x0018 /* Interrupt Flag Status and Clear Register */
#define SAM_ADC_STATUS_OFFSET 0x0019 /* Status Register */
#define SAM_ADC_RESULT_OFFSET 0x001A /* Result Register */
#define SAM_ADC_WINLT_OFFSET 0x001C /* Window Monitor Lower Threshold Register */
#define SAM_ADC_WINUT_OFFSET 0x0020 /* Window Monitor Upper Threshold Register */
#define SAM_ADC_GAINCORR_OFFSET 0x0024 /* Gain Correction Register */
#define SAM_ADC_OFFSETCORR_OFFSET 0x0026 /* Offset Correction Register */
#define SAM_ADC_CALIB_OFFSET 0x0028 /* Calibration Register */
#define SAM_ADC_DBGCTRL_OFFSET 0x002A /* Debug Control Register */
/* ADC register addresses ***************************************************/
#define SAM_ADC_CTRLA (SAM_ADC_BASE + SAM_ADC_CTRLA_OFFSET)
#define SAM_ADC_REFCTL (SAM_ADC_BASE + SAM_ADC_REFCTL_OFFSET)
#define SAM_ADC_AVGCTRL (SAM_ADC_BASE + SAM_ADC_AVGCTRL_OFFSET)
#define SAM_ADC_SAMPCTRL (SAM_ADC_BASE + SAM_ADC_SAMPCTRL_OFFSET)
#define SAM_ADC_CTRLB (SAM_ADC_BASE + SAM_ADC_CTRLB_OFFSET)
#define SAM_ADC_WINCTRL (SAM_ADC_BASE + SAM_ADC_WINCTRL_OFFSET)
#define SAM_ADC_SWTRIG (SAM_ADC_BASE + SAM_ADC_SWTRIG_OFFSET)
#define SAM_ADC_INPUTCTRL (SAM_ADC_BASE + SAM_ADC_INPUTCTRL_OFFSET)
#define SAM_ADC_EVCTRL (SAM_ADC_BASE + SAM_ADC_EVCTRL_OFFSET)
#define SAM_ADC_INTENCLR (SAM_ADC_BASE + SAM_ADC_INTENCLR_OFFSET)
#define SAM_ADC_INTENSET (SAM_ADC_BASE + SAM_ADC_INTENSET_OFFSET)
#define SAM_ADC_INTFLAG (SAM_ADC_BASE + SAM_ADC_INTFLAG_OFFSET)
#define SAM_ADC_STATUS (SAM_ADC_BASE + SAM_ADC_STATUS_OFFSET)
#define SAM_ADC_RESULT (SAM_ADC_BASE + SAM_ADC_RESULT_OFFSET)
#define SAM_ADC_WINLT (SAM_ADC_BASE + SAM_ADC_WINLT_OFFSET)
#define SAM_ADC_WINUT (SAM_ADC_BASE + SAM_ADC_WINUT_OFFSET)
#define SAM_ADC_GAINCORR (SAM_ADC_BASE + SAM_ADC_GAINCORR_OFFSET)
#define SAM_ADC_OFFSETCORR (SAM_ADC_BASE + SAM_ADC_OFFSETCORR_OFFSET)
#define SAM_ADC_CALIB (SAM_ADC_BASE + SAM_ADC_CALIB_OFFSET)
#define SAM_ADC_ADC_DBGCTRL (SAM_ADC_BASE + SAM_ADC_DBGCTRL_OFFSET)
/* ADC register bit definitions *********************************************/
/* Control A Register */
#define ADC_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
#define ADC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable ADC controller */
#define ADC_CTRLA_RUNSTDBY (1 << 2) /* Bit 2: Run in standby */
/* Reference Control Register */
#define ADC_REFCTRL_REFSEL_OFFSET (0) /* Bit 3:0: Reference selection */
#define ADC_REFCTRL_REFSEL_MASK (0x0F << ADC_REFCTRL_REFSEL_OFFSET)
# define ADC_REFCTRL_REFSEL_INT1V (0 << ADC_REFCTRL_REFSEL_OFFSET) /* 1.0V voltage reference */
# define ADC_REFCTRL_REFSEL_INTVCC0 (1 << ADC_REFCTRL_REFSEL_OFFSET) /* 1/1.48 VDDANA */
# define ADC_REFCTRL_REFSEL_INTVCC1 (2 << ADC_REFCTRL_REFSEL_OFFSET) /* 1/2 VDDANA (only for VDDANA > 2.0V) */
# define ADC_REFCTRL_REFSEL_VREFA (3 << ADC_REFCTRL_REFSEL_OFFSET) /* External reference */
# define ADC_REFCTRL_REFSEL_VREFB (4 << ADC_REFCTRL_REFSEL_OFFSET) /* External reference */
#define ADC_REFCTRL_REFCOMP (1 << 7) /* Bit 7: Reference buffer offset compensation enable */
/* Average Control Register */
#define ADC_AVGCTRL_SAMPLENUM_OFFSET (0) /* Bit 3:0: Number of samples to be collected */
#define ADC_AVGCTRL_SAMPLENUM_MASK (0x0F << ADC_AVGCTRL_SAMPLENUM_OFFSET)
# define ADC_AVGCTRL_SAMPLENUM_1 (0x00 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
# define ADC_AVGCTRL_SAMPLENUM_2 (0x01 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
# define ADC_AVGCTRL_SAMPLENUM_4 (0x02 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
# define ADC_AVGCTRL_SAMPLENUM_8 (0x03 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
# define ADC_AVGCTRL_SAMPLENUM_16 (0x04 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
# define ADC_AVGCTRL_SAMPLENUM_32 (0x05 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
# define ADC_AVGCTRL_SAMPLENUM_64 (0x06 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
# define ADC_AVGCTRL_SAMPLENUM_128 (0x07 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
# define ADC_AVGCTRL_SAMPLENUM_256 (0x08 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
# define ADC_AVGCTRL_SAMPLENUM_512 (0x09 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
# define ADC_AVGCTRL_SAMPLENUM_1024 (0x0A << ADC_AVGCTRL_SAMPLENUM_OFFSET)
#define ADC_AVGCTRL_ADJRES_OFFSET (1 << 4) /* Bit 4:6: Adjusting result/division coefficient */
#define ADC_AVGCTRL_ADJRES_MASK (7 << ADC_AVGCTRL_ADJRES_OFFSET)
/* Sampling Time Control Register */
#define ADC_SAMPCTRL_SAMPLEN_OFFSET (0) /* Bit 5:0:Sampling time length */
#define ADC_SAMPCTRL_SAMPLEN_MASK (0x3F << ADC_SAMPCTRL_SAMPLEN_OFFSET)
/* Control B Register */
#define ADC_CTRLB_DIFFMODE (1 << 0) /* Bit 0: Differenstial mode */
#define ADC_CTRLB_LEFTADJ (1 << 1) /* Bit 1: Left-adjusted result */
#define ADC_CTRLB_FREERUN (1 << 2) /* Bit 2: Free running mode */
#define ADC_CTRLB_CORREN (1 << 3) /* Bit 3: Digital correction logic enabled */
#define ADC_CTRLB_RESSEL_OFFSET (4) /* Bit 5:4: Conversion result resolution */
#define ADC_CTRLB_RESSEL_MASK (3 << ADC_CTRLB_RESSEL_OFFSET)
# define ADC_CTRLB_RESSEL_12BIT (0 << ADC_CTRLB_RESSEL_OFFSET) /* 12-bit result */
# define ADC_CTRLB_RESSEL_16BIT (1 << ADC_CTRLB_RESSEL_OFFSET) /* For averaging mode output */
# define ADC_CTRLB_RESSEL_10BIT (2 << ADC_CTRLB_RESSEL_OFFSET) /* 10-bit result */
# define ADC_CTRLB_RESSEL_8BIT (3 << ADC_CTRLB_RESSEL_OFFSET) /* 8-bit result */
#define ADC_CTRLB_PRESCALER_OFFSET (8) /* Bit 10:8: Prescaler configuration */
#define ADC_CTRLB_PRESCALER_MASK (7 << ADC_CTRLB_PRESCALER_OFFSET)
# define ADC_CTRLB_PRESCALER_DIV4 (0 << ADC_CTRLB_PRESCALER_OFFSET)
# define ADC_CTRLB_PRESCALER_DIV8 (1 << ADC_CTRLB_PRESCALER_OFFSET)
# define ADC_CTRLB_PRESCALER_DIV16 (2 << ADC_CTRLB_PRESCALER_OFFSET)
# define ADC_CTRLB_PRESCALER_DIV32 (3 << ADC_CTRLB_PRESCALER_OFFSET)
# define ADC_CTRLB_PRESCALER_DIV64 (4 << ADC_CTRLB_PRESCALER_OFFSET)
# define ADC_CTRLB_PRESCALER_DIV128 (5 << ADC_CTRLB_PRESCALER_OFFSET)
# define ADC_CTRLB_PRESCALER_DIV256 (6 << ADC_CTRLB_PRESCALER_OFFSET)
# define ADC_CTRLB_PRESCALER_DIV512 (7 << ADC_CTRLB_PRESCALER_OFFSET)
/* Window Monitor Control Register */
#define ADC_WINCTRL_WINMODE_OFFSET (0) /* Bit 2:0: Window monitor mode */
#define ADC_WINCTRL_WINMODE_MASK (7)
# define ADC_WINCTRL_WINMODE_DISABLE (0 << ADC_WINCTRL_WINMODE_OFFSET) /* No window mode */
# define ADC_WINCTRL_WINMODE_MODE1 (1 << ADC_WINCTRL_WINMODE_OFFSET) /* Mode 1: result > winlt */
# define ADC_WINCTRL_WINMODE_MODE2 (2 << ADC_WINCTRL_WINMODE_OFFSET) /* Mode 2: result < winut */
# define ADC_WINCTRL_WINMODE_MODE3 (3 << ADC_WINCTRL_WINMODE_OFFSET) /* Mode 3: winlt < result < winut */
# define ADC_WINCTRL_WINMODE_MODE4 (4 << ADC_WINCTRL_WINMODE_OFFSET) /* Mode 4: !(winlt < result < winut) */
/* Software Trigger Register */
#define ADC_SWTRIG_FLUSH (1 << 0) /* Bit 0: Adc conversion flush */
#define ADC_SWTRIG_START (1 << 1) /* Bit 1: Adc start conversion */
/* Input Control Register */
#define ADC_INPUTCTRL_MUXPOS_OFFSET (0) /* Bit 4:0: Positive mux input selection */
#define ADC_INPUTCTRL_MUXPOS_MASK (0x1F << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN0 (0 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN1 (1 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN2 (2 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN3 (3 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN4 (4 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN5 (5 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN6 (6 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN7 (7 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN8 (8 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN9 (9 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN10 (10 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN11 (11 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN12 (12 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN13 (13 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN14 (14 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN15 (15 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN16 (16 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN17 (17 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN18 (18 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_AIN19 (19 << ADC_INPUTCTRL_MUXPOS_OFFSET)
# define ADC_INPUTCTRL_MUXPOS_BANDGAP (0x19 << ADC_INPUTCTRL_MUXPOS_OFFSET) /* Bandgap voltage */
# define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (0x1A << ADC_INPUTCTRL_MUXPOS_OFFSET) /* 1/4 scaled core voltage */
# define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (0x1B << ADC_INPUTCTRL_MUXPOS_OFFSET) /* 1/4 scaled I/) supplly */
# define ADC_INPUTCTRL_MUXPOS_DAC (0x1C << ADC_INPUTCTRL_MUXPOS_OFFSET) /* DAC output */
#define ADC_INPUTCTRL_MUXNEG_OFFSET (8) /* Bit 12:8: Negative mux input selection */
#define ADC_INPUTCTRL_MUXNEG_MASK (0x1F << ADC_INPUTCTRL_MUXNEG_OFFSET)
# define ADC_INPUTCTRL_MUXNEG_AIN0 (0 << ADC_INPUTCTRL_MUXNEG_OFFSET)
# define ADC_INPUTCTRL_MUXNEG_AIN1 (1 << ADC_INPUTCTRL_MUXNEG_OFFSET)
# define ADC_INPUTCTRL_MUXNEG_AIN2 (2 << ADC_INPUTCTRL_MUXNEG_OFFSET)
# define ADC_INPUTCTRL_MUXNEG_AIN3 (3 << ADC_INPUTCTRL_MUXNEG_OFFSET)
# define ADC_INPUTCTRL_MUXNEG_AIN4 (4 << ADC_INPUTCTRL_MUXNEG_OFFSET)
# define ADC_INPUTCTRL_MUXNEG_AIN5 (5 << ADC_INPUTCTRL_MUXNEG_OFFSET)
# define ADC_INPUTCTRL_MUXNEG_AIN6 (6 << ADC_INPUTCTRL_MUXNEG_OFFSET)
# define ADC_INPUTCTRL_MUXNEG_AIN7 (7 << ADC_INPUTCTRL_MUXNEG_OFFSET)
# define ADC_INPUTCTRL_MUXNEG_GND (0x18 << ADC_INPUTCTRL_MUXNEG_OFFSET) /* Internal ground */
# define ADC_INPUTCTRL_MUXNEG_IOGND (0x19 << ADC_INPUTCTRL_MUXNEG_OFFSET) /* I/O ground */
#define ADC_INPUTCTRL_INPUTSCAN_OFFSET (16) /* Bit 19:16: Number of input channels included in scan */
#define ADC_INPUTCTRL_INPUTSCAN_MASK (0x0F << ADC_INPUTCTRL_INPUTSCAN_OFFSET)
#define ADC_INPUTCTRL_INPUTOFFSET_OFFSET (20) /* Bit 23:20: Positive mux setting offset */
#define ADC_INPUTCTRL_INPUTOFFSET_MASK (0x0F << ADC_INPUTCTRL_INPUTOFFSET_OFFSET)
#define ADC_INPUTCTRL_GAIN_OFFSET (24) /* Bit 27:24: Gain factor selection */
#define ADC_INPUTCTRL_GAIN_MASK (0x0F) << ADC_INPUTCTRL_GAIN_OFFSET
# define ADC_INPUTCTRL_GAIN_1X (0 << ADC_INPUTCTRL_GAIN_OFFSET)
# define ADC_INPUTCTRL_GAIN_2X (1 << ADC_INPUTCTRL_GAIN_OFFSET)
# define ADC_INPUTCTRL_GAIN_4X (2 << ADC_INPUTCTRL_GAIN_OFFSET)
# define ADC_INPUTCTRL_GAIN_8X (3 << ADC_INPUTCTRL_GAIN_OFFSET)
# define ADC_INPUTCTRL_GAIN_16X (4 << ADC_INPUTCTRL_GAIN_OFFSET)
# define ADC_INPUTCTRL_GAIN_DIV2 (15 << ADC_INPUTCTRL_GAIN_OFFSET)
/* Event Control Register */
#define ADC_EVCTRL_STARTEI (1 << 0) /* Bit 0: Start conversion event in */
#define ADC_EVCTRL_SYNCEI (1 << 1) /* Bit 1: Synchronization event in */
#define ADC_EVCTRL_RESRDYEO (1 << 4) /* Bit 4: Result ready event out */
#define ADC_EVCTRL_WINMONEO (1 << 5) /* Bit 5: Window monitor event out */
/* Common bit definitions for Interrupt Enable Clear Register,
* Interrupt Enable Set Register, and Interrupt Flag Status and Clear
* Register
*/
#define ADC_INT_RESRDY (1 << 0) /* Bit 0: Result ready */
#define ADC_INT_OVERRUN (1 << 1) /* Bit 1: Overrun */
#define ADC_INT_WINMON (1 << 2) /* Bit 2: Window monitor */
#define ADC_INT_SYNCRDY (1 << 3) /* Bit 3: Synchronization ready */
/* Status Register */
#define ADC_STATUS_SYNCBUSY (1 << 7) /* Bit 7: Synchronization buzy */
/* Calibration Register */
#define ADC_CALIB_LINEARITY_OFFSET (0) /* Bit 7:0: Linearity calibration value */
#define ADC_CALIB_LINEARITY_MASK (0xFF)
#define ADC_CALIB_BIAS_OFFSET (8) /* Bit 10:8: Bias calibration value */
#define ADC_CALIB_BIAS_MASK (7 << ADC_CALIB_BIAS_OFFSET)
/* Debug Control Register */
#define ADC_DBGCTRL_DBGRUN (1) /* Bit 0: Debug run */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_ADC_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_dac.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_DAC_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_DAC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_ARCH_FAMILY_SAMD21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* DAC register offsets *****************************************************/
#define SAM_DAC_CTRLA_OFFSET 0x0000 /* Control A Register */
#define SAM_DAC_CTRLB_OFFSET 0x0001 /* Control B Register */
#define SAM_DAC_EVCTRL_OFFSET 0x0002 /* Event Control Register */
#define SAM_DAC_INTENCLR_OFFSET 0x0004 /* Interrupt Enable Clear Register */
#define SAM_DAC_INTENSET_OFFSET 0x0005 /* Interrupt Enable Set Register */
#define SAM_DAC_INTFLAG_OFFSET 0x0006 /* Interrupt Flag Status and Clear Register */
#define SAM_DAC_STATUS_OFFSET 0x0007 /* Status Register */
#define SAM_DAC_DATA0_OFFSET 0x0008 /* Data DAC0 Register */
#define SAM_DAC_DATA1_OFFSET 0x0009 /* Data DAC1 Register */
#define SAM_DAC_DATABUF0_OFFSET 0x000C /* Data Buffer DAC0 Register */
#define SAM_DAC_DATABUF1_OFFSET 0x000D /* Data Buffer DAC1 Register */
/* DAC register addresses ***************************************************/
#define SAM_DAC_CTRLA (SAM_DAC_BASE+SAM_DAC_CTRLA_OFFSET)
#define SAM_DAC_CTRLB (SAM_DAC_BASE+SAM_DAC_CTRLB_OFFSET)
#define SAM_DAC_EVCTRL (SAM_DAC_BASE+SAM_DAC_EVCTRL_OFFSET)
#define SAM_DAC_INTENCLR (SAM_DAC_BASE+SAM_DAC_INTENCLR_OFFSET)
#define SAM_DAC_INTENSET (SAM_DAC_BASE+SAM_DAC_INTENSET_OFFSET)
#define SAM_DAC_INTFLAG (SAM_DAC_BASE+SAM_DAC_INTFLAG_OFFSET)
#define SAM_DAC_STATUS (SAM_DAC_BASE+SAM_DAC_STATUS_OFFSET)
#define SAM_DAC_DATA0 (SAM_DAC_BASE+SAM_DAC_DATA0_OFFSET)
#define SAM_DAC_DATA1 (SAM_DAC_BASE+SAM_DAC_DATA1_OFFSET)
#define SAM_DAC_DATABUF0 (SAM_DAC_BASE+SAM_DAC_DATABUF0_OFFSET)
#define SAM_DAC_DATABUF1 (SAM_DAC_BASE+SAM_DAC_DATABUF1_OFFSET)
/* DAC register bit definitions *********************************************/
/* Control A Register */
#define DAC_CTRLA_SWRTS (1 << 0) /* Bit 0: Software reset */
#define DAC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable DAC controller */
#define DAC_CTRLA_RUNSTDBY (1 << 2) /* Bit 1: Run in standby */
/* Control B Register */
#define DAC_CTRLB_EOEN (1 << 0) /* Bit 0: External Output Enable (to Vout) */
#define DAC_CTRLB_IOEN (1 << 1) /* Bit 1: Internal Output Enable (to analog comparator) */
#define DAC_CTRLB_LEFTADJ (1 << 2) /* Bit 2: Left-Adjusted Data */
#define DAC_CTRLB_VPD (1 << 3) /* Bit 3: Voltage Pump Disabled */
#define DAC_CTRLB_BDWP (1 << 4) /* Bit 4: Bypass DATABUF Write protection */
#define DAC_CTRLB_REFSEL_SHIFT (6) /* Bit 7:6: Reference selection */
#define DAC_CTRLB_REFSEL_MASK (3 << DAC_CTRLB_REFSEL_SHIFT)
# define DAC_CTRLB_REFSEL_INTREF (0 << DAC_CTRLB_REFSEL_SHIFT) /* Internal voltage reference */
# define DAC_CTRLB_REFSEL_VDDANA (1 << DAC_CTRLB_REFSEL_SHIFT) /* Analog voltage supply */
# define DAC_CTRLB_REFSEL_VREFA (2 << DAC_CTRLB_REFSEL_SHIFT) /* External voltage reference */
/* Event Control Register */
#define DAC_EVCTRL_STARTEI (1 << 0) /* Bit 0: Start conversion event input */
#define DAC_EVCTRL_EMPTYEO (1 << 1) /* Bit 1: Data buffer empty event output */
/* Common bit definitions for Interrupt Enable Clear Register,
* Interrupt Enable Set Register,
* and Interrupt Flag Status and Clear Register
*/
#define DAC_INT_UNDERRUN (1 << 0) /* Bit 0: Underrun interrupt */
#define DAC_INT_EMPTY (1 << 1) /* Bit 1: Data buffer empty interrupt */
#define DAC_INT_SYNCRDY (1 << 2) /* Bit 2: Sync ready */
#define DAC_INT_ALL 0x07
/* Status Register */
#define DAC_STATUS_SYNCBUSY (1 << 7) /* Bit 0: Sync busy */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_DAC_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_dmac.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_DMAC_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_DMAC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* DMAC register offsets ****************************************************/
#define SAM_DMAC_CTRL_OFFSET 0x0000 /* Control Register */
#define SAM_DMAC_CRCCTRL_OFFSET 0x0002 /* CRC Control Register */
#define SAM_DMAC_CRCDATAIN_OFFSET 0x0004 /* CRC Data Input Register */
#define SAM_DMAC_CRCCHKSUM_OFFSET 0x0008 /* CRC Checksum Register */
#define SAM_DMAC_CRCSTATUS_OFFSET 0x000c /* CRC Status Register */
#define SAM_DMAC_DBGCTRL_OFFSET 0x000d /* Debug Control Register */
#define SAM_DMAC_QOSCTRL_OFFSET 0x000e /* Quality of Service Control Register */
#define SAM_DMAC_SWTRIGCTRL_OFFSET 0x0010 /* Software Trigger Control Register */
#define SAM_DMAC_PRICTRL0_OFFSET 0x0014 /* Priority Control 0 Register */
#define SAM_DMAC_INTPEND_OFFSET 0x0020 /* Interrupt Pending Register */
#define SAM_DMAC_INTSTATUS_OFFSET 0x0024 /* Interrupt Status Register */
#define SAM_DMAC_BUSYCH_OFFSET 0x0028 /* Busy Channels Register */
#define SAM_DMAC_PENDCH_OFFSET 0x002c /* Pending Channels Register */
#define SAM_DMAC_ACTIVE_OFFSET 0x0030 /* Active Channels and Levels Register */
#define SAM_DMAC_BASEADDR_OFFSET 0x0034 /* Descriptor Memory Section Base Address Register */
#define SAM_DMAC_WRBADDR_OFFSET 0x0038 /* Write-Back Memory Section Base Address Register */
#define SAM_DMAC_CHID_OFFSET 0x003f /* Channel ID Register */
#define SAM_DMAC_CHCTRLA_OFFSET 0x0040 /* Channel Control A Register */
#define SAM_DMAC_CHCTRLB_OFFSET 0x0044 /* Channel Control B Register */
#define SAM_DMAC_CHINTENCLR_OFFSET 0x004c /* Channel Interrupt Enable Clear Register */
#define SAM_DMAC_CHINTENSET_OFFSET 0x004d /* Channel Interrupt Enable Set Register */
#define SAM_DMAC_CHINTFLAG_OFFSET 0x004e /* Channel Interrupt Flag Status and Clear Register */
#define SAM_DMAC_CHSTATUS_OFFSET 0x004f /* Channel Status Register */
/* LPSRAM Registers Relative to BASEADDR or WRBADDR */
#define SAM_LPSRAM_BTCTRL_OFFSET 0x0000 /* Block Transfer Control Register */
#define SAM_LPSRAM_BTCNT_OFFSET 0x0002 /* Block Transfer Count Register */
#define SAM_LPSRAM_SRCADDR_OFFSET 0x0004 /* Block Transfer Source Address Register */
#define SAM_LPSRAM_DSTADDR_OFFSET 0x0008 /* Block Transfer Destination Address Register */
#define SAM_LPSRAM_DESCADDR_OFFSET 0x000c /* Next Address Descriptor Register */
/* DMAC register addresses **************************************************/
#define SAM_DMAC_CTRL (SAM_DMAC_BASE+SAM_DMAC_CTRL_OFFSET)
#define SAM_DMAC_CRCCTRL (SAM_DMAC_BASE+SAM_DMAC_CRCCTRL_OFFSET)
#define SAM_DMAC_CRCDATAIN (SAM_DMAC_BASE+SAM_DMAC_CRCDATAIN_OFFSET)
#define SAM_DMAC_CRCCHKSUM (SAM_DMAC_BASE+SAM_DMAC_CRCCHKSUM_OFFSET)
#define SAM_DMAC_CRCSTATUS (SAM_DMAC_BASE+SAM_DMAC_CRCSTATUS_OFFSET)
#define SAM_DMAC_DBGCTRL (SAM_DMAC_BASE+SAM_DMAC_DBGCTRL_OFFSET)
#define SAM_DMAC_QOSCTRL (SAM_DMAC_BASE+SAM_DMAC_QOSCTRL_OFFSET)
#define SAM_DMAC_SWTRIGCTRL (SAM_DMAC_BASE+SAM_DMAC_SWTRIGCTRL_OFFSET)
#define SAM_DMAC_PRICTRL0 (SAM_DMAC_BASE+SAM_DMAC_PRICTRL0_OFFSET)
#define SAM_DMAC_INTPEND (SAM_DMAC_BASE+SAM_DMAC_INTPEND_OFFSET)
#define SAM_DMAC_INTSTATUS (SAM_DMAC_BASE+SAM_DMAC_INTSTATUS_OFFSET)
#define SAM_DMAC_BUSYCH (SAM_DMAC_BASE+SAM_DMAC_BUSYCH_OFFSET)
#define SAM_DMAC_PENDCH (SAM_DMAC_BASE+SAM_DMAC_PENDCH_OFFSET)
#define SAM_DMAC_ACTIVE (SAM_DMAC_BASE+SAM_DMAC_ACTIVE_OFFSET)
#define SAM_DMAC_BASEADDR (SAM_DMAC_BASE+SAM_DMAC_BASEADDR_OFFSET)
#define SAM_DMAC_WRBADDR (SAM_DMAC_BASE+SAM_DMAC_WRBADDR_OFFSET)
#define SAM_DMAC_CHID (SAM_DMAC_BASE+SAM_DMAC_CHID_OFFSET)
#define SAM_DMAC_CHCTRLA (SAM_DMAC_BASE+SAM_DMAC_CHCTRLA_OFFSET)
#define SAM_DMAC_CHCTRLB (SAM_DMAC_BASE+SAM_DMAC_CHCTRLB_OFFSET)
#define SAM_DMAC_CHINTENCLR (SAM_DMAC_BASE+SAM_DMAC_CHINTENCLR_OFFSET)
#define SAM_DMAC_CHINTENSET (SAM_DMAC_BASE+SAM_DMAC_CHINTENSET_OFFSET)
#define SAM_DMAC_CHINTFLAG (SAM_DMAC_BASE+SAM_DMAC_CHINTFLAG_OFFSET)
#define SAM_DMAC_CHSTATUS (SAM_DMAC_BASE+SAM_DMAC_CHSTATUS_OFFSET)
/* DMAC register bit definitions ********************************************/
/* Control Register */
#define DMAC_CTRL_SWRST (1 << 0) /* Bit 0: Software Reset */
#define DMAC_CTRL_DMAENABLE (1 << 1) /* Bit 1: DMA Enable */
#define DMAC_CTRL_CRCENABLE (1 << 2) /* Bit 2: CRC Enable */
#define DMAC_CTRL_LVLEN0 (1 << 8) /* Bit 8: Priority level 0 Enable */
#define DMAC_CTRL_LVLEN1 (1 << 9) /* Bit 9: Priority level 1 Enable */
#define DMAC_CTRL_LVLEN2 (1 << 10) /* Bit 10: Priority level 2 Enable */
#define DMAC_CTRL_LVLEN3 (1 << 11) /* Bit 10: Priority level 2 Enable */
/* CRC Control Register */
#define DMAC_CRCCTRL_CRCBEATSIZE_SHIFT (0) /* Bits 0-1: CRC beat size */
#define DMAC_CRCCTRL_CRCBEATSIZE_MASK (3 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT)
# define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (0 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 8-bit bus transfer */
# define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (1 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 16-bit bus transfer */
# define DMAC_CRCCTRL_CRCBEATSIZE_WORD (2 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 32-bit bus transfer */
#define DMAC_CRCCTRL_CRCPOLY_SHIFT (2) /* Bits 2-3: CRC polynomial type */
#define DMAC_CRCCTRL_CRCPOLY_MASK (3 < DMAC_CRCCTRL_CRCPOLY_SHIFT)
# define DMAC_CRCCTRL_CRCPOLY_CRC16 (0 < DMAC_CRCCTRL_CRCPOLY_SHIFT) /* CRC-16 (CRC-CCITT) */
# define DMAC_CRCCTRL_CRCPOLY_CRC32 (1 < DMAC_CRCCTRL_CRCPOLY_SHIFT) /* CRC32 (IEEE 802.3) */
#define DMAC_CRCCTRL_CRCSRC_SHIFT (8) /* Bits 8-13: CRC Input Source */
#define DMAC_CRCCTRL_CRCSRC_MASK (0x3f < DMAC_CRCCTRL_CRCSRC_SHIFT)
# define DMAC_CRCCTRL_CRCSRC_NOACTION (0 < DMAC_CRCCTRL_CRCSRC_SHIFT) /* No action */
# define DMAC_CRCCTRL_CRCSRC_IO (1 < DMAC_CRCCTRL_CRCSRC_SHIFT) /* I/O interface */
# define DMAC_CRCCTRL_CRCSRC_CHAN(n) (((uint32_t)(n) + 0x20) < DMAC_CRCCTRL_CRCSRC_SHIFT)
/* CRC Data Input Register (32-bit value) */
/* CRC Checksum Register (32-bit value) */
/* CRC Status Register */
#define DMAC_CRCSTATUS_CRCBUSY (1 << 0) /* Bit 0: CRC module busy */
#define DMAC_CRCSTATUS_CRCZERO (1 << 1) /* Bit 1: CRC zero */
/* Debug Control Register */
#define DMAC_DBGCTRL_DBGRUN (1 << 0) /* Bit 0: Debug run */
/* Quality of Service Control Register */
#define DMAC_QOSCTRL_WRBQOS_SHIFT (0) /* Bits 0-1: Write back quality of service */
#define DMAC_QOSCTRL_WRBQOS_MASK (3 << DMAC_QOSCTRL_WRBQOS_SHIFT)
# define DMAC_QOSCTRL_WRBQOS_DISABLE (0 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Background */
# define DMAC_QOSCTRL_WRBQOS_LOW (1 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Sensitive bandwidth */
# define DMAC_QOSCTRL_WRBQOS_MEDIUM (2 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Sensitive latency */
# define DMAC_QOSCTRL_WRBQOS_HIGH (3 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Critical latency */
#define DMAC_QOSCTRL_FQOS_SHIFT (2) /* Bits 2-3: Fetch quality of service */
#define DMAC_QOSCTRL_FQOS_MASK (3 << DMAC_QOSCTRL_FQOS_SHIFT)
# define DMAC_QOSCTRL_FQOS_DISABLE (0 << DMAC_QOSCTRL_FQOS_SHIFT) /* Background */
# define DMAC_QOSCTRL_FQOS_LOW (1 << DMAC_QOSCTRL_FQOS_SHIFT) /* Sensitive bandwidth */
# define DMAC_QOSCTRL_FQOS_MEDIUM (2 << DMAC_QOSCTRL_FQOS_SHIFT) /* Sensitive latency */
# define DMAC_QOSCTRL_FQOS_HIGH (3 << DMAC_QOSCTRL_FQOS_SHIFT) /* Critical latency */
#define DMAC_QOSCTRL_DQOS_SHIFT (4) /* Bits 4-5: Data transfer quality of service */
#define DMAC_QOSCTRL_DQOS_MASK (3 << DMAC_QOSCTRL_DQOS_SHIFT)
# define DMAC_QOSCTRL_DQOS_DISABLE (0 << DMAC_QOSCTRL_DQOS_SHIFT) /* Background */
# define DMAC_QOSCTRL_DQOS_LOW (1 << DMAC_QOSCTRL_DQOS_SHIFT) /* Sensitive bandwidth */
# define DMAC_QOSCTRL_DQOS_MEDIUM (2 << DMAC_QOSCTRL_DQOS_SHIFT) /* Sensitive latency */
# define DMAC_QOSCTRL_DQOS_HIGH (3 << DMAC_QOSCTRL_DQOS_SHIFT) /* Critical latency */
/* Common bit definitions for: Software Trigger Control Register,
* Interrupt Status Register, Busy Channels Register, and Pending Channels
* Register
*/
#define DMAC_CHAN(n) (1 << (n)) /* DMAC Channel n, n=0-11 */
/* Priority Control 0 Register */
#define DMAC_PRICTRL0_LVLPRI0_SHIFT (0) /* Bits 0-3: Level 0 channel priority number */
#define DMAC_PRICTRL0_LVLPRI0_MASK (15 << DMAC_PRICTRL0_LVLPRI0_SHIFT)
# define DMAC_PRICTRL0_LVLPRI0(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI0_SHIFT)
#define DMAC_PRICTRL0_RRLVLEN0 (1 << 7) /* Bit 7: Level 0 round-robin arbitrarion enable */
#define DMAC_PRICTRL0_LVLPRI1_SHIFT (8) /* Bits 8-11: Level 1 channel priority number */
#define DMAC_PRICTRL0_LVLPRI1_MASK (15 << DMAC_PRICTRL0_LVLPRI1_SHIFT)
# define DMAC_PRICTRL0_LVLPRI1(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI1_SHIFT)
#define DMAC_PRICTRL0_RRLVLEN1 (1 << 15) /* Bit 15: Level 1 round-robin arbitrarion enable */
#define DMAC_PRICTRL0_LVLPRI2_SHIFT (16) /* Bits 16-18: Level 2 channel priority number */
#define DMAC_PRICTRL0_LVLPRI2_MASK (7 << DMAC_PRICTRL0_LVLPRI2_SHIFT)
# define DMAC_PRICTRL0_LVLPRI2(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI2_SHIFT)
#define DMAC_PRICTRL0_RRLVLEN2 (1 << 23) /* Bit 23: Level 2 round-robin arbitrarion enable */
#define DMAC_PRICTRL0_LVLPRI3_SHIFT (24) /* Bits 24-27: Level 3 channel priority number */
#define DMAC_PRICTRL0_LVLPRI3_MASK (7 << DMAC_PRICTRL0_LVLPRI3_SHIFT)
# define DMAC_PRICTRL0_LVLPRI3(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI3_SHIFT)
#define DMAC_PRICTRL0_RRLVLEN3 (1 << 31) /* Bit 23: Level 3 round-robin arbitrarion enable */
/* Interrupt Pending Register */
#define DMAC_INTPEND_ID_SHIFT (0) /* Bit 0-3: Channel ID */
#define DMAC_INTPEND_ID_MASK (15 << DMAC_INTPEND_ID_SHIFT)
#define DMAC_INTPEND_TERR (1 << 8) /* Bit 8: Transfer error */
#define DMAC_INTPEND_TCMPL (1 << 9) /* Bit 9: Transfer complete */
#define DMAC_INTPEND_SUSP (1 << 10) /* Bit 10: Channel suspend */
#define DMAC_INTPEND_FERR (1 << 13) /* Bit 13: Fetch error */
#define DMAC_INTPEND_BUSY (1 << 14) /* Bit 14: Busy */
#define DMAC_INTPEND_PEND (1 << 15) /* Bit 15: Pending */
/* Interrupt Status Register */
/* Busy Channels Register */
/* Pending Channels Register */
/* Active Channels and Levels Register */
#define DMAC_ACTIVE_LVLEX0 (1 << 0) /* Bit 0: Level 0 channel trigger request executing */
#define DMAC_ACTIVE_LVLEX1 (1 << 1) /* Bit 1: Level 1 channel trigger request executing */
#define DMAC_ACTIVE_LVLEX2 (1 << 2) /* Bit 2: Level 2 channel trigger request executing */
#define DMAC_ACTIVE_LVLEX3 (1 << 3) /* Bit 3: Level 3 channel trigger request executing */
#define DMAC_ACTIVE_ID_SHIFT (8) /* Bits 8-11: Active channel ID */
#define DMAC_ACTIVE_ID_MASK (15 << DMAC_ACTIVE_ID_SHIFT)
#define DMAC_ACTIVE_ABUSY (1 << 15) /* Bit 15: Active channel busy */
#define DMAC_ACTIVE_BTCNT_SHIFT (16) /* Bit 16-31: Active channel block transfer count */
#define DMAC_ACTIVE_BTCNT_MASK (0xffff << DMAC_ACTIVE_BTCNT_SHIFT)
/* Descriptor Memory Section Base Address Register (32-bit address) */
/* Write-Back Memory Section Base Address Register (31-bit address) */
/* Channel ID Register */
#define DMAC_CHID_MASK 0x0f /* Bits 0-3: Channel ID */
/* Channel Control A Register */
#define DMAC_CHCTRLA_SWRST (1 << 0) /* Bit 0: Channel software reset */
#define DMAC_CHCTRLA_ENABLE (1 << 1) /* Bit 1: Channel enable */
/* Channel Control B Register */
#define DMAC_CHCTRLB_EVACT_SHIFT (0) /* Bits 0-2: Event input action */
#define DMAC_CHCTRLB_EVACT_MASK (7 << DMAC_CHCTRLB_EVACT_SHIFT)
# define DMAC_CHCTRLB_EVACT_NOACT (0 << DMAC_CHCTRLB_EVACT_SHIFT) /* No action */
# define DMAC_CHCTRLB_EVACT_TRIG (1 << DMAC_CHCTRLB_EVACT_SHIFT) /* Normal Transfer and Conditional Transfer on Strobe
* trigger */
# define DMAC_CHCTRLB_EVACT_CTRIG (2 << DMAC_CHCTRLB_EVACT_SHIFT) /* Conditional transfer trigger */
# define DMAC_CHCTRLB_EVACT_CBLOCK (3 << DMAC_CHCTRLB_EVACT_SHIFT) /* Conditional block transfer */
# define DMAC_CHCTRLB_EVACT_SUSPEND (4 << DMAC_CHCTRLB_EVACT_SHIFT) /* Channel suspend operation */
# define DMAC_CHCTRLB_EVACT_RESUME (5 << DMAC_CHCTRLB_EVACT_SHIFT) /* Channel resume operation */
# define DMAC_CHCTRLB_EVACT_SSKIP (6 << DMAC_CHCTRLB_EVACT_SHIFT) /* Skip next block suspend action */
#define DMAC_CHCTRLB_EVIE (1 << 3) /* Bit 3: Channel event input enable */
#define DMAC_CHCTRLB_EVOE (1 << 4) /* Bit 4: Channel event output enable */
#define DMAC_CHCTRLB_LVL_SHIFT (5) /* Bits 5-6: Channel arbitration level */
#define DMAC_CHCTRLB_LVL_MASK (3 << DMAC_CHCTRLB_LVL_SHIFT)
# define DMAC_CHCTRLB_LVL(n) ((uint32_t)(n) << DMAC_CHCTRLB_LVL_SHIFT)
# define DMAC_CHCTRLB_LVL_LVL0 (0 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 0 */
# define DMAC_CHCTRLB_LVL_LVL1 (1 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 1 */
# define DMAC_CHCTRLB_LVL_LVL2 (2 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 2 */
# define DMAC_CHCTRLB_LVL_LVL3 (3 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 3 */
#define DMAC_CHCTRLB_TRIGSRC_SHIFT (8) /* Bits 8-13: Trigger source */
#define DMAC_CHCTRLB_TRIGSRC_MASK (0x3f << DMAC_CHCTRLB_TRIGSRC_SHIFT)
# define DMAC_CHCTRLB_TRIGSRC(n) ((uint32_t)(n) << DMAC_CHCTRLB_TRIGSRC_SHIFT)
#define DMAC_CHCTRLB_TRIGACT_SHIFT (22) /* Bits 22-23: Trigger action */
#define DMAC_CHCTRLB_TRIGACT_MASK (3 << DMAC_CHCTRLB_TRIGACT_SHIFT)
# define DMAC_CHCTRLB_TRIGACT_BLOCK (0 << DMAC_CHCTRLB_TRIGACT_SHIFT) /* One trigger required for each action */
# define DMAC_CHCTRLB_TRIGACT_BEAT (2 << DMAC_CHCTRLB_TRIGACT_SHIFT) /* One trigger required for beat transfer */
# define DMAC_CHCTRLB_TRIGACT_TRANSACT (3 << DMAC_CHCTRLB_TRIGACT_SHIFT) /* One trigger required for each transaction */
#define DMAC_CHCTRLB_CMD_SHIFT (24) /* Bits 24-25: Software command */
#define DMAC_CHCTRLB_CMD_MASK (3 << DMAC_CHCTRLB_CMD_SHIFT)
# define DMAC_CHCTRLB_CMD_NOACTION (0 << DMAC_CHCTRLB_CMD_SHIFT) /* No action */
# define DMAC_CHCTRLB_CMD_SUSPEND (1 << DMAC_CHCTRLB_CMD_SHIFT) /* Channel suspend operation */
# define DMAC_CHCTRLB_CMD_RESUME (2 << DMAC_CHCTRLB_CMD_SHIFT) /* Channel resume operation */
/* Values for use with the DMAC_CHCTRLB_TRIGSRC(n) macro: */
#define DMAC_TRIGSRC_DISABLE (0) /* Only software/event triggers */
#define DMAC_TRIGSRC_SERCOM0_RX (1) /* SERCOM0 RX Trigger */
#define DMAC_TRIGSRC_SERCOM0_TX (2) /* SERCOM0 TX Trigger */
#define DMAC_TRIGSRC_SERCOM1_RX (3) /* SERCOM1 RX Trigger */
#define DMAC_TRIGSRC_SERCOM1_TX (4) /* SERCOM1 TX Trigger */
#define DMAC_TRIGSRC_SERCOM2_RX (5) /* SERCOM2 RX Trigger */
#define DMAC_TRIGSRC_SERCOM2_TX (6) /* SERCOM2 TX Trigger */
#define DMAC_TRIGSRC_SERCOM3_RX (7) /* SERCOM3 RX Trigger */
#define DMAC_TRIGSRC_SERCOM3_TX (8) /* SERCOM3 TX Trigger */
#define DMAC_TRIGSRC_SERCOM4_RX (9) /* SERCOM4 RX Trigger */
#define DMAC_TRIGSRC_SERCOM4_TX (10) /* SERCOM4 TX Trigger */
#define DMAC_TRIGSRC_SERCOM5_RX (11) /* SERCOM4 RX Trigger */
#define DMAC_TRIGSRC_SERCOM5_TX (12) /* SERCOM4 TX Trigger */
#define DMAC_TRIGSRC_TCC0_OVF (13) /* TCC0 Overflow Trigger */
#define DMAC_TRIGSRC_TCC0_MC0 (14) /* TCC0 Match/Compare 0 Trigger */
#define DMAC_TRIGSRC_TCC0_MC1 (15) /* TCC0 Match/Compare 1 Trigger */
#define DMAC_TRIGSRC_TCC0_MC2 (16) /* TCC0 Match/Compare 2 Trigger */
#define DMAC_TRIGSRC_TCC0_MC3 (17) /* TCC0 Match/Compare 3 Trigger */
#define DMAC_TRIGSRC_TCC1_OVF (18) /* TCC1 Overflow Trigger */
#define DMAC_TRIGSRC_TCC1_MC0 (19) /* TCC1 Match/Compare 0 Trigger */
#define DMAC_TRIGSRC_TCC1_MC1 (20) /* TCC1 Match/Compare 1 Trigger */
#define DMAC_TRIGSRC_TCC2_OVF (21) /* TCC2 Overflow Trigger */
#define DMAC_TRIGSRC_TCC2_MC0 (22) /* TCC2 Match/Compare 0 Trigger */
#define DMAC_TRIGSRC_TCC2_MC1 (23) /* TCC2 Match/Compare 1 Trigger */
#define DMAC_TRIGSRC_TC0_OVF (24) /* TC0 Overflow Trigger */
#define DMAC_TRIGSRC_TC0_MC0 (25) /* TC0 Match/Compare 0 Trigger */
#define DMAC_TRIGSRC_TC0 MC1 (26) /* TC0 Match/Compare 1 Trigger */
#define DMAC_TRIGSRC_TC1_OVF (27) /* TC1 Overflow Trigger */
#define DMAC_TRIGSRC_TC1_MC0 (28) /* TC1 Match/Compare 0 Trigger */
#define DMAC_TRIGSRC_TC1_MC1 (29) /* TC1 Match/Compare 1 Trigger */
#define DMAC_TRIGSRC_TC2_OVF (30) /* TC2 Overflow Trigger */
#define DMAC_TRIGSRC_TC2_MC0 (31) /* TC2 Match/Compare 0 Trigger */
#define DMAC_TRIGSRC_TC2_MC1 (32) /* TC2 Match/Compare 1 Trigger */
#define DMAC_TRIGSRC_TC3_OVF (33) /* TC3 Overflow Trigger */
#define DMAC_TRIGSRC_TC3_MC0 (34) /* TC3 Match/Compare 0 Trigger */
#define DMAC_TRIGSRC_TC3_MC1 (35) /* TC3 Match/Compare 1 Trigger */
#define DMAC_TRIGSRC_TC4_OVF (36) /* TC4 Overflow Trigger */
#define DMAC_TRIGSRC_TC4_MC0 (37) /* TC4 Match/Compare 0 Trigger */
#define DMAC_TRIGSRC_TC4_MC1 (38) /* TC4 Match/Compare 1 Trigger */
#define DMAC_TRIGSRC_ADC_RESRDY (39) /* ADC Result Ready Trigger */
#define DMAC_TRIGSRC_DAC_EMPTY (40) /* DAC0 Empty Trigger */
#define DMAC_TRIGSRC_I2S0_RX (41) /* I2S0 RX Trigger */
#define DMAC_TRIGSRC_I2S1_RX (42) /* I2S1 RX Trigger */
#define DMAC_TRIGSRC_I2S0_TX (43) /* I2S0 TX Trigger */
#define DMAC_TRIGSRC_I2S1_TX (44) /* I2S1 TX Trigger */
/* Common register bit definitions: Channel Interrupt Enable Clear Register,
* Channel Interrupt Enable Set Register, and Channel Interrupt Flag Status
* and Clear Register
*/
#define DMAC_INT_TERR (1 << 0) /* Bit 0: Transfer error interrupt */
#define DMAC_INT_TCMPL (1 << 1) /* Bit 1: Channel transfer complete interrupt */
#define DMAC_INT_SUSP (1 << 2) /* Bit 2: Channel suspend interrupt */
#define DMAC_INT_ALL (0x07)
/* Channel Status Register */
#define DMAC_CHSTATUS_PEND (1 << 0) /* Bit 0: Channel pending */
#define DMAC_CHSTATUS_BUSY (1 << 1) /* Bit 1: Channel busy */
#define DMAC_CHSTATUS_FERR (1 << 2) /* Bit 2: Channel fetch error */
/* Block Transfer Control Register */
#define LPSRAM_BTCTRL_VALID (1 << 0) /* Bit 0: Descriptor valid */
#define LPSRAM_BTCTRL_EVOSEL_SHIFT (1) /* Bits 1-2: Event output selection */
#define LPSRAM_BTCTRL_EVOSEL_MASK (3 << LPSRAM_BTCTRL_EVOSEL_SHIFT)
# define LPSRAM_BTCTRL_EVOSEL_DISABLE (0 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event generation disabled */
# define LPSRAM_BTCTRL_EVOSEL_BLOCK (1 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event strobe when block transfer complete */
# define LPSRAM_BTCTRL_EVOSEL_BEAT (3 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event strobe when beat transfer complete */
#define LPSRAM_BTCTRL_BLOCKACT_SHIFT (3) /* Bits 3-4: Block action */
#define LPSRAM_BTCTRL_BLOCKACT_MASK (3 << LPSRAM_BTCTRL_BLOCKACT_SHIFT)
# define LPSRAM_BTCTRL_BLOCKACT_NOACT (0 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel disabled if last block transfer */
# define LPSRAM_BTCTRL_BLOCKACT_INT (1 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel disabled if last block transfer + block int */
# define LPSRAM_BTCTRL_BLOCKACT_SUSPEND (2 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel suspend operation is completed */
# define LPSRAM_BTCTRL_BLOCKACT_BOTH (3 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Both channel suspend operation + block int */
#define LPSRAM_BTCTRL_BEATSIZE_SHIFT (8) /* Bits 8-9: Beat size */
#define LPSRAM_BTCTRL_BEATSIZE_MASK (3 << LPSRAM_BTCTRL_BEATSIZE_SHIFT)
# define LPSRAM_BTCTRL_BEATSIZE_BYTE (0 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 8-bit bus transfer */
# define LPSRAM_BTCTRL_BEATSIZE_HWORD (1 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 16-bit bus transfer */
# define LPSRAM_BTCTRL_BEATSIZE_WORD (2 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 32-bit bus transfer */
#define LPSRAM_BTCTRL_SRCINC (1 << 10) /* Bit 10: Source address increment enable */
#define LPSRAM_BTCTRL_DSTINC (1 << 11) /* Bit 11: Destination address increment enable */
#define LPSRAM_BTCTRL_STEPSEL (1 << 12) /* Bit 12: Step selection */
#define LPSRAM_BTCTRL_STEPSIZE_SHIFT (13) /* Bits 13-15: Address increment step */
#define LPSRAM_BTCTRL_STEPSIZE_MASK (7 << LPSRAM_BTCTRL_STEPSIZE_SHIFT)
# define LPSRAM_BTCTRL_STEPSIZE_X1 (0 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 1 */
# define LPSRAM_BTCTRL_STEPSIZE_X2 (1 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 2 */
# define LPSRAM_BTCTRL_STEPSIZE_X4 (2 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 4 */
# define LPSRAM_BTCTRL_STEPSIZE_X8 (3 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 8 */
# define LPSRAM_BTCTRL_STEPSIZE_X16 (4 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 16 */
# define LPSRAM_BTCTRL_STEPSIZE_X32 (5 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 32 */
# define LPSRAM_BTCTRL_STEPSIZE_X64 (6 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 64 */
# define LPSRAM_BTCTRL_STEPSIZE_X128 (7 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 128 */
/* Block Transfer Count Register (16-bit count) */
/* Block Transfer Source Address Register (32-bit address) */
/* Block Transfer Destination Address Register (32-bit address) */
/* Next Address Descriptor Register (32-bit address) */
/****************************************************************************
* Public Types
****************************************************************************/
/* DMA descriptor */
struct dma_desc_s
{
uint16_t btctrl; /* Block Transfer Control Register */
uint16_t btcnt; /* Block Transfer Count Register */
uint32_t srcaddr; /* Block Transfer Source Address Register */
uint32_t dstaddr; /* Block Transfer Destination Address Register */
uint32_t descaddr; /* Next Address Descriptor Register */
};
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_DMAC_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_eic.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Microchip SAMD21 datasheet"
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EIC_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EIC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_ARCH_FAMILY_SAMD21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* EIC register offsets *****************************************************/
#define SAM_EIC_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_EIC_STATUS_OFFSET 0x0001 /* Status register */
#define SAM_EIC_NMICTRL_OFFSET 0x0002 /* Non-maskable interrupt control register */
#define SAM_EIC_NMIFLAG_OFFSET 0x0003 /* Non-maskable interrupt flag register */
#define SAM_EIC_EVCTRL_OFFSET 0x0004 /* Event control register */
#define SAM_EIC_INTENCLR_OFFSET 0x0008 /* Interrupt enable clear register */
#define SAM_EIC_INTENSET_OFFSET 0x000c /* Interrupt enable set register */
#define SAM_EIC_INTFLAG_OFFSET 0x0010 /* Interrupt flag and status clear register */
#define SAM_EIC_WAKEUP_OFFSET 0x0014 /* Wakeup register */
#define SAM_EIC_CONFIG0_OFFSET 0x0018 /* Configuration 0 register */
#define SAM_EIC_CONFIG1_OFFSET 0x001c /* Configuration 1 register */
#define SAM_EIC_CONFIG2_OFFSET 0x0020 /* Configuration 2 register */
/* EIC register addresses ***************************************************/
#define SAM_EIC_CTRLA (SAM_EIC_BASE+SAM_EIC_CTRLA_OFFSET)
#define SAM_EIC_STATUS (SAM_EIC_BASE+SAM_EIC_STATUS_OFFSET)
#define SAM_EIC_NMICTRL (SAM_EIC_BASE+SAM_EIC_NMICTRL_OFFSET)
#define SAM_EIC_NMIFLAG (SAM_EIC_BASE+SAM_EIC_NMIFLAG_OFFSET)
#define SAM_EIC_EVCTRL (SAM_EIC_BASE+SAM_EIC_EVCTRL_OFFSET)
#define SAM_EIC_INTENCLR (SAM_EIC_BASE+SAM_EIC_INTENCLR_OFFSET)
#define SAM_EIC_INTENSET (SAM_EIC_BASE+SAM_EIC_INTENSET_OFFSET)
#define SAM_EIC_INTFLAG (SAM_EIC_BASE+SAM_EIC_INTFLAG_OFFSET)
#define SAM_EIC_WAKEUP (SAM_EIC_BASE+SAM_EIC_WAKEUP_OFFSET)
#define SAM_EIC_CONFIG0 (SAM_EIC_BASE+SAM_EIC_CONFIG0_OFFSET)
#define SAM_EIC_CONFIG1 (SAM_EIC_BASE+SAM_EIC_CONFIG1_OFFSET)
#define SAM_EIC_CONFIG2 (SAM_EIC_BASE+SAM_EIC_CONFIG2_OFFSET)
/* EIC register bit definitions *********************************************/
/* Control A register */
#define EIC_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
#define EIC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
/* Status register */
#define EIC_STATUS_SYNCBUSY (1 << 7) /* Bit 7: Synchronization busy */
/* Non-maskable interrupt control register */
#define EIC_NMICTRL_NMISENSE_SHIFT (0) /* Bits 0-2: Non-maskable interrupt sense */
#define EIC_NMICTRL_NMISENSE_MASK (7 << EIC_NVMICTRL_NMISENSE_SHIFT)
# define EIC_NMICTRL_NMISENSE_NONE (0 << EIC_NVMICTRL_NMISENSE_SHIFT) /* No detection */
# define EIC_NMICTRL_NMISENSE_RISE (1 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Rising edge detection */
# define EIC_NMICTRL_NMISENSE_FALL (2 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Falling edge detection */
# define EIC_NMICTRL_NMISENSE_BOTH (3 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Both edge detection */
# define EIC_NMICTRL_NMISENSE_HIGH (4 << EIC_NVMICTRL_NMISENSE_SHIFT) /* High level detection */
# define EIC_NMICTRL_NMISENSE_LOW (5 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Low level detection */
#define EIC_NMICTRL_NMIFLTEN (1 << 3) /* Bit 3: Non-maskable interrupt filter enable */
/* Non-maskable interrupt flas status and clear register */
#define EIC_NMIFLAG_NMI (1 << 0) /* Non-maskable interrupt */
/* Event control, Interrupt enable clear, interrupt enable set register,
* interrupt flag status and clear, and external interrupt wakeup
* registers.
*/
#define EIC_EXTINT_SHIFT (0) /* Bits 0-15: External interrupt n */
#define EIC_EXTINT_MASK (0x3ffff << EIC_EXTINT_SHIFT)
# define EIC_EXTINT(n) (1 << (n))
# define EIC_EXTINT_0 (1 << 0) /* Bit 0: External interrupt 0 */
# define EIC_EXTINT_1 (1 << 1) /* Bit 1: External interrupt 1 */
# define EIC_EXTINT_2 (1 << 2) /* Bit 2: External interrupt 2 */
# define EIC_EXTINT_3 (1 << 3) /* Bit 3: External interrupt 3 */
# define EIC_EXTINT_4 (1 << 4) /* Bit 4: External interrupt 4 */
# define EIC_EXTINT_5 (1 << 5) /* Bit 5: External interrupt 5 */
# define EIC_EXTINT_6 (1 << 6) /* Bit 6: External interrupt 6 */
# define EIC_EXTINT_7 (1 << 7) /* Bit 7: External interrupt 7 */
# define EIC_EXTINT_8 (1 << 8) /* Bit 8: External interrupt 8 */
# define EIC_EXTINT_9 (1 << 9) /* Bit 9: External interrupt 9 */
# define EIC_EXTINT_10 (1 << 10) /* Bit 10: External interrupt 10 */
# define EIC_EXTINT_11 (1 << 11) /* Bit 11: External interrupt 11 */
# define EIC_EXTINT_12 (1 << 12) /* Bit 12: External interrupt 12 */
# define EIC_EXTINT_13 (1 << 13) /* Bit 13: External interrupt 13 */
# define EIC_EXTINT_14 (1 << 14) /* Bit 14: External interrupt 14 */
# define EIC_EXTINT_15 (1 << 15) /* Bit 15: External interrupt 15 */
# define EIC_EXTINT_16 (1 << 16) /* Bit 16: External interrupt 16 */
# define EIC_EXTINT_17 (1 << 17) /* Bit 17: External interrupt 17 */
#define EIC_EXTINT_ALL EIC_EXTINT_MASK
/* Configuration 0 register */
#define EIC_CONFIG0_FILTEN(n) (0x8 << ((n) << 2)) /* Filter n enable, n=0-7 */
#define EIC_CONFIG0_SENSE_SHIFT(n) ((n) << 2) /* Filter n input sense, n=0-7 */
#define EIC_CONFIG0_SENSE_MASK(n) (7 << EIC_CONFIG0_SENSE_SHIFT(n))
# define EIC_CONFIG0_SENSE_NONE(n) (0 << EIC_CONFIG0_SENSE_SHIFT(n)) /* No detection */
# define EIC_CONFIG0_SENSE_RISE(n) (1 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Rising edge detection */
# define EIC_CONFIG0_SENSE_FALL(n) (2 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Falling edge detection */
# define EIC_CONFIG0_SENSE_BOTH(n) (3 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Both edge detection */
# define EIC_CONFIG0_SENSE_HIGH(n) (4 << EIC_CONFIG0_SENSE_SHIFT(n)) /* High level detection */
# define EIC_CONFIG0_SENSE_LOW(n) (5 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Low level detection */
/* Configuration 1 register */
#define EIC_CONFIG1_FILTEN(n) (0x8 << (((n) - 8) << 2)) /* Filter n enable, n=8-15 */
#define EIC_CONFIG1_SENSE_SHIFT(n) (((n) - 8) << 2) /* Filter n input sense, n=8-17 */
#define EIC_CONFIG1_SENSE_MASK(n) (7 << EIC_CONFIG1_SENSE_SHIFT(n))
# define EIC_CONFIG1_SENSE_NONE(n) (0 << EIC_CONFIG1_SENSE_SHIFT(n)) /* No detection */
# define EIC_CONFIG1_SENSE_RISE(n) (1 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Rising edge detection */
# define EIC_CONFIG1_SENSE_FALL(n) (2 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Falling edge detection */
# define EIC_CONFIG1_SENSE_BOTH(n) (3 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Both edge detection */
# define EIC_CONFIG1_SENSE_HIGH(n) (4 << EIC_CONFIG1_SENSE_SHIFT(n)) /* High level detection */
# define EIC_CONFIG1_SENSE_LOW(n) (5 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Low level detection */
/* Configuration 2 register */
#define EIC_CONFIG2_FILTEN(n) (0x8 << (((n) - 16) << 2)) /* Filter n enable, n=16-23 */
#define EIC_CONFIG2_SENSE_SHIFT(n) (((n) - 16) << 2) /* Filter n input sense, n=16-23 */
#define EIC_CONFIG2_SENSE_MASK(n) (7 << EIC_CONFIG2_SENSE_SHIFT(n))
# define EIC_CONFIG2_SENSE_NONE(n) (0 << EIC_CONFIG2_SENSE_SHIFT(n)) /* No detection */
# define EIC_CONFIG2_SENSE_RISE(n) (1 << EIC_CONFIG2_SENSE_SHIFT(n)) /* Rising edge detection */
# define EIC_CONFIG2_SENSE_FALL(n) (2 << EIC_CONFIG2_SENSE_SHIFT(n)) /* Falling edge detection */
# define EIC_CONFIG2_SENSE_BOTH(n) (3 << EIC_CONFIG2_SENSE_SHIFT(n)) /* Both edge detection */
# define EIC_CONFIG2_SENSE_HIGH(n) (4 << EIC_CONFIG2_SENSE_SHIFT(n)) /* High level detection */
# define EIC_CONFIG2_SENSE_LOW(n) (5 << EIC_CONFIG2_SENSE_SHIFT(n)) /* Low level detection */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EIC_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_evsys.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EVSYS_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EVSYS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* EVSYS register offsets ***************************************************/
#define SAM_EVSYS_CTRL_OFFSET 0x0000 /* Control register */
#define SAM_EVSYS_CHANNEL_OFFSET 0x0004 /* Channel register */
#define SAM_EVSYS_USER_OFFSET 0x0008 /* User multiplexer register */
#define SAM_EVSYS_CHSTATUS_OFFSET 0x000c /* Channel status register */
#define SAM_EVSYS_INTENCLR_OFFSET 0x0010 /* Interrupt enable clear register */
#define SAM_EVSYS_INTENSET_OFFSET 0x0014 /* Interrupt enable set register */
#define SAM_EVSYS_INTFLAG_OFFSET 0x0018 /* Interrupt flag status and clear register */
/* EVSYS register addresses *************************************************/
#define SAM_EVSYS_CTRL (SAM_EVSYS_BASE+SAM_EVSYS_CTRL_OFFSET)
#define SAM_EVSYS_CHANNEL (SAM_EVSYS_BASE+SAM_EVSYS_CHANNEL_OFFSET)
#define SAM_EVSYS_USER (SAM_EVSYS_BASE+SAM_EVSYS_USER_OFFSET)
#define SAM_EVSYS_CHSTATUS (SAM_EVSYS_BASE+SAM_EVSYS_CHSTATUS_OFFSET)
#define SAM_EVSYS_INTENCLR (SAM_EVSYS_BASE+SAM_EVSYS_INTENCLR_OFFSET)
#define SAM_EVSYS_INTENSET (SAM_EVSYS_BASE+SAM_EVSYS_INTENSET_OFFSET)
#define SAM_EVSYS_INTFLAG (SAM_EVSYS_BASE+SAM_EVSYS_INTFLAG_OFFSET)
/* EVSYS register bit definitions *******************************************/
/* Control register */
#define EVSYS_CTRL_SWRST (1 << 0) /* Bit 0: Software Reset */
#define EVSYS_CTRL_GCLKREQ (1 << 4) /* Bit 4: Generic Clock Requests */
/* Channel register */
#define EVSYS_CHANNEL_SHIFT (0) /* Bits 0-3: Channel Selection */
#define EVSYS_CHANNEL_MASK (0xff << EVSYS_CHANNEL_SHIFT)
# define EVSYS_CHANNEL(n) ((uint32_t)(n) << EVSYS_CHANNEL_SHIFT)
#define EVSYS_CHANNEL_SWEVT (1 << 8) /* Bit 8: Software Event */
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define EVSYS_CHANNEL_EVGEN_SHIFT (16) /* Bits 16-23: Event Generator */
# define EVSYS_CHANNEL_EVGEN_MASK (0xff << EVSYS_CHANNEL_EVGEN_SHIFT)
# define EVSYS_CHANNEL_EVGEN_NONE (0 << EVSYS_CHANNEL_EVGEN_SHIFT) /* No event generator selected */
# define EVSYS_CHANNEL_EVGEN_RTCCMP0 (1 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Compare 0 or Alarm 0 */
# define EVSYS_CHANNEL_EVGEN_RTCCMP1 (2 << EVSYS_CHANNEL_EVGEN_SHIFT) /* Compare 1 */
# define EVSYS_CHANNEL_EVGEN_RTCOVF (3 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Overflow */
# define EVSYS_CHANNEL_EVGEN_RTCPER0 (4 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Period 0 */
# define EVSYS_CHANNEL_EVGEN_RTCPER1 (5 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Period 1 */
# define EVSYS_CHANNEL_EVGEN_RTCPER2 (6 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Period 2 */
# define EVSYS_CHANNEL_EVGEN_RTCPER3 (7 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Period 3 */
# define EVSYS_CHANNEL_EVGEN_RTCPER4 (8 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Period 4 */
# define EVSYS_CHANNEL_EVGEN_RTCPER5 (9 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Period 5 */
# define EVSYS_CHANNEL_EVGEN_RTCPER6 (10 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Period 6 */
# define EVSYS_CHANNEL_EVGEN_RTCPER7 (11 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Period 7 */
# define EVSYS_CHANNEL_EVGEN_EXTINT0 (12 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 0 */
# define EVSYS_CHANNEL_EVGEN_EXTINT1 (13 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 1 */
# define EVSYS_CHANNEL_EVGEN_EXTINT2 (14 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 2 */
# define EVSYS_CHANNEL_EVGEN_EXTINT3 (15 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 3 */
# define EVSYS_CHANNEL_EVGEN_EXTINT4 (16 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 4 */
# define EVSYS_CHANNEL_EVGEN_EXTINT5 (17 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 5 */
# define EVSYS_CHANNEL_EVGEN_EXTINT6 (18 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 6 */
# define EVSYS_CHANNEL_EVGEN_EXTINT7 (19 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 7 */
# define EVSYS_CHANNEL_EVGEN_EXTINT8 (20 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 8 */
# define EVSYS_CHANNEL_EVGEN_EXTINT9 (21 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 9 */
# define EVSYS_CHANNEL_EVGEN_EXTINT10 (22 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 10 */
# define EVSYS_CHANNEL_EVGEN_EXTINT11 (23 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 11 */
# define EVSYS_CHANNEL_EVGEN_EXTINT12 (24 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 12 */
# define EVSYS_CHANNEL_EVGEN_EXTINT13 (25 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 13 */
# define EVSYS_CHANNEL_EVGEN_EXTINT14 (26 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 14 */
# define EVSYS_CHANNEL_EVGEN_EXTINT15 (27 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 15 */
# define EVSYS_CHANNEL_EVGEN_TC0OVF (28 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC0 Overflow/Underflow */
# define EVSYS_CHANNEL_EVGEN_TC0MC0 (29 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC0 Match/Capture 0 */
# define EVSYS_CHANNEL_EVGEN_TC0MC1 (30 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC0 Match/Capture 1 */
# define EVSYS_CHANNEL_EVGEN_TC1OVF (31 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC1 Overflow/Underflow */
# define EVSYS_CHANNEL_EVGEN_TC1MC0 (32 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC1 Match/Capture 0 */
# define EVSYS_CHANNEL_EVGEN_TC1MC1 (33 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC1 Match/Capture 1 */
# define EVSYS_CHANNEL_EVGEN_TC2OVF (34 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC2 Overflow/Underflow */
# define EVSYS_CHANNEL_EVGEN_TC2MC0 (35 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC2 Match/Capture 0 */
# define EVSYS_CHANNEL_EVGEN_TC2MC1 (36 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC2 Match/Capture 1 */
# define EVSYS_CHANNEL_EVGEN_TC3OVF (37 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC3 Overflow/Underflow */
# define EVSYS_CHANNEL_EVGEN_TC3MC0 (38 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC3 Match/Capture 0 */
# define EVSYS_CHANNEL_EVGEN_TC3MC1 (39 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC3 Match/Capture 1 */
# define EVSYS_CHANNEL_EVGEN_TC4OVF (40 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC4 Overflow/Underflow */
# define EVSYS_CHANNEL_EVGEN_TC4MC0 (41 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC4 Match/Capture 0 */
# define EVSYS_CHANNEL_EVGEN_TC4MC1 (42 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC4 Match/Capture 1 */
# define EVSYS_CHANNEL_EVGEN_TC5OVF (43 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC5 Overflow/Underflow */
# define EVSYS_CHANNEL_EVGEN_TC5MC0 (44 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC5 Match/Capture 0 */
# define EVSYS_CHANNEL_EVGEN_TC5MC1 (45 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC5 Match/Capture 1 */
# define EVSYS_CHANNEL_EVGEN_TC6OVF (46 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC6 Overflow/Underflow */
# define EVSYS_CHANNEL_EVGEN_TC6MC0 (47 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC6 Match/Capture 0 */
# define EVSYS_CHANNEL_EVGEN_TC6MC1 (48 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC6 Match/Capture 1 */
# define EVSYS_CHANNEL_EVGEN_TC7OVF (49 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC7 Overflow/Underflow */
# define EVSYS_CHANNEL_EVGEN_TC7MC0 (50 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC7 Match/Capture 0 */
# define EVSYS_CHANNEL_EVGEN_TC7MC1 (51 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC7 Match/Capture 1 */
# define EVSYS_CHANNEL_EVGEN_ADCRESRDY (52 << EVSYS_CHANNEL_EVGEN_SHIFT) /* ADC Result Ready */
# define EVSYS_CHANNEL_EVGEN_ADCWINMON (53 << EVSYS_CHANNEL_EVGEN_SHIFT) /* ADC Window Monitor */
# define EVSYS_CHANNEL_EVGEN_ACCOMP0 (54 << EVSYS_CHANNEL_EVGEN_SHIFT) /* AC Comparator 0 */
# define EVSYS_CHANNEL_EVGEN_ACCOMP1 (55 << EVSYS_CHANNEL_EVGEN_SHIFT) /* AC Comparator 1 */
# define EVSYS_CHANNEL_EVGEN_ACWIN (56 << EVSYS_CHANNEL_EVGEN_SHIFT) /* AC Window 0 */
# define EVSYS_CHANNEL_EVGEN_DACEMPTY (57 << EVSYS_CHANNEL_EVGEN_SHIFT) /* DAC Data Buffer Empty */
# define EVSYS_CHANNEL_EVGEN_PTCEOC (58 << EVSYS_CHANNEL_EVGEN_SHIFT) /* PTC End of Conversion */
# define EVSYS_CHANNEL_EVGEN_PTCWCOMP (59 << EVSYS_CHANNEL_EVGEN_SHIFT) /* PTC Window Comparator */
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define EVSYS_CHANNEL_EVGEN_SHIFT (16) /* Bits 16-22: Event Generator */
# define EVSYS_CHANNEL_EVGEN_MASK (0x7f << EVSYS_CHANNEL_EVGEN_SHIFT)
# define EVSYS_CHANNEL_EVGEN_NONE (0 << EVSYS_CHANNEL_EVGEN_SHIFT) /* No event generator selected */
# define EVSYS_CHANNEL_EVGEN_RTCCMP0 (1 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Compare 0 or Alarm 0 */
# define EVSYS_CHANNEL_EVGEN_RTCCMP1 (2 << EVSYS_CHANNEL_EVGEN_SHIFT) /* Compare 1 */
# define EVSYS_CHANNEL_EVGEN_RTCOVF (3 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Overflow */
# define EVSYS_CHANNEL_EVGEN_RTCPER0 (4 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Period 0 */
# define EVSYS_CHANNEL_EVGEN_RTCPER1 (5 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Period 1 */
# define EVSYS_CHANNEL_EVGEN_RTCPER2 (6 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Period 2 */
# define EVSYS_CHANNEL_EVGEN_RTCPER3 (7 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Period 3 */
# define EVSYS_CHANNEL_EVGEN_RTCPER4 (8 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Period 4 */
# define EVSYS_CHANNEL_EVGEN_RTCPER5 (9 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Period 5 */
# define EVSYS_CHANNEL_EVGEN_RTCPER6 (10 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Period 6 */
# define EVSYS_CHANNEL_EVGEN_RTCPER7 (11 << EVSYS_CHANNEL_EVGEN_SHIFT) /* RTC Period 7 */
# define EVSYS_CHANNEL_EVGEN_EXTINT0 (12 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 0 */
# define EVSYS_CHANNEL_EVGEN_EXTINT1 (13 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 1 */
# define EVSYS_CHANNEL_EVGEN_EXTINT2 (14 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 2 */
# define EVSYS_CHANNEL_EVGEN_EXTINT3 (15 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 3 */
# define EVSYS_CHANNEL_EVGEN_EXTINT4 (16 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 4 */
# define EVSYS_CHANNEL_EVGEN_EXTINT5 (17 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 5 */
# define EVSYS_CHANNEL_EVGEN_EXTINT6 (18 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 6 */
# define EVSYS_CHANNEL_EVGEN_EXTINT7 (19 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 7 */
# define EVSYS_CHANNEL_EVGEN_EXTINT8 (20 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 8 */
# define EVSYS_CHANNEL_EVGEN_EXTINT9 (21 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 9 */
# define EVSYS_CHANNEL_EVGEN_EXTINT10 (22 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 10 */
# define EVSYS_CHANNEL_EVGEN_EXTINT11 (23 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 11 */
# define EVSYS_CHANNEL_EVGEN_EXTINT12 (24 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 12 */
# define EVSYS_CHANNEL_EVGEN_EXTINT13 (25 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 13 */
# define EVSYS_CHANNEL_EVGEN_EXTINT14 (26 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 14 */
# define EVSYS_CHANNEL_EVGEN_EXTINT15 (27 << EVSYS_CHANNEL_EVGEN_SHIFT) /* EIC External Interrupt 15 */
# define EVSYS_CHANNEL_EVGEN_DMACH0 (30 << EVSYS_CHANNEL_EVGEN_SHIFT) /* DMAC CH0 Channel 0 */
# define EVSYS_CHANNEL_EVGEN_DMACH1 (31 << EVSYS_CHANNEL_EVGEN_SHIFT) /* DMAC CH1 Channel 1 */
# define EVSYS_CHANNEL_EVGEN_DMACH2 (32 << EVSYS_CHANNEL_EVGEN_SHIFT) /* DMAC CH2 Channel 2 */
# define EVSYS_CHANNEL_EVGEN_DMACH3 (33 << EVSYS_CHANNEL_EVGEN_SHIFT) /* DMAC CH3 Channel 3 */
# define EVSYS_CHANNEL_EVGEN_TCC0OVF (34 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC0 Overflow */
# define EVSYS_CHANNEL_EVGEN_TCC0TRG (35 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC0 Trig */
# define EVSYS_CHANNEL_EVGEN_TCC0CNT (36 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC0 Counter */
# define EVSYS_CHANNEL_EVGEN_TCC0MCX0 (37 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC0 Match/Capture 0 */
# define EVSYS_CHANNEL_EVGEN_TCC0MCX1 (38 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC0 Match/Capture 1 */
# define EVSYS_CHANNEL_EVGEN_TCC0MCX2 (39 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC0 Match/Capture 2 */
# define EVSYS_CHANNEL_EVGEN_TCC0MCX3 (40 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC0 Match/Capture 3 */
# define EVSYS_CHANNEL_EVGEN_TCC1OVF (41 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC1 Overflow */
# define EVSYS_CHANNEL_EVGEN_TCC1TRG (42 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC1 Trig */
# define EVSYS_CHANNEL_EVGEN_TCC1CNT (43 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC1 Counter */
# define EVSYS_CHANNEL_EVGEN_TCC1MCX0 (44 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC1 Match/Capture 0 */
# define EVSYS_CHANNEL_EVGEN_TCC1MCX1 (45 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC1 Match/Capture 1 */
# define EVSYS_CHANNEL_EVGEN_TCC2OVF (46 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC2 Overflow */
# define EVSYS_CHANNEL_EVGEN_TCC2TRG (47 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC2 Trig */
# define EVSYS_CHANNEL_EVGEN_TCC2CNT (48 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC2 Counter */
# define EVSYS_CHANNEL_EVGEN_TCC2MCX0 (49 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC2 Match/Capture 0 */
# define EVSYS_CHANNEL_EVGEN_TCC2MCX1 (50 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC2 Match/Capture 1 */
# define EVSYS_CHANNEL_EVGEN_TC3OVF (51 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC3 Overflow/Underflow */
# define EVSYS_CHANNEL_EVGEN_TC3MC0 (52 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC3 Match/Capture 0 */
# define EVSYS_CHANNEL_EVGEN_TC3MC1 (53 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC3 Match/Capture 1 */
# define EVSYS_CHANNEL_EVGEN_TC4OVF (54 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC4 Overflow/Underflow */
# define EVSYS_CHANNEL_EVGEN_TC4MC0 (55 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC4 Match/Capture 0 */
# define EVSYS_CHANNEL_EVGEN_TC4MC1 (56 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC4 Match/Capture 1 */
# define EVSYS_CHANNEL_EVGEN_TC5OVF (57 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC5 Overflow/Underflow */
# define EVSYS_CHANNEL_EVGEN_TC5MC0 (58 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC5 Match/Capture 0 */
# define EVSYS_CHANNEL_EVGEN_TC5MC1 (59 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC5 Match/Capture 1 */
# define EVSYS_CHANNEL_EVGEN_TC6OVF (60 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC6 Overflow/Underflow */
# define EVSYS_CHANNEL_EVGEN_TC6MC0 (61 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC6 Match/Capture 0 */
# define EVSYS_CHANNEL_EVGEN_TC6MC1 (62 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC6 Match/Capture 1 */
# define EVSYS_CHANNEL_EVGEN_TC7OVF (63 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC7 Overflow/Underflow */
# define EVSYS_CHANNEL_EVGEN_TC7MC0 (64 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC7 Match/Capture 0 */
# define EVSYS_CHANNEL_EVGEN_TC7MC1 (65 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC7 Match/Capture 1 */
# define EVSYS_CHANNEL_EVGEN_ADCRESRDY (66 << EVSYS_CHANNEL_EVGEN_SHIFT) /* ADC Result Ready */
# define EVSYS_CHANNEL_EVGEN_ADCWINMON (67 << EVSYS_CHANNEL_EVGEN_SHIFT) /* ADC Window Monitor */
# define EVSYS_CHANNEL_EVGEN_ACCOMP0 (68 << EVSYS_CHANNEL_EVGEN_SHIFT) /* AC Comparator 0 */
# define EVSYS_CHANNEL_EVGEN_ACCOMP1 (69 << EVSYS_CHANNEL_EVGEN_SHIFT) /* AC Comparator 1 */
# define EVSYS_CHANNEL_EVGEN_ACWIN (70 << EVSYS_CHANNEL_EVGEN_SHIFT) /* AC Window 0 */
# define EVSYS_CHANNEL_EVGEN_DACEMPTY (71 << EVSYS_CHANNEL_EVGEN_SHIFT) /* DAC Data Buffer Empty */
# define EVSYS_CHANNEL_EVGEN_PTCEOC (72 << EVSYS_CHANNEL_EVGEN_SHIFT) /* PTC End of Conversion */
# define EVSYS_CHANNEL_EVGEN_PTCWCOMP (73 << EVSYS_CHANNEL_EVGEN_SHIFT) /* PTC Window Comparator */
#endif
#define EVSYS_CHANNEL_PATH_SHIFT (24) /* Bits 24-25: Path Selection */
#define EVSYS_CHANNEL_PATH_MASK (3 << EVSYS_CHANNEL_PATH_SHIFT)
# define EVSYS_CHANNEL_PATH_SYNCH (0 << EVSYS_CHANNEL_PATH_SHIFT) /* Synchronous path */
# define EVSYS_CHANNEL_PATH_RESYNCH (1 << EVSYS_CHANNEL_PATH_SHIFT) /* Resynchronized path */
# define EVSYS_CHANNEL_PATH_ASYNCH (2 << EVSYS_CHANNEL_PATH_SHIFT) /* Asynchronous path */
#define EVSYS_CHANNEL_EDGSEL_SHIFT (26) /* Bits 26-27: Edge Detection Selection */
#define EVSYS_CHANNEL_EDGSEL_MASK (3 << EVSYS_CHANNEL_EDGSEL_SHIFT)
# define EVSYS_CHANNEL_EDGSEL_NOEVT (0 << EVSYS_CHANNEL_EDGSEL_SHIFT) /* No event output */
# define EVSYS_CHANNEL_EDGSEL_RISING (1 << EVSYS_CHANNEL_EDGSEL_SHIFT) /* Event detection on rising edge */
# define EVSYS_CHANNEL_EDGSEL_FALLING (2 << EVSYS_CHANNEL_EDGSEL_SHIFT) /* Event detection on falling edge */
# define EVSYS_CHANNEL_EDGSEL_BOTH (3 << EVSYS_CHANNEL_EDGSEL_SHIFT) /* Event detection on both edges */
/* User multiplexer register */
#define EVSYS_USER_SHIFT (0) /* Bits 0-4: User Multiplexer Selection */
#define EVSYS_USER_MASK (0x1f << EVSYS_USER_SHIFT)
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define EVSYS_USER_TC0 (0 << EVSYS_USER_SHIFT) /* TC0 paths */
# define EVSYS_USER_TC1 (1 << EVSYS_USER_SHIFT) /* TC1 paths */
# define EVSYS_USER_TC2 (2 << EVSYS_USER_SHIFT) /* TC2 paths */
# define EVSYS_USER_TC3 (3 << EVSYS_USER_SHIFT) /* TC3 paths */
# define EVSYS_USER_TC4 (4 << EVSYS_USER_SHIFT) /* TC4 paths */
# define EVSYS_USER_TC5 (5 << EVSYS_USER_SHIFT) /* TC5 paths */
# define EVSYS_USER_TC6 (6 << EVSYS_USER_SHIFT) /* TC6 paths */
# define EVSYS_USER_TC7 (7 << EVSYS_USER_SHIFT) /* TC7 paths */
# define EVSYS_USER_ADCSTART (8 << EVSYS_USER_SHIFT) /* ADC start conversion asynch path */
# define EVSYS_USER_ADCSYNC (9 << EVSYS_USER_SHIFT) /* Flush ADC asynch path */
# define EVSYS_USER_ACCOMP0 (10 << EVSYS_USER_SHIFT) /* Start comparator 0 asynch path */
# define EVSYS_USER_ACCOMP1 (11 << EVSYS_USER_SHIFT) /* Start comparator 1 asynch path */
# define EVSYS_USER_DACSTART (12 << EVSYS_USER_SHIFT) /* DAC start conversion asynch path */
# define EVSYS_USER_PTCSTCONV (13 << EVSYS_USER_SHIFT) /* PTC start conversion asynch path */
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define EVSYS_USER_DMACH0 (0 << EVSYS_USER_SHIFT) /* DMAC Channel 0 resync path */
# define EVSYS_USER_DMACH1 (1 << EVSYS_USER_SHIFT) /* DMAC Channel 1 resync path only */
# define EVSYS_USER_DMACH2 (2 << EVSYS_USER_SHIFT) /* DMAC Channel 2 resync path only */
# define EVSYS_USER_DMACH3 (3 << EVSYS_USER_SHIFT) /* DMAC Channel 3 resync path only */
# define EVSYS_USER_TCC0EV0 (4 << EVSYS_USER_SHIFT) /* TCC0 EV0 async, sync and resync paths */
# define EVSYS_USER_TCC0EV1 (5 << EVSYS_USER_SHIFT) /* TCC0 EV1 async, sync and resync paths */
# define EVSYS_USER_TCC0MC0 (6 << EVSYS_USER_SHIFT) /* TCC0 Match/Capture 0 async, sync and resync paths */
# define EVSYS_USER_TCC0MC1 (7 << EVSYS_USER_SHIFT) /* TCC0 Match/Capture 1 async, sync and resync paths */
# define EVSYS_USER_TCC0MC2 (8 << EVSYS_USER_SHIFT) /* TCC0 Match/Capture 2 async, sync and resync paths */
# define EVSYS_USER_TCCMC3 (9 << EVSYS_USER_SHIFT) /* TCC0 Match/Capture 3 async, sync and resync paths */
# define EVSYS_USER_TCC1EV0 (10 << EVSYS_USER_SHIFT) /* TCC1 EV0 async, sync and resync paths */
# define EVSYS_USER_TCC1EV1 (11 << EVSYS_USER_SHIFT) /* TCC1 EV1 async, sync and resync paths */
# define EVSYS_USER_TCC1MC0 (12 << EVSYS_USER_SHIFT) /* TCC1 Match/Capture 0 async, sync and resync paths */
# define EVSYS_USER_TCC1MC1 (13 << EVSYS_USER_SHIFT) /* TCC1 Match/Capture 1 async, sync and resync paths */
# define EVSYS_USER_TCC2EV0 (14 << EVSYS_USER_SHIFT) /* TCC2 EV0 async, sync and resync paths */
# define EVSYS_USER_TCC2EV1 (15 << EVSYS_USER_SHIFT) /* TCC2 EV1 async, sync and resync paths */
# define EVSYS_USER_TCC2MC0 (16 << EVSYS_USER_SHIFT) /* TCC2 Match/Capture 0 async, sync and resync paths */
# define EVSYS_USER_TCC2MC1 (17 << EVSYS_USER_SHIFT) /* TCC2 Match/Capture 1 async, sync and resync paths */
# define EVSYS_USER_TC3 (18 << EVSYS_USER_SHIFT) /* TC3 async, sync and resync paths */
# define EVSYS_USER_TC4 (19 << EVSYS_USER_SHIFT) /* TC4 async, sync and resync paths */
# define EVSYS_USER_TC5 (10 << EVSYS_USER_SHIFT) /* TC5 async, sync and resync paths */
# define EVSYS_USER_TC6 (21 << EVSYS_USER_SHIFT) /* TC6 async, TC and resync paths */
# define EVSYS_USER_TC7 (22 << EVSYS_USER_SHIFT) /* TC7 async, sync and resync paths */
# define EVSYS_USER_ADCSTART (23 << EVSYS_USER_SHIFT) /* ADC start conversion asynch path */
# define EVSYS_USER_ADCSYNC (24 << EVSYS_USER_SHIFT) /* Flush ADC asynch path */
# define EVSYS_USER_ACCOMP0 (25 << EVSYS_USER_SHIFT) /* Start comparator 0 asynch path */
# define EVSYS_USER_ACCOMP1 (26 << EVSYS_USER_SHIFT) /* Start comparator 1 asynch path */
# define EVSYS_USER_DACSTART (27 << EVSYS_USER_SHIFT) /* DAC start conversion asynch path */
# define EVSYS_USER_PTCSTCONV (28 << EVSYS_USER_SHIFT) /* PTC start conversion asynch path */
#endif
#define EVSYS_USER_CHANNEL_SHIFT (8) /* Bits 8-12: Channel Event Selection */
#define EVSYS_USER_CHANNEL_MASK (0x1f << EVSYS_USER_CHANNEL_SHIFT)
# define EVSYS_USER_CHANNEL_NONE (0 << EVSYS_USER_CHANNEL_SHIFT) /* No channel output selected */
# define EVSYS_USER_CHANNEL(n) ((uint16_t)((n)+1) << EVSYS_USER_CHANNEL_SHIFT)
/* Channel status register */
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define EVSYS_CHSTATUS_USRRDY_SHIFT (0) /* Bits 0-7: User Ready for Channel n, n=0-7 */
# define EVSYS_CHSTATUS_USRRDY_MASK (0xff << EVSYS_CHSTATUS_USRRDY_SHIFT)
# define EVSYS_CHSTATUS_USRRDY(n) (1 << (n))
# define EVSYS_CHSTATUS_CHBUSY_SHIFT (8) /* Bits 8-15: Channel Busy n, n=0-7 */
# define EVSYS_CHSTATUS_CHBUSY_MASK (0xff << EVSYS_CHSTATUS_CHBUSY_SHIFT)
# define EVSYS_CHSTATUS_CHBUSY(n) (1 << ((n) + 8))
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define EVSYS_CHSTATUS_USRRDYH_SHIFT (16) /* Bits 16-19: User Ready for Channel n, n=8-11 */
# define EVSYS_CHSTATUS_USRRDYH_MASK (15 << EVSYS_CHSTATUS_USRRDYH_SHIFT)
# define EVSYS_CHSTATUS_USRRDYH(n) (1 << ((n) + 8))
# define EVSYS_CHSTATUS_CHBUSYH_SHIFT (24) /* Bits 24-27: Channel Busy n, n=8-11 */
# define EVSYS_CHSTATUS_CHBUSYH_MASK (15 << EVSYS_CHSTATUS_CHBUSYH_SHIFT)
# define EVSYS_CHSTATUS_CHBUSYH(n) (1 << ((n) + 16))
#endif
/* Interrupt enable clear, interrupt enable set,
* and interrupt flag status and clear registers
*/
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define EVSYS_INT_OVR_SHIFT (0) /* Bits 0-7: Overrun channel n interrupt, n=0-7 */
# define EVSYS_INT_OVR_MASK (0xff << EVSYS_INT_OVR_SHIFT)
# define EVSYS_INT_OVR(n) (1 << (n))
# define EVSYS_INT_EVD_SHIFT (8) /* Bits 8-15: Event detected channel n interrupt, n=0-7 */
# define EVSYS_INT_EVD_MASK (0xff << EVSYS_INT_EVD_SHIFT)
# define EVSYS_INT_EVD(n) (1 << ((n) + 8))
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define EVSYS_INT_OVR_SHIFT (16) /* Bits 16-19: Overrun channel n interrupt, n=8-11 */
# define EVSYS_INT_OVR_MASK (15 << EVSYS_INT_OVR_SHIFT)
# define EVSYS_INT_OVR(n) (1 << ((n) + 8))
# define EVSYS_INT_EVD_SHIFT (24) /* Bits 24-27: Event detected channel n interrupt, n=8-11 */
# define EVSYS_INT_EVD_MASK (15 << EVSYS_INT_EVD_SHIFT)
# define EVSYS_INT_EVD(n) (1 << ((n) + 16))
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EVSYS_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_fuses.h
*
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Some fuse-related definitions derive from Atmel sample code:
*
* Copyright (c) 2013 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with
* an Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_FUSES_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_FUSES_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Fuse definitions *********************************************************/
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define NVMCTRL_FUSES_LOCKFIELD_ADDR (SAM_LOCKBIT_BASE + 0)
# define NVMCTRL_FUSES_LOCKFIELD_SHIFT (0) /* LOCK Region */
# define NVMCTRL_FUSES_LOCKFIELD_MASK (0xff << NVMCTRL_FUSES_LOCKFIELD_SHIFT)
# define NVMCTRL_FUSES_LOCKFIELD(n) ((n) << NVMCTRL_FUSES_LOCKFIELD_SHIFT)
#endif
#define NVMCTRL_FUSES_BOOTPROT_ADDR (SAM_AUX0_BASE + 0)
#define NVMCTRL_FUSES_BOOTPROT_SHIFT (0) /* Bits 0-2: Bootloader Size */
#define NVMCTRL_FUSES_BOOTPROT_MASK (7 << NVMCTRL_FUSES_BOOTPROT_SHIFT)
# define NVMCTRL_FUSES_BOOTPROT(n) ((n) << NVMCTRL_FUSES_BOOTPROT_SHIFT)
#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR (SAM_AUX0_BASE + 0)
#define NVMCTRL_FUSES_EEPROM_SIZE_SHIFT (4) /* Bits 4-6: EEPROM Size */
#define NVMCTRL_FUSES_EEPROM_SIZE_MASK (7 << NVMCTRL_FUSES_EEPROM_SIZE_SHIFT)
# define NVMCTRL_FUSES_EEPROM_SIZE(n) ((n) << NVMCTRL_FUSES_EEPROM_SIZE_SHIFT)
#define SYSCTRL_FUSES_BOD33USERLEVEL_ADDR (SAM_AUX0_BASE + 8)
#define SYSCTRL_FUSES_BOD33USERLEVEL_SHIFT (8) /* Bits 8-13: BOD33 User Level */
#define SYSCTRL_FUSES_BOD33USERLEVEL_MASK (0x3f << SYSCTRL_FUSES_BOD33USERLEVEL_SHIFT)
# define SYSCTRL_FUSES_BOD33USERLEVEL(n) ((n) << SYSCTRL_FUSES_BOD33USERLEVEL_SHIFT)
#define SYSCTRL_FUSES_BOD33_EN_ADDR (SAM_AUX0_BASE + 0)
#define SYSCTRL_FUSES_BOD33_EN_SHIFT (14) /* Bit 14: BOD33 Enable */
#define SYSCTRL_FUSES_BOD33_EN_MASK (1 << SYSCTRL_FUSES_BOD33_EN_SHIFT)
#define SYSCTRL_FUSES_BOD33_ACTION_ADDR (SAM_AUX0_BASE + 0)
#define SYSCTRL_FUSES_BOD33_ACTION_SHIFT (15) /* Bits 15-16: BOD33 Action */
#define SYSCTRL_FUSES_BOD33_ACTION_MASK (3 << SYSCTRL_FUSES_BOD33_ACTION_SHIFT)
# define SYSCTRL_FUSES_BOD33_ACTION(n) ((n) << SYSCTRL_FUSES_BOD33_ACTION_SHIFT)
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define SYSCTRL_FUSES_BOD12USERLEVEL_ADDR (SAM_AUX0_BASE + 0)
# define SYSCTRL_FUSES_BOD12USERLEVEL_SHIFT (17) /* Bit 17: BOD12 User Level */
# define SYSCTRL_FUSES_BOD12USERLEVEL_MASK (0x1f << SYSCTRL_FUSES_BOD12USERLEVEL_SHIFT)
# define SYSCTRL_FUSES_BOD12USERLEVEL(n) ((n) << SYSCTRL_FUSES_BOD12USERLEVEL_SHIFT)
# define SYSCTRL_FUSES_BOD12_ACTION_ADDR (SAM_AUX0_BASE + 0)
# define SYSCTRL_FUSES_BOD12_EN_ADDR (SAM_AUX0_BASE + 0)
# define SYSCTRL_FUSES_BOD12_EN_SHIFT (22) /* Bit 22: BOD12 Enable */
# define SYSCTRL_FUSES_BOD12_EN_MASK (1 << SYSCTRL_FUSES_BOD12_EN_SHIFT)
# define SYSCTRL_FUSES_BOD12_ACTION_SHIFT (23) /* Bits 23-24: BOD12 Action */
# define SYSCTRL_FUSES_BOD12_ACTION_MASK (3 << SYSCTRL_FUSES_BOD12_ACTION_SHIFT)
# define SYSCTRL_FUSES_BOD12_ACTION(n) ((n) << SYSCTRL_FUSES_BOD12_ACTION_SHIFT)
#endif
#define WDT_FUSES_ENABLE_ADDR (SAM_AUX0_BASE + 0)
#define WDT_FUSES_ENABLE_SHIFT (25) /* Bit 25: WDT Enable */
#define WDT_FUSES_ENABLE_MASK (1 << WDT_FUSES_ENABLE_SHIFT)
#define WDT_FUSES_ALWAYSON_ADDR (SAM_AUX0_BASE + 0)
#define WDT_FUSES_ALWAYSON_SHIFT (26) /* Bit 26: WDT Always On */
#define WDT_FUSES_ALWAYSON_MASK (1 << WDT_FUSES_ALWAYSON_SHIFT)
#define WDT_FUSES_PER_ADDR (SAM_AUX0_BASE + 0)
#define WDT_FUSES_PER_SHIFT (27) /* Bits 27-30: WDT Period */
#define WDT_FUSES_PER_MASK (15 << WDT_FUSES_PER_SHIFT)
# define WDT_FUSES_PER(n) ((n) << WDT_FUSES_PER_SHIFT)
#define WDT_FUSES_WINDOW_0_ADDR (SAM_AUX0_BASE + 0)
#define WDT_FUSES_WINDOW_0_SHIFT (31) /* Bit 31: WDT Window bit 0 */
#define WDT_FUSES_WINDOW_0_MASK (1 << WDT_FUSES_WINDOW_0_SHIFT)
#define WDT_FUSES_WINDOW_1_ADDR (SAM_AUX0_BASE + 4)
#define WDT_FUSES_WINDOW_1_SHIFT (0) /* Bits 32-34: WDT Window bits 3:1 */
#define WDT_FUSES_WINDOW_1_MASK (7 << WDT_FUSES_WINDOW_1_SHIFT)
# define WDT_FUSES_WINDOW_1(n) ((n) << WDT_FUSES_WINDOW_1_SHIFT)
#define WDT_FUSES_EWOFFSET_ADDR (SAM_AUX0_BASE + 4)
#define WDT_FUSES_EWOFFSET_SHIFT (3) /* Bits 35-38: WDT Early Warning Offset */
#define WDT_FUSES_EWOFFSET_MASK (15 << WDT_FUSES_EWOFFSET_SHIFT)
# define WDT_FUSES_EWOFFSET(n) ((n) << WDT_FUSES_EWOFFSET_SHIFT)
#define WDT_FUSES_WEN_ADDR (SAM_AUX0_BASE + 4)
#define WDT_FUSES_WEN_SHIFT (7) /* Bit 39: WDT Window Mode Enable */
#define WDT_FUSES_WEN_MASK (1 << WDT_FUSES_WEN_SHIFT)
#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (SAM_AUX0_BASE + 4)
#define NVMCTRL_FUSES_REGION_LOCKS_SHIFT (16) /* Bits 48-63: NVM Region Locks */
#define NVMCTRL_FUSES_REGION_LOCKS_MASK (0xffff << NVMCTRL_FUSES_REGION_LOCKS_SHIFT)
# define NVMCTRL_FUSES_REGION_LOCKS(n) ((n) << NVMCTRL_FUSES_REGION_LOCKS_SHIFT)
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define NVMCTRL_FUSES_NVM_LOCK_ADDR (SAM_AUX1_AREA1 + 0)
# define NVMCTRL_FUSES_NVM_LOCK_SHIFT (0) /* Bits 0-7: NVM Lock */
# define NVMCTRL_FUSES_NVM_LOCK_MASK (0xff << NVMCTRL_FUSES_NVM_LOCK_SHIFT)
# define NVMCTRL_FUSES_NVM_LOCK(n) ((n) << NVMCTRL_FUSES_NVM_LOCK_SHIFT)
# define NVMCTRL_FUSES_PSZ_ADDR (SAM_AUX1_AREA1 + 0)
# define NVMCTRL_FUSES_PSZ_SHIFT (8) /* Bits 8-11: NVM Page Size */
# define NVMCTRL_FUSES_PSZ_MASK (15 << NVMCTRL_FUSES_PSZ_SHIFT)
# define NVMCTRL_FUSES_PSZ(n) ((n) << NVMCTRL_FUSES_PSZ_SHIFT)
# define NVMCTRL_FUSES_NVMP_ADDR (SAM_AUX1_AREA1 + 0)
# define NVMCTRL_FUSES_NVMP_SHIFT (16) /* Bits 16-31: Number of NVM Pages */
# define NVMCTRL_FUSES_NVMP_MASK (0xffff << NVMCTRL_FUSES_NVMP_SHIFT)
# define NVMCTRL_FUSES_NVMP(n) ((n) << NVMCTRL_FUSES_NVMP_SHIFT)
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define DSU_FUSES_DCFG0_ADDR (SAM_AUX1_AREA2 + 0)
# define DSU_FUSES_DCFG0_SHIFT (0) /* Bits 0-31: Device Configuration 0 */
# define DSU_FUSES_DCFG0_MASK (0xffffffff << DSU_FUSES_DCFG0_SHIFT)
# define DSU_FUSES_DCFG0(n) ((n) << DSU_FUSES_DCFG0_SHIFT)
# define DSU_FUSES_DID_DEVSEL_ADDR (SAM_AUX1_AREA2 + 0)
# define DSU_FUSES_DID_DEVSEL_SHIFT (0) /* Bits 0-4: Device Number */
# define DSU_FUSES_DID_DEVSEL_MASK (0x1f << DSU_FUSES_DID_DEVSEL_SHIFT)
# define DSU_FUSES_DID_DEVSEL(n) ((n) << DSU_FUSES_DID_DEVSEL_SHIFT)
# define DSU_FUSES_DEV_FAMILY_CFG_0_ADDR (SAM_AUX1_AREA2 + 0)
# define DSU_FUSES_DEV_FAMILY_CFG_0_SHIFT (5) /* Bits 5-31: Device Family Configuration bits 26:0 */
# define DSU_FUSES_DEV_FAMILY_CFG_0_MASK (0x7ffffff << DSU_FUSES_DEV_FAMILY_CFG_0_SHIFT)
# define DSU_FUSES_DEV_FAMILY_CFG_0(n) ((n) << DSU_FUSES_DEV_FAMILY_CFG_0_SHIFT)
# define DSU_FUSES_DCFG1_ADDR (SAM_AUX1_AREA2 + 4)
# define DSU_FUSES_DCFG1_SHIFT (0) /* Bits 0-31: Device Configuration 1 */
# define DSU_FUSES_DCFG1_MASK (0xffffffff << DSU_FUSES_DCFG1_SHIFT)
# define DSU_FUSES_DCFG1(n) ((n) << DSU_FUSES_DCFG1_SHIFT)
# define DSU_FUSES_DEV_FAMILY_CFG_1_ADDR (SAM_AUX1_AREA2 + 4)
# define DSU_FUSES_DEV_FAMILY_CFG_1_SHIFT (0) /* Bits 0-15: Device Family Configuration bits 42:27 */
# define DSU_FUSES_DEV_FAMILY_CFG_1_MASK (0xffff << DSU_FUSES_DEV_FAMILY_CFG_1_SHIFT)
# define DSU_FUSES_DEV_FAMILY_CFG_1(n) ((n) << DSU_FUSES_DEV_FAMILY_CFG_1_SHIFT)
# define ADC_FUSES_DCFG_ADDR (SAM_AUX1_AREA2 + 4)
# define ADC_FUSES_DCFG_SHIFT (16) /* Bits 16-19: ADC Device Configuration */
# define ADC_FUSES_DCFG_MASK (15 << ADC_FUSES_DCFG_SHIFT)
# define ADC_FUSES_DCFG(n) ((n) << ADC_FUSES_DCFG_SHIFT)
# define ADC_FUSES_CMPDELAY_ADDR (SAM_AUX1_AREA2 + 4)
# define ADC_FUSES_CMPDELAY_SHIFT (16) /* Bit 16: ADC Comparator Delay */
# define ADC_FUSES_CMPDELAY_MASK (1 << ADC_FUSES_CMPDELAY_SHIFT)
# define ADC_FUSES_BOOSTEN_ADDR (SAM_AUX1_AREA2 + 4)
# define ADC_FUSES_BOOSTEN_SHIFT (17) /* Bit 17: ADC Boost Enable */
# define ADC_FUSES_BOOSTEN_MASK (1 << ADC_FUSES_BOOSTEN_SHIFT)
# define ADC_FUSES_VCMPULSE_ADDR (SAM_AUX1_AREA2 + 4)
# define ADC_FUSES_VCMPULSE_SHIFT (18) /* Bit 18: ADC VCM Pulse */
# define ADC_FUSES_VCMPULSE_MASK (1 << ADC_FUSES_VCMPULSE_SHIFT)
# define ADC_FUSES_BIAS_OPA_ADDR (SAM_AUX1_AREA2 + 4)
# define ADC_FUSES_BIAS_OPA_SHIFT (19) /* Bit 19: ADC OPA Bias */
# define ADC_FUSES_BIAS_OPA_MASK (1 << ADC_FUSES_BIAS_OPA_SHIFT)
# define DSU_FUSES_RAM_BIAS_ADDR (SAM_AUX1_AREA2 + 4)
# define DSU_FUSES_RAM_BIAS_SHIFT (20) /* Bits 20-21: RAM Bias */
# define DSU_FUSES_RAM_BIAS_MASK (3 << DSU_FUSES_RAM_BIAS_SHIFT)
# define DSU_FUSES_RAM_BIAS(n) ((n) << DSU_FUSES_RAM_BIAS_SHIFT)
# define DSU_FUSES_RAM_READ_MARGIN_ADDR (SAM_AUX1_AREA2 + 4)
# define DSU_FUSES_RAM_READ_MARGIN_SHIFT (22) /* Bits 22-25: RAM Read Margin */
# define DSU_FUSES_RAM_READ_MARGIN_MASK (15 << DSU_FUSES_RAM_READ_MARGIN_SHIFT)
# define DSU_FUSES_RAM_READ_MARGIN(n) ((n) << DSU_FUSES_RAM_READ_MARGIN_SHIFT)
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define SYSCTRL_FUSES_ULPVREG_ADDR (SAM_AUX1_AREA4 + 0)
# define SYSCTRL_FUSES_ULPVREG_SHIFT (0) /* Bits 0-2: ULP Regulator Fallback Mode */
# define SYSCTRL_FUSES_ULPVREG_MASK (7 << SYSCTRL_FUSES_ULPVREG_SHIFT)
# define SYSCTRL_FUSES_ULPVREG(n) ((n) << SYSCTRL_FUSES_ULPVREG_SHIFT)
# define ADC_FUSES_GAINCORR_ADDR (SAM_AUX1_AREA4 + 0)
# define ADC_FUSES_GAINCORR_SHIFT (3) /* Bits 3-14: ADC Gain Correction */
# define ADC_FUSES_GAINCORR_MASK (0xfff << ADC_FUSES_GAINCORR_SHIFT)
# define ADC_FUSES_GAINCORR(n) ((n) << ADC_FUSES_GAINCORR_SHIFT)
# define ADC_FUSES_OFFSETCORR_ADDR (SAM_AUX1_AREA4 + 0)
# define ADC_FUSES_OFFSETCORR_SHIFT (15) /* Bits 15-26: ADC Offset Correction */
# define ADC_FUSES_OFFSETCORR_MASK (0xfff << ADC_FUSES_OFFSETCORR_SHIFT)
# define ADC_FUSES_OFFSETCORR(n) ((n) << ADC_FUSES_OFFSETCORR_SHIFT)
#endif
#define ADC_FUSES_LINEARITY_0_ADDR (SAM_AUX1_AREA4 + 0)
#define ADC_FUSES_LINEARITY_0_SHIFT (27) /* Bits 27-31: ADC Linearity bits 4:0 */
#define ADC_FUSES_LINEARITY_0_MASK (0x1f << ADC_FUSES_LINEARITY_0_SHIFT)
# define ADC_FUSES_LINEARITY_0(n) ((n) << ADC_FUSES_LINEARITY_0_SHIFT)
#define ADC_FUSES_LINEARITY_1_ADDR (SAM_AUX1_AREA4 + 4)
#define ADC_FUSES_LINEARITY_1_SHIFT (0) /* Bits 32-34: ADC Linearity bits 7:5 */
#define ADC_FUSES_LINEARITY_1_MASK (7 << ADC_FUSES_LINEARITY_1_SHIFT)
# define ADC_FUSES_LINEARITY_1(n) ((n) << ADC_FUSES_LINEARITY_1_SHIFT)
#define ADC_FUSES_BIASCAL_ADDR (SAM_AUX1_AREA4 + 4)
#define ADC_FUSES_BIASCAL_SHIFT (3) /* Bits 35-27: ADC Bias Calibration */
#define ADC_FUSES_BIASCAL_MASK (7 << ADC_FUSES_BIASCAL_SHIFT)
# define ADC_FUSES_BIASCAL(n) ((n) << ADC_FUSES_BIASCAL_SHIFT)
#define SYSCTRL_FUSES_OSC32KCAL_ADDR (SAM_AUX1_AREA4 + 4)
#define SYSCTRL_FUSES_OSC32KCAL_SHIFT (6) /* Bits 38-44: OSC32K Calibration */
#define SYSCTRL_FUSES_OSC32KCAL_MASK (0x7f << SYSCTRL_FUSES_OSC32KCAL_SHIFT)
# define SYSCTRL_FUSES_OSC32KCAL(n) ((n) << SYSCTRL_FUSES_OSC32KCAL_SHIFT)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SYSCTRL_FUSES_USBTRANSN_ADDR (SAM_AUX1_AREA4 + 4)
# define SYSCTRL_FUSES_USBTRANSN_SHIFT (13) /* Bits 45-49: USB TRANSN calibration value. */
# define SYSCTRL_FUSES_USBTRANSN_MASK (0x1f << SYSCTRL_FUSES_USBTRANSN_SHIFT)
# define SYSCTRL_FUSES_USBTRANSN(n) ((n) << SYSCTRL_FUSES_USBTRANSN_SHIFT)
# define SYSCTRL_FUSES_USBTRANSP_ADDR (SAM_AUX1_AREA4 + 4)
# define SYSCTRL_FUSES_USBTRANSP_SHIFT (18) /* Bits 50-54: USB TRANSP calibration value. */
# define SYSCTRL_FUSES_USBTRANSP_MASK (0x1f << SYSCTRL_FUSES_USBTRANSP_SHIFT)
# define SYSCTRL_FUSES_USBTRANSP(n) ((n) << SYSCTRL_FUSES_USBTRANSP_SHIFT)
# define SYSCTRL_FUSES_USBTRIM_ADDR (SAM_AUX1_AREA4 + 4)
# define SYSCTRL_FUSES_USBTRIM_SHIFT (23) /* Bits 55-57: USB TRIM calibration value. */
# define SYSCTRL_FUSES_USBTRIM_MASK (7 << SYSCTRL_FUSES_USBTRIM_SHIFT)
# define SYSCTRL_FUSES_USBTRIM(n) ((n) << SYSCTRL_FUSES_USBTRIM_SHIFT)
# define SYSCTRL_FUSES_DFLL48MCOARSE_ADDR (SAM_AUX1_AREA4 + 4)
# define SYSCTRL_FUSES_DFLL48MCOARSE_SHIFT (26) /* Bits 58-63: DFLL48M Coarse calibration value. */
# define SYSCTRL_FUSES_DFLL48MCOARSE_MASK (0x3f << SYSCTRL_FUSES_DFLL48MCOARSE_SHIFT)
# define SYSCTRL_FUSES_DFLL48MCOARSE(n) ((n) << SYSCTRL_FUSES_DFLL48MCOARSE_SHIFT)
# define SYSCTRL_FUSES_DFLL48MFINE_ADDR (SAM_AUX1_AREA4 + 8)
# define SYSCTRL_FUSES_DFLL48MFINE_SHIFT (0) /* Bits 64-74: DFLL48M Fine calibration value. */
# define SYSCTRL_FUSES_DFLL48MFINE_MASK (0x7ff << SYSCTRL_FUSES_DFLL48MFINE_SHIFT)
# define SYSCTRL_FUSES_DFLL48MFINE(n) ((n) << SYSCTRL_FUSES_DFLL48MFINE_SHIFT)
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_FUSES_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_gclk.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_GCLK_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_GCLK_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* GCLK register offsets ****************************************************/
#define SAM_GCLK_CTRL_OFFSET 0x0000 /* Control register */
#define SAM_GCLK_STATUS_OFFSET 0x0001 /* Status register */
#define SAM_GCLK_CLKCTRL_OFFSET 0x0002 /* Generic clock control register */
#define SAM_GCLK_GENCTRL_OFFSET 0x0004 /* Generic clock generator control register */
#define SAM_GCLK_GENDIV_OFFSET 0x0008 /* Generic clock generator division register */
/* GCLK register addresses **************************************************/
#define SAM_GCLK_CTRL (SAM_GCLK_BASE+SAM_GCLK_CTRL_OFFSET)
#define SAM_GCLK_STATUS (SAM_GCLK_BASE+SAM_GCLK_STATUS_OFFSET)
#define SAM_GCLK_CLKCTRL (SAM_GCLK_BASE+SAM_GCLK_CLKCTRL_OFFSET)
#define SAM_GCLK_GENCTRL (SAM_GCLK_BASE+SAM_GCLK_GENCTRL_OFFSET)
#define SAM_GCLK_GENDIV (SAM_GCLK_BASE+SAM_GCLK_GENDIV_OFFSET)
/* GCLK register bit definitions ********************************************/
/* Control register */
#define GCLK_CTRL_SWRST (1 << 0) /* Bit 0: Software Reset */
/* Status register */
#define GCLK_STATUS_SYNCBUSY (1 << 7) /* Bit 7: Synchronization Busy Status */
/* Generic clock control register */
#define GCLK_CLKCTRL_ID_SHIFT (0) /* Bits 0-5: Generic Clock Selection ID */
#define GCLK_CLKCTRL_ID_MASK (0x3f << GCLK_CLKCTRL_ID_SHIFT)
# define GCLK_CLKCTRL_ID(n) ((n) << GCLK_CLKCTRL_ID_SHIFT)
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define GCLK_CLKCTRL_ID_DFLL48M (0 << GCLK_CLKCTRL_ID_SHIFT) /* DFLL48M Reference */
# define GCLK_CLKCTRL_ID_WDT (1 << GCLK_CLKCTRL_ID_SHIFT) /* WDT */
# define GCLK_CLKCTRL_ID_RTC (2 << GCLK_CLKCTRL_ID_SHIFT) /* RTC */
# define GCLK_CLKCTRL_ID_EIC (3 << GCLK_CLKCTRL_ID_SHIFT) /* EIC */
# define GCLK_CLKCTRL_ID_EVSYS(n) (((n)+4) << GCLK_CLKCTRL_ID_SHIFT)
# define GCLK_CLKCTRL_ID_EVSYS1 (5 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_1 */
# define GCLK_CLKCTRL_ID_EVSYS1 (5 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_1 */
# define GCLK_CLKCTRL_ID_EVSYS2 (6 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_2 */
# define GCLK_CLKCTRL_ID_EVSYS3 (7 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_3 */
# define GCLK_CLKCTRL_ID_EVSYS4 (8 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_4 */
# define GCLK_CLKCTRL_ID_EVSYS5 (9 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_5 */
# define GCLK_CLKCTRL_ID_EVSYS6 (10 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_6 */
# define GCLK_CLKCTRL_ID_EVSYS7 (11 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_7 */
# define GCLK_CLKCTRL_ID_SERCOMS (12 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOMx_SLOW */
# define GCLK_CLKCTRL_ID_SERCOMC(n) (((n)+13) << GCLK_CLKCTRL_ID_SHIFT)
# define GCLK_CLKCTRL_ID_SERCOM0C (13 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM0_CORE */
# define GCLK_CLKCTRL_ID_SERCOM1C (14 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM1_CORE */
# define GCLK_CLKCTRL_ID_SERCOM2C (15 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM2_CORE */
# define GCLK_CLKCTRL_ID_SERCOM3C (16 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM3_CORE */
# define GCLK_CLKCTRL_ID_SERCOM4C (17 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM4_CORE */
# define GCLK_CLKCTRL_ID_SERCOM5C (18 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM5_CORE */
# define GCLK_CLKCTRL_ID_TC01 (19 << GCLK_CLKCTRL_ID_SHIFT) /* TC0,TC1 */
# define GCLK_CLKCTRL_ID_TC23 (20 << GCLK_CLKCTRL_ID_SHIFT) /* TC2,TC3 */
# define GCLK_CLKCTRL_ID_TC45 (21 << GCLK_CLKCTRL_ID_SHIFT) /* TC4,TC5 */
# define GCLK_CLKCTRL_ID_TC67 (22 << GCLK_CLKCTRL_ID_SHIFT) /* TC6,TC7 */
# define GCLK_CLKCTRL_ID_ADC (23 << GCLK_CLKCTRL_ID_SHIFT) /* ADC */
# define GCLK_CLKCTRL_ID_ACDIG (24 << GCLK_CLKCTRL_ID_SHIFT) /* AC_DIG */
# define GCLK_CLKCTRL_ID_ACANA (25 << GCLK_CLKCTRL_ID_SHIFT) /* AC_ANA */
# define GCLK_CLKCTRL_ID_DAC (26 << GCLK_CLKCTRL_ID_SHIFT) /* DAC */
# define GCLK_CLKCTRL_ID_PTC (27 << GCLK_CLKCTRL_ID_SHIFT) /* PTC */
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define GCLK_CLKCTRL_ID_DFLL48M (0 << GCLK_CLKCTRL_ID_SHIFT) /* DFLL48M Reference */
# define GCLK_CLKCTRL_ID_DPLL (1 << GCLK_CLKCTRL_ID_SHIFT) /* FDPLL96M input clock source for reference */
# define GCLK_CLKCTRL_ID_DPLL32K (2 << GCLK_CLKCTRL_ID_SHIFT) /* FDPLL96M 32kHz clock for FDPLL96M internal lock timer */
# define GCLK_CLKCTRL_ID_WDT (3 << GCLK_CLKCTRL_ID_SHIFT) /* WDT */
# define GCLK_CLKCTRL_ID_RTC (4 << GCLK_CLKCTRL_ID_SHIFT) /* RTC */
# define GCLK_CLKCTRL_ID_EIC (5 << GCLK_CLKCTRL_ID_SHIFT) /* EIC */
# define GCLK_CLKCTRL_ID_USB (6 << GCLK_CLKCTRL_ID_SHIFT) /* USB */
# define GCLK_CLKCTRL_ID_EVSYS(n) (((n)+7) << GCLK_CLKCTRL_ID_SHIFT)
# define GCLK_CLKCTRL_ID_EVSYS0 (7 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_0 */
# define GCLK_CLKCTRL_ID_EVSYS1 (8 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_1 */
# define GCLK_CLKCTRL_ID_EVSYS2 (9 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_2 */
# define GCLK_CLKCTRL_ID_EVSYS3 (10 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_3 */
# define GCLK_CLKCTRL_ID_EVSYS4 (11 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_4 */
# define GCLK_CLKCTRL_ID_EVSYS5 (12 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_5 */
# define GCLK_CLKCTRL_ID_EVSYS6 (13 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_6 */
# define GCLK_CLKCTRL_ID_EVSYS7 (14 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_7 */
# define GCLK_CLKCTRL_ID_EVSYS8 (15 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_8 */
# define GCLK_CLKCTRL_ID_EVSYS9 (16 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_9 */
# define GCLK_CLKCTRL_ID_EVSYS10 (17 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_10 */
# define GCLK_CLKCTRL_ID_EVSYS11 (18 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_11 */
# define GCLK_CLKCTRL_ID_SERCOMS (19 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOMx_SLOW */
# define GCLK_CLKCTRL_ID_SERCOMC(n) (((n)+20) << GCLK_CLKCTRL_ID_SHIFT)
# define GCLK_CLKCTRL_ID_SERCOM0C (20 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM0_CORE */
# define GCLK_CLKCTRL_ID_SERCOM1C (21 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM1_CORE */
# define GCLK_CLKCTRL_ID_SERCOM2C (22 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM2_CORE */
# define GCLK_CLKCTRL_ID_SERCOM3C (23 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM3_CORE */
# define GCLK_CLKCTRL_ID_SERCOM4C (24 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM4_CORE */
# define GCLK_CLKCTRL_ID_SERCOM5C (25 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM5_CORE */
# define GCLK_CLKCTRL_ID_TCC01 (26 << GCLK_CLKCTRL_ID_SHIFT) /* TCC0,TCC1 */
# define GCLK_CLKCTRL_ID_TCC23 (27 << GCLK_CLKCTRL_ID_SHIFT) /* TCC2,TC3 */
# define GCLK_CLKCTRL_ID_TC45 (28 << GCLK_CLKCTRL_ID_SHIFT) /* TC4,TC5 */
# define GCLK_CLKCTRL_ID_TC67 (29 << GCLK_CLKCTRL_ID_SHIFT) /* TC6,TC7 */
# define GCLK_CLKCTRL_ID_ADC (30 << GCLK_CLKCTRL_ID_SHIFT) /* ADC */
# define GCLK_CLKCTRL_ID_ACDIG (31 << GCLK_CLKCTRL_ID_SHIFT) /* AC_DIG */
# define GCLK_CLKCTRL_ID_ACANA (32 << GCLK_CLKCTRL_ID_SHIFT) /* AC_ANA */
# define GCLK_CLKCTRL_ID_DAC (33 << GCLK_CLKCTRL_ID_SHIFT) /* DAC */
# define GCLK_CLKCTRL_ID_PTC (34 << GCLK_CLKCTRL_ID_SHIFT) /* PTC */
# define GCLK_CLKCTRL_ID_I2S0 (35 << GCLK_CLKCTRL_ID_SHIFT) /* I2S0 */
# define GCLK_CLKCTRL_ID_I2S1 (36 << GCLK_CLKCTRL_ID_SHIFT) /* I2S1 */
#endif
#define GCLK_CLKCTRL_GEN_SHIFT (8) /* Bits 8-11: Generic Clock Generator */
#define GCLK_CLKCTRL_GEN_MASK (15 << GCLK_CLKCTRL_GEN_SHIFT)
# define GCLK_CLKCTRL_GEN(n) ((n) << GCLK_CLKCTRL_GEN_SHIFT) /* Generic clock generator n */
# define GCLK_CLKCTRL_GEN0 (0 << GCLK_CLKCTRL_GEN_SHIFT) /* Generic clock generator 0 */
# define GCLK_CLKCTRL_GEN1 (1 << GCLK_CLKCTRL_GEN_SHIFT) /* Generic clock generator 1 */
# define GCLK_CLKCTRL_GEN2 (2 << GCLK_CLKCTRL_GEN_SHIFT) /* Generic clock generator 2 */
# define GCLK_CLKCTRL_GEN3 (3 << GCLK_CLKCTRL_GEN_SHIFT) /* Generic clock generator 3 */
# define GCLK_CLKCTRL_GEN4 (4 << GCLK_CLKCTRL_GEN_SHIFT) /* Generic clock generator 4 */
# define GCLK_CLKCTRL_GEN5 (5 << GCLK_CLKCTRL_GEN_SHIFT) /* Generic clock generator 5 */
# define GCLK_CLKCTRL_GEN6 (6 << GCLK_CLKCTRL_GEN_SHIFT) /* Generic clock generator 6 */
# define GCLK_CLKCTRL_GEN7 (7 << GCLK_CLKCTRL_GEN_SHIFT) /* Generic clock generator 7 */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define GCLK_CLKCTRL_GEN8 (8 << GCLK_CLKCTRL_GEN_SHIFT) /* Generic clock generator 8 */
#endif
#define GCLK_CLKCTRL_CLKEN (1 << 14) /* Bit 14: Clock Enable */
#define GCLK_CLKCTRL_WRTLOCK (1 << 15) /* Bit 15: Write Lock */
/* Generic clock generator control register */
#define GCLK_GENCTRL_ID_SHIFT (0) /* Bits 0-3: Generic Clock Generator Selection */
#define GCLK_GENCTRL_ID_MASK (15 << GCLK_GENCTRL_ID_SHIFT)
# define GCLK_GENCTRL_ID(n) ((n) << GCLK_GENCTRL_ID_SHIFT) /* Generic clock generator n */
# define GCLK_GENCTRL_ID0 (0 << GCLK_GENCTRL_ID_SHIFT) /* Generic clock generator 0 */
# define GCLK_GENCTRL_ID1 (1 << GCLK_GENCTRL_ID_SHIFT) /* Generic clock generator 1 */
# define GCLK_GENCTRL_ID2 (2 << GCLK_GENCTRL_ID_SHIFT) /* Generic clock generator 2 */
# define GCLK_GENCTRL_ID3 (3 << GCLK_GENCTRL_ID_SHIFT) /* Generic clock generator 3 */
# define GCLK_GENCTRL_ID4 (4 << GCLK_GENCTRL_ID_SHIFT) /* Generic clock generator 4 */
# define GCLK_GENCTRL_ID5 (5 << GCLK_GENCTRL_ID_SHIFT) /* Generic clock generator 5 */
# define GCLK_GENCTRL_ID6 (6 << GCLK_GENCTRL_ID_SHIFT) /* Generic clock generator 6 */
# define GCLK_GENCTRL_ID7 (7 << GCLK_GENCTRL_ID_SHIFT) /* Generic clock generator 7 */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define GCLK_GENCTRL_ID8 (8 << GCLK_GENCTRL_ID_SHIFT) /* Generic clock generator 8 */
#endif
#define GCLK_GENCTRL_SRC_SHIFT (8) /* Bits 8-12: Source Select */
#define GCLK_GENCTRL_SRC_MASK (31 << GCLK_GENCTRL_SRC_SHIFT)
# define GCLK_GENCTRL_SRC_XOSC (0 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC oscillator output */
# define GCLK_GENCTRL_SRC_GCLKIN (1 << GCLK_GENCTRL_SRC_SHIFT) /* Generator input pad */
# define GCLK_GENCTRL_SRC_GCLKGEN1 (2 << GCLK_GENCTRL_SRC_SHIFT) /* Generic clock generator 1 output */
# define GCLK_GENCTRL_SRC_OSCULP32K (3 << GCLK_GENCTRL_SRC_SHIFT) /* OSCULP32K oscillator output */
# define GCLK_GENCTRL_SRC_OSC32K (4 << GCLK_GENCTRL_SRC_SHIFT) /* OSC32K oscillator output */
# define GCLK_GENCTRL_SRC_XOSC32K (5 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC32K oscillator output */
# define GCLK_GENCTRL_SRC_OSC8M (6 << GCLK_GENCTRL_SRC_SHIFT) /* OSC8M oscillator output */
# define GCLK_GENCTRL_SRC_DFLL48M (7 << GCLK_GENCTRL_SRC_SHIFT) /* DFLL48M output */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define GCLK_GENCTRL_SRC_FDPLL96M (8 << GCLK_GENCTRL_SRC_SHIFT) /* FDPLL96M output */
#endif
#define GCLK_GENCTRL_GENEN (1 << 16) /* Bit 16: Generic Clock Generator Enable */
#define GCLK_GENCTRL_IDC (1 << 17) /* Bit 17: Improve Duty Cycle */
#define GCLK_GENCTRL_OOV (1 << 18) /* Bit 18: Output Off Value */
#define GCLK_GENCTRL_OE (1 << 19) /* Bit 19: Output Enable */
#define GCLK_GENCTRL_DIVSEL (1 << 20) /* Bit 20: Divide Selection */
#define GCLK_GENCTRL_RUNSTDBY (1 << 21) /* Bit 21: Run in Standby */
/* Generic clock generator division register */
#define GCLK_GENDIV_ID_SHIFT (0) /* Bits 0-3: Generic Clock Generator Selection */
#define GCLK_GENDIV_ID_MASK (15 << GCLK_GENDIV_ID_SHIFT)
# define GCLK_GENDIV_ID(n) ((n) << GCLK_GENDIV_ID_SHIFT) /* Generic clock generator n */
# define GCLK_GENDIV_ID0 (0 << GCLK_GENDIV_ID_SHIFT) /* Generic clock generator 0 */
# define GCLK_GENDIV_ID1 (1 << GCLK_GENDIV_ID_SHIFT) /* Generic clock generator 1 */
# define GCLK_GENDIV_ID2 (2 << GCLK_GENDIV_ID_SHIFT) /* Generic clock generator 2 */
# define GCLK_GENDIV_ID3 (3 << GCLK_GENDIV_ID_SHIFT) /* Generic clock generator 3 */
# define GCLK_GENDIV_ID4 (4 << GCLK_GENDIV_ID_SHIFT) /* Generic clock generator 4 */
# define GCLK_GENDIV_ID5 (5 << GCLK_GENDIV_ID_SHIFT) /* Generic clock generator 5 */
# define GCLK_GENDIV_ID6 (6 << GCLK_GENDIV_ID_SHIFT) /* Generic clock generator 6 */
# define GCLK_GENDIV_ID7 (7 << GCLK_GENDIV_ID_SHIFT) /* Generic clock generator 7 */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define GCLK_GENDIV_ID8 (8 << GCLK_GENCTRL_ID_SHIFT) /* Generic clock generator 8 */
#endif
#define GCLK_GENDIV_DIV_SHIFT (8) /* Bits 8-23: Division Factor */
#define GCLK_GENDIV_DIV_MASK (0xffff << GCLK_GENDIV_DIV_SHIFT)
# define GCLK_GENDIV_DIV(n) ((n) << GCLK_GENDIV_DIV_SHIFT)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_GCLK_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_i2c_master.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_MASTER_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_MASTER_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/samd_sercom.h"
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* I2C register offsets *****************************************************/
#define SAM_I2C_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_I2C_CTRLB_OFFSET 0x0004 /* Control B register */
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
# define SAM_I2C_BAUD_OFFSET 0x000a /* Baud register */
# define SAM_I2C_DBGCTRL_OFFSET 0x0008 /* Debug control register */
# define SAM_I2C_INTENCLR_OFFSET 0x000c /* Interrupt enable clear register */
# define SAM_I2C_INTENSET_OFFSET 0x000d /* Interrupt enable set register */
# define SAM_I2C_INTFLAG_OFFSET 0x000e /* Interrupt flag and status clear register */
# define SAM_I2C_STATUS_OFFSET 0x0010 /* Status register */
# define SAM_I2C_ADDR_OFFSET 0x0014 /* Address register */
# define SAM_I2C_DATA_OFFSET 0x0018 /* Data register */
#elif defined(CONFIG_ARCH_FAMILY_SAMD21)
# define SAM_I2C_BAUD_OFFSET 0x000c /* Baud register */
# define SAM_I2C_INTENCLR_OFFSET 0x0014 /* Interrupt enable clear register */
# define SAM_I2C_INTENSET_OFFSET 0x0016 /* Interrupt enable set register */
# define SAM_I2C_INTFLAG_OFFSET 0x0018 /* Interrupt flag and status clear register */
# define SAM_I2C_STATUS_OFFSET 0x001a /* Status register */
# define SAM_I2C_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */
# define SAM_I2C_ADDR_OFFSET 0x0024 /* Address register */
# define SAM_I2C_DATA_OFFSET 0x0028 /* Data register */
# define SAM_I2C_DBGCTRL_OFFSET 0x0030 /* Debug control register */
#endif
/* I2C register addresses ***************************************************/
#define SAM_I2C0_CTRLA (SAM_SERCOM0_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C0_CTRLB (SAM_SERCOM0_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C0_BAUD (SAM_SERCOM0_BASE+SAM_I2C_BAUD_OFFSET)
#define SAM_I2C0_INTENCLR (SAM_SERCOM0_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C0_INTENSET (SAM_SERCOM0_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C0_INTFLAG (SAM_SERCOM0_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C0_STATUS (SAM_SERCOM0_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C0_SYNCBUSY (SAM_SERCOM0_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C0_ADDR (SAM_SERCOM0_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C0_DATA (SAM_SERCOM0_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C0_DBGCTRL (SAM_SERCOM0_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C1_CTRLA (SAM_SERCOM1_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C1_CTRLB (SAM_SERCOM1_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C1_BAUD (SAM_SERCOM1_BASE+SAM_I2C_BAUD_OFFSET)
#define SAM_I2C1_INTENCLR (SAM_SERCOM1_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C1_INTENSET (SAM_SERCOM1_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C1_INTFLAG (SAM_SERCOM1_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C1_STATUS (SAM_SERCOM1_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C1_SYNCBUSY (SAM_SERCOM1_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C1_ADDR (SAM_SERCOM1_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C1_DATA (SAM_SERCOM1_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C1_DBGCTRL (SAM_SERCOM1_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C2_CTRLA (SAM_SERCOM2_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C2_CTRLB (SAM_SERCOM2_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C2_BAUD (SAM_SERCOM2_BASE+SAM_I2C_BAUD_OFFSET)
#define SAM_I2C2_INTENCLR (SAM_SERCOM2_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C2_INTENSET (SAM_SERCOM2_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C2_INTFLAG (SAM_SERCOM2_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C2_STATUS (SAM_SERCOM2_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C2_SYNCBUSY (SAM_SERCOM2_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C2_ADDR (SAM_SERCOM2_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C2_DATA (SAM_SERCOM2_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C2_DBGCTRL (SAM_SERCOM2_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C3_CTRLA (SAM_SERCOM3_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C3_CTRLB (SAM_SERCOM3_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C3_BAUD (SAM_SERCOM3_BASE+SAM_I2C_BAUD_OFFSET)
#define SAM_I2C3_INTENCLR (SAM_SERCOM3_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C3_INTENSET (SAM_SERCOM3_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C3_INTFLAG (SAM_SERCOM3_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C3_STATUS (SAM_SERCOM3_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C3_SYNCBUSY (SAM_SERCOM3_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C3_ADDR (SAM_SERCOM3_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C3_DATA (SAM_SERCOM3_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C3_DBGCTRL (SAM_SERCOM3_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C4_CTRLA (SAM_SERCOM4_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C4_CTRLB (SAM_SERCOM4_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C4_BAUD (SAM_SERCOM4_BASE+SAM_I2C_BAUD_OFFSET)
#define SAM_I2C4_INTENCLR (SAM_SERCOM4_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C4_INTENSET (SAM_SERCOM4_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C4_INTFLAG (SAM_SERCOM4_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C4_STATUS (SAM_SERCOM4_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C4_SYNCBUSY (SAM_SERCOM4_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C4_ADDR (SAM_SERCOM4_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C4_DATA (SAM_SERCOM4_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C4_DBGCTRL (SAM_SERCOM4_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C5_CTRLA (SAM_SERCOM5_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C5_CTRLB (SAM_SERCOM5_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C5_BAUD (SAM_SERCOM5_BASE+SAM_I2C_BAUD_OFFSET)
#define SAM_I2C5_INTENCLR (SAM_SERCOM5_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C5_INTENSET (SAM_SERCOM5_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C5_INTFLAG (SAM_SERCOM5_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C5_STATUS (SAM_SERCOM5_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C5_SYNCBUSY (SAM_SERCOM5_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C5_ADDR (SAM_SERCOM5_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C5_DATA (SAM_SERCOM5_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C5_DBGCTRL (SAM_SERCOM5_BASE+SAM_I2C_DBGCTRL_OFFSET)
/* I2C register bit definitions *********************************************/
/* Control A register */
#define I2C_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
#define I2C_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
#define I2C_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */
#define I2C_CTRLA_MODE_MASK (7 << I2C_CTRLA_MODE_SHIFT)
# define I2C_CTRLA_MODE_MASTER (5 << I2C_CTRLA_MODE_SHIFT) /* I2C master mode */
#define I2C_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */
#define I2C_CTRLA_PINOUT (1 << 16) /* Bit 16: Transmit data pinout */
# define I2C_CTRLA_1WIRE (0) /* 4-wire operation disable */
# define I2C_CTRLA_4WIRE I2C_CTRLA_PINOUT /* 4-wire operation enable */
#define I2C_CTRLA_SDAHOLD_SHIFT (20) /* Bits 20-21: SDA Hold Time */
#define I2C_CTRLA_SDAHOLD_MASK (3 << I2C_CTRLA_SDAHOLD_SHIFT)
# define I2C_CTRLA_SDAHOLD_DIS (0 << I2C_CTRLA_SDAHOLD_SHIFT) /* Disabled */
# define I2C_CTRLA_SDAHOLD_75NS (1 << I2C_CTRLA_SDAHOLD_SHIFT) /* 50-100ns hold time */
# define I2C_CTRLA_SDAHOLD_450NS (2 << I2C_CTRLA_SDAHOLD_SHIFT) /* 300-600ns hold time */
# define I2C_CTRLA_SDAHOLD_600NS (3 << I2C_CTRLA_SDAHOLD_SHIFT) /* 400-800ns hold time */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define I2C_CTRLA_MEXTTOEN (1 << 22) /* Bit 22: Master SCL low extend time-out */
# define I2C_CTRLA_SEXTTOEN (1 << 23) /* Bit 23: Slave SCL low extend time-out */
# define I2C_CTRLA_SPEED_SHIFT (24) /* Bits 24-25: Transfer speed */
# define I2C_CTRLA_SPEED_MASK (3 << I2C_CTRLA_SPEED_SHIFT)
# define I2C_CTRLA_SPEED_STANDARD (0 << I2C_CTRLA_SPEED_SHIFT) /* Standard-mode (<=100 kHz) and Fast-mode (<=400 kHz) */
# define I2C_CTRLA_SPEED_FAST (1 << I2C_CTRLA_SPEED_SHIFT) /* Fast-mode Plus (<=1 MHz) */
# define I2C_CTRLA_SPEED_HIGHSPEED (2 << I2C_CTRLA_SPEED_SHIFT) /* High-speed mode (<=3.4 MHz) */
# define I2C_CTRLA_SCLSM (1 << 27) /* Bit 27: SCL clock stretch mode */
#endif
#define I2C_CTRLA_INACTOUT_SHIFT (28) /* Bits 28-29: Inactive Time-Out */
#define I2C_CTRLA_INACTOUT_MASK (7 << I2C_CTRLA_INACTOUT_SHIFT)
# define I2C_CTRLA_INACTOUT_DIS (0 << I2C_CTRLA_INACTOUT_SHIFT) /* Disabled */
# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60µs) */
# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110µs) */
# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210µs) */
#define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */
/* Control B register */
#define I2C_CTRLB_SMEN (1 << 8) /* Bit 8: Smart Mode Enable */
#define I2C_CTRLB_QCEN (1 << 9) /* Bit 9: Quick Command Enable */
#define I2C_CTRLB_CMD_SHIFT (16) /* Bits 16-17: Command */
#define I2C_CTRLB_CMD_MASK (3 << I2C_CTRLB_CMD_SHIFT)
# define I2C_CTRLB_CMD_NOACTION (0 << I2C_CTRLB_CMD_SHIFT) /* No action */
# define I2C_CTRLB_CMD_ACKREP (1 << I2C_CTRLB_CMD_SHIFT) /* ACK followed by repeated START */
# define I2C_CTRLB_CMD_ACKREAD (2 << I2C_CTRLB_CMD_SHIFT) /* ACK followed by read operation */
# define I2C_CTRLB_CMD_ACKSTOP (3 << I2C_CTRLB_CMD_SHIFT) /* ACK followed by STOP */
#define I2C_CTRLB_ACKACT (1 << 18) /* Bit 18: Acknowledge Action */
# define I2C_CTRLB_ACK (0) /* Send ACK */
# define I2C_CTRLB_NACK I2C_CTRLB_ACKACT /* Send NACK */
/* Baud register (16-bit baud value) */
#define I2C_BAUD_SHIFT (0) /* Bits 0-7: Master baud rate */
#define I2C_BAUD_MASK (0xff << I2C_BAUD_SHIFT)
# define I2C_BAUD(n) ((uint16_t)(n) << I2C_BAUD_SHIFT)
#define I2C_BAUDLOW_SHIFT (8) /* Bits 8-15: Master baud rate low */
#define I2C_BAUDLOW_MASK (0xff << I2C_BAUDLOW_SHIFT)
# define I2C_BAUDLOW(n) (uint16_t)(n) << I2C_BAUDLOW_SHIFT
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define I2C_HSBAUD_SHIFT (16) /* Bits 16-23: High speed master baud rate */
# define I2C_HSBAUD_MASK (0xff << I2C_HSBAUD_SHIFT)
# define I2C_HSBAUD(n) ((uint16)(n) << I2C_HSBAUD_SHIFT)
# define I2C_HSBAUDLOW_SHIFT (24) /* Bits 24-31: High speed master baud rate low */
# define I2C_HSBAUDLOW_MASK (0xff << I2C_HSBAUDLOW_SHIFT)
# define I2C_HSBAUDLOW(n) (uint16)(n) << I2C_HSBAUDLOW_SHIFT
#endif
/* Interrupt enable clear, interrupt enable set, interrupt enable set,
* interrupt flag and status clear registers.
*/
#define I2C_INT_MB (1 << 0) /* Bit 0: Master on bus interrupt */
#define I2C_INT_SB (1 << 1) /* Bit 1: Slave on bus interrupt */
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
# define I2C_INT_ALL (0x03)
#elif defined(CONFIG_ARCH_FAMILY_SAMD21)
# define I2C_INT_ERROR (1 << 7) /* Bit 7: Error interrupt */
# define I2C_INT_ALL (0x03)
#endif
/* Status register */
#define I2C_STATUS_BUSERR (1 << 0) /* Bit 0: Bus Error */
#define I2C_STATUS_ARBLOST (1 << 1) /* Bit 1: Arbitration Lost */
#define I2C_STATUS_RXNACK (1 << 2) /* Bit 2: Received Not Acknowledge */
#define I2C_STATUS_BUSSTATE_SHIFT (4) /* Bits 4-5: Bus State */
#define I2C_STATUS_BUSSTATE_MASK (3 << I2C_STATUS_BUSSTATE_SHIFT)
# define I2C_STATUS_BUSSTATE_UNKNOWN (0 << I2C_STATUS_BUSSTATE_SHIFT) /* Unknown to master */
# define I2C_STATUS_BUSSTATE_IDLE (1 << I2C_STATUS_BUSSTATE_SHIFT) /* Waiting for transaction */
# define I2C_STATUS_BUSSTATE_OWNER (2 << I2C_STATUS_BUSSTATE_SHIFT) /* Master of bus owner */
# define I2C_STATUS_BUSSTATE_BUSY (3 << I2C_STATUS_BUSSTATE_SHIFT) /* Other master owns */
#define I2C_STATUS_LOWTOUT (1 << 6) /* Bit 6: SCL Low Time-Out */
#define I2C_STATUS_CLKHOLD (1 << 7) /* Bit 7: Clock Hold */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define I2C_STATUS_MEXTTOUT (1 << 8) /* Bit 8: Master SCL low extend time-out */
# define I2C_STATUS_SEXTTOUT (1 << 9) /* Bit 9: Slave SCL low extend time-out */
# define I2C_STATUS_LENERR (1 << 10) /* Bit 10: Transaction length error */
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define I2C_STATUS_SYNCBUSY (1 << 15) /* Bit 15: Synchronization busy */
#endif
/* Synchronization busy register */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define I2C_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset synchronization busy */
# define I2C_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: SERCOM enable synchronization busy */
# define I2C_SYNCBUSY_SYSOP (1 << 2) /* Bit 2: System operation synchronization busy */
# define I2C_SYNCBUSY_ALL 0x0007
#endif
/* Address register */
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define I2C_ADDR_SHIFT (0) /* Bits 0-7: Address */
# define I2C_ADDR_MASK (0xff << I2C_ADDR_SHIFT)
# define I2C_ADDR(n) ((uint16_t)(n) << I2C_ADDR_SHIFT)
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define I2C_ADDR_SHIFT (0) /* Bits 0-10: Address */
# define I2C_ADDR_MASK (0x7ff << I2C_ADDR_SHIFT)
# define I2C_ADDR(n) ((uint32_t)(n) << I2C_ADDR_SHIFT)
# define I2C_ADDR_LENEN (1 << 13) /* Bit 13: Transfer length enable */
# define I2C_ADDR_HS (1 << 14) /* Bit 14: High speed */
# define I2C_ADDR_TENBITEN (1 << 15) /* Bit 15: Ten Bit Addressing Enable */
# define I2C_ADDR_LEN_SHIFT (16) /* Bits 16-23: Transaction Length */
# define I2C_ADDR_LEN_MASK (0xff << I2C_ADDR_LEN_SHIFT)
# define I2C_ADDR_LEN(n) ((uint32_t)(n) << I2C_ADDR_LEN_SHIFT)
#endif
/* Data register */
#define I2C_DATA_MASK (0x00ff) /* Bits 0-7: Data */
/* Debug control register */
#define I2C_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_MASTER_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_i2c_slave.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_SLAVE_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_SLAVE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/samd_sercom.h"
#ifdef CONFIG_ARCH_FAMILY_SAMD20
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* I2C register offsets *****************************************************/
#define SAM_I2C_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_I2C_CTRLB_OFFSET 0x0004 /* Control B register */
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
# define SAM_I2C_INTENCLR_OFFSET 0x000c /* Interrupt enable clear register */
# define SAM_I2C_INTENSET_OFFSET 0x000d /* Interrupt enable set register */
# define SAM_I2C_INTFLAG_OFFSET 0x000e /* Interrupt flag and status clear register */
# define SAM_I2C_STATUS_OFFSET 0x0010 /* Status register */
# define SAM_I2C_ADDR_OFFSET 0x0014 /* Address register */
# define SAM_I2C_DATA_OFFSET 0x0018 /* Data register */
#elif defined(CONFIG_ARCH_FAMILY_SAMD21)
# define SAM_I2C_INTENCLR_OFFSET 0x0014 /* Interrupt enable clear register */
# define SAM_I2C_INTENSET_OFFSET 0x0016 /* Interrupt enable set register */
# define SAM_I2C_INTFLAG_OFFSET 0x0018 /* Interrupt flag and status clear register */
# define SAM_I2C_STATUS_OFFSET 0x001a /* Status register */
# define SAM_I2C_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */
# define SAM_I2C_ADDR_OFFSET 0x0024 /* Address register */
# define SAM_I2C_DATA_OFFSET 0x0028 /* Data register */
#endif
/* I2C register addresses ***************************************************/
#define SAM_I2C0_CTRLA (SAM_SERCOM0_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C0_CTRLB (SAM_SERCOM0_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C0_INTENCLR (SAM_SERCOM0_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C0_INTENSET (SAM_SERCOM0_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C0_INTFLAG (SAM_SERCOM0_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C0_STATUS (SAM_SERCOM0_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C0_SYNCBUSY (SAM_SERCOM0_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C0_ADDR (SAM_SERCOM0_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C0_DATA (SAM_SERCOM0_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C1_CTRLA (SAM_SERCOM1_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C1_CTRLB (SAM_SERCOM1_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C1_INTENCLR (SAM_SERCOM1_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C1_INTENSET (SAM_SERCOM1_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C1_INTFLAG (SAM_SERCOM1_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C1_STATUS (SAM_SERCOM1_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C1_SYNCBUSY (SAM_SERCOM1_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C1_ADDR (SAM_SERCOM1_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C1_DATA (SAM_SERCOM1_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C2_CTRLA (SAM_SERCOM2_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C2_CTRLB (SAM_SERCOM2_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C2_INTENCLR (SAM_SERCOM2_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C2_INTENSET (SAM_SERCOM2_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C2_INTFLAG (SAM_SERCOM2_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C2_STATUS (SAM_SERCOM2_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C2_SYNCBUSY (SAM_SERCOM2_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C2_ADDR (SAM_SERCOM2_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C2_DATA (SAM_SERCOM2_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C3_CTRLA (SAM_SERCOM3_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C3_CTRLB (SAM_SERCOM3_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C3_INTENCLR (SAM_SERCOM3_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C3_INTENSET (SAM_SERCOM3_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C3_INTFLAG (SAM_SERCOM3_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C3_STATUS (SAM_SERCOM3_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C3_SYNCBUSY (SAM_SERCOM3_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C3_ADDR (SAM_SERCOM3_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C3_DATA (SAM_SERCOM3_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C4_CTRLA (SAM_SERCOM4_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C4_CTRLB (SAM_SERCOM4_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C4_INTENCLR (SAM_SERCOM4_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C4_INTENSET (SAM_SERCOM4_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C4_INTFLAG (SAM_SERCOM4_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C4_STATUS (SAM_SERCOM4_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C4_SYNCBUSY (SAM_SERCOM4_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C4_ADDR (SAM_SERCOM4_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C4_DATA (SAM_SERCOM4_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C5_CTRLA (SAM_SERCOM5_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C5_CTRLB (SAM_SERCOM5_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C5_INTENCLR (SAM_SERCOM5_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C5_INTENSET (SAM_SERCOM5_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C5_INTFLAG (SAM_SERCOM5_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C5_STATUS (SAM_SERCOM5_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C5_SYNCBUSY (SAM_SERCOM5_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C5_ADDR (SAM_SERCOM5_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C5_DATA (SAM_SERCOM5_BASE+SAM_I2C_DATA_OFFSET)
/* I2C register bit definitions *********************************************/
/* Control A register */
#define I2C_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
#define I2C_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
#define I2C_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */
#define I2C_CTRLA_MODE_MASK (7 << I2C_CTRLA_MODE_SHIFT)
# define I2C_CTRLA_MODE_SLAVE (4 << I2C_CTRLA_MODE_SHIFT) /* I2C slave mode */
#define I2C_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */
#define I2C_CTRLA_PINOUT (1 << 16) /* Bit 16: Transmit data pinout */
# define I2C_CTRLA_1WIRE (0) /* 4-wire operation disable */
# define I2C_CTRLA_4WIRE I2C_CTRLA_PINOUT /* 4-wire operation enable */
#define I2C_CTRLA_SDAHOLD_SHIFT (20) /* Bits 20-21: SDA Hold Time */
#define I2C_CTRLA_SDAHOLD_MASK (3 << I2C_CTRLA_SDAHOLD_SHIFT)
# define I2C_CTRLA_SDAHOLD_DIS (0 << I2C_CTRLA_SDAHOLD_SHIFT) /* Disabled */
# define I2C_CTRLA_SDAHOLD_75NS (1 << I2C_CTRLA_SDAHOLD_SHIFT) /* 50-100ns hold time */
# define I2C_CTRLA_SDAHOLD_450NS (2 << I2C_CTRLA_SDAHOLD_SHIFT) /* 300-600ns hold time */
# define I2C_CTRLA_SDAHOLD_600NS (3 << I2C_CTRLA_SDAHOLD_SHIFT) /* 400-800ns hold time */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define I2C_CTRLA_SEXTTOEN (1 << 23) /* Bit 23: Slave SCL low extend time-out */
# define I2C_CTRLA_SPEED_SHIFT (24) /* Bits 24-25: Transfer speed */
# define I2C_CTRLA_SPEED_MASK (3 << I2C_CTRLA_SPEED_SHIFT)
# define I2C_CTRLA_SPEED_STANDARD (0 << I2C_CTRLA_SPEED_SHIFT) /* Standard-mode (<=100 kHz) and Fast-mode (<=400 kHz) */
# define I2C_CTRLA_SPEED_FAST (1 << I2C_CTRLA_SPEED_SHIFT) /* Fast-mode Plus (<=1 MHz) */
# define I2C_CTRLA_SPEED_HIGHSPEED (2 << I2C_CTRLA_SPEED_SHIFT) /* High-speed mode (<=3.4 MHz) */
# define I2C_CTRLA_SCLSM (1 << 27) /* Bit 27: SCL clock stretch mode */
#endif
#define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL low time-out */
/* Control B register */
#define I2C_CTRLB_SMEN (1 << 8) /* Bit 8: Smart Mode Enable */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define I2C_CTRLB_GCMD (1 << 9) /* Bit 8: PMBus group command */
# define I2C_CTRLB_AACKEN (1 << 10) /* Bit 10: Automatic acknowledge enable */
#endif
#define I2C_CRLB_AMODE_SHIFT (14) /* Bits 14-15: Address Mode */
#define I2C_CRLB_AMODE_MASK (3 << I2C_CRLB_AMODE_SHIFT)
# define I2C_CRLB_AMODE_MASK (0 << I2C_CRLB_AMODE_SHIFT) /* ADDRMASK used to mask ADDR */
# define I2C_CRLB_AMODE_2ADDRS (1 << I2C_CRLB_AMODE_SHIFT) /* Slave 2 addresses: ADDR & ADDRMASK */
# define I2C_CRLB_AMODE_RANGE (2 << I2C_CRLB_AMODE_SHIFT) /* Slave range of addresses: ADDRMASK-ADDR */
#define I2C_CTRLB_CMD_SHIFT (16) /* Bits 16-17: Command */
#define I2C_CTRLB_CMD_MASK (3 << I2C_CTRLB_CMD_SHIFT)
# define I2C_CTRLB_CMD_NOACTION (0 << I2C_CTRLB_CMD_SHIFT) /* No action */
# define I2C_CTRLB_CMD_WAITSTART (2 << I2C_CTRLB_CMD_SHIFT) /* ACK (write) wait for START */
# define I2C_CTRLB_CMD_ACKREAD (3 << I2C_CTRLB_CMD_SHIFT) /* ACK with read (context dependent) */
#define I2C_CTRLB_ACKACT (1 << 18) /* Bit 18: Acknowledge Action */
# define I2C_CTRLB_ACK (0) /* Send ACK */
# define I2C_CTRLB_NCK I2C_CTRLB_ACKACT /* Send NACK */
/* Interrupt enable clear, interrupt enable set, interrupt enable set,
* interrupt flag and status clear registers.
*/
#define I2C_INT_PREC (1 << 0) /* Bit 0: Stop received interrupt */
#define I2C_INT_AMATCH (1 << 1) /* Bit 1: Address match interrupt */
#define I2C_INT_DRDY (1 << 2) /* Bit 2: Data ready interrupt */
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
# define I2C_INT_ALL (0x07)
#elif defined(CONFIG_ARCH_FAMILY_SAMD21)
# define I2C_INT_ERROR (1 << 7) /* Bit 7: Error interrupt */
# define I2C_INT_ALL (0x87)
#endif
/* Status register */
#define I2C_STATUS_BUSERR (1 << 0) /* Bit 0: Bus Error */
#define I2C_STATUS_COLL (1 << 1) /* Bit 1: Transmit Collision */
#define I2C_STATUS_RXNACK (1 << 2) /* Bit 2: Received Not Acknowledge */
#define I2C_STATUS_DIR (1 << 3) /* Bit 3: Read / Write Direction */
#define I2C_STATUS_SR (1 << 4) /* Bit 4: Repeated Start */
#define I2C_STATUS_LOWTOUT (1 << 6) /* Bit 6: SCL Low Time-Out */
#define I2C_STATUS_CLKHOLD (1 << 7) /* Bit 7: Clock Hold */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define I2C_STATUS_SEXTTOUT (1 << 9) /* Bit 9: Slave SCL low extend time-out */
# define I2C_STATUS_HS (1 << 10) /* Bit 10: High speed */
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define I2C_STATUS_SYNCBUSY (1 << 15) /* Bit 15: Synchronization busy */
#endif
/* Synchronization busy register */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define I2C_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset synchronization busy */
# define I2C_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: SERCOM enable synchronization busy */
# define I2C_SYNCBUSY_ALL 0x0003
#endif
/* Address register */
#define SPI_ADDR_GENCEN (1 << 0) /* Bit 0: General call address enable */
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define SPI_ADDR_SHIFT (1) /* Bits 1-7: Address */
# define SPI_ADDR_MASK (0x7f << SPI_ADDR_SHIFT)
# define SPI_ADDR(n) ((uint32_t)(n) << SPI_ADDR_SHIFT)
# define SPI_ADDRMASK_SHIFT (17) /* Bits 17-23: Address Mask */
# define SPI_ADDRMASK_MASK (0x7f << SPI_ADDRMASK_SHIFT)
# define SPI_ADDRMASK(n) ((uint32_t)(n) << SPI_ADDRMASK_SHIFT)
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SPI_ADDR_SHIFT (1) /* Bits 1-10: Address */
# define SPI_ADDR_MASK (0x3ff << SPI_ADDR_SHIFT)
# define SPI_ADDR(n) ((uint32_t)(n) << SPI_ADDR_SHIFT)
# define SPI_ADDR_TENBITEN (1 << 15) /* Bit 15: Ten bit addressing enable */
# define SPI_ADDRMASK_SHIFT (17) /* Bits 17-26: Address Mask */
# define SPI_ADDRMASK_MASK (0x3ff << SPI_ADDRMASK_SHIFT)
# define SPI_ADDRMASK(n) ((uint32_t)(n) << SPI_ADDRMASK_SHIFT)
#endif
/* Data register */
#define I2C_DATA_MASK (0xooff) /* Bits 0-7: Data */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD20 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_SLAVE_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_i2s.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Matt Thompson <matt@extent3d.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* References:
* "Microchip SAMD21 datasheet"
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2S_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2S_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_ARCH_FAMILY_SAMD21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* I2S register offsets *****************************************************/
#define SAM_I2S_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_I2S_CLKCTRL0_OFFSET 0x0004 /* Clock Control 0 register */
#define SAM_I2S_CLKCTRL1_OFFSET 0x0008 /* Clock Control 1 register */
#define SAM_I2S_INTENCLR_OFFSET 0x000C /* Interrupt enable clear register */
#define SAM_I2S_INTENSET_OFFSET 0x0010 /* Interrupt enable set register */
#define SAM_I2S_INTFLAG_OFFSET 0x0014 /* Interrupt flag register */
#define SAM_I2S_SYNCBUSY_OFFSET 0x0018 /* Sync Busy register */
#define SAM_I2S_SERCTRL0_OFFSET 0x0020 /* Serializer 0 Control register */
#define SAM_I2S_SERCTRL1_OFFSET 0x0024 /* Serializer 1 Control register */
#define SAM_I2S_DATA0_OFFSET 0x0030 /* Data 0 register */
#define SAM_I2S_DATA1_OFFSET 0x0034 /* Data 1 register */
/* I2S register addresses ***************************************************/
#define SAM_I2S_CTRLA (SAM_I2S_BASE+SAM_I2S_CTRLA_OFFSET)
#define SAM_I2S_CLKCTRL0 (SAM_I2S_BASE+SAM_I2S_CLKCTRL0_OFFSET)
#define SAM_I2S_CLKCTRL1 (SAM_I2S_BASE+SAM_I2S_CLKCTRL1_OFFSET)
#define SAM_I2S_INTENCLR (SAM_I2S_BASE+SAM_I2S_INTENCLR_OFFSET)
#define SAM_I2S_INTENSET (SAM_I2S_BASE+SAM_I2S_INTENSET_OFFSET)
#define SAM_I2S_INTFLAG (SAM_I2S_BASE+SAM_I2S_INTFLAG_OFFSET)
#define SAM_I2S_SYNCBUSY (SAM_I2S_BASE+SAM_I2S_SYNCBUSY_OFFSET)
#define SAM_I2S_SERCTRL0 (SAM_I2S_BASE+SAM_I2S_SERCTRL0_OFFSET)
#define SAM_I2S_SERCTRL1 (SAM_I2S_BASE+SAM_I2S_SERCTRL1_OFFSET)
#define SAM_I2S_DATA0 (SAM_I2S_BASE+SAM_I2S_DATA0_OFFSET)
#define SAM_I2S_DATA1 (SAM_I2S_BASE+SAM_I2S_DATA1_OFFSET)
/* I2S register bit definitions *********************************************/
/* Control A register */
#define I2S_CTRLA_SWRST (1 << 0) /* Bit 0: Software Reset */
#define I2S_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
#define I2S_CTRLA_CKEN0 (1 << 2) /* Bit 2: Clock Unit 0 Enable */
#define I2S_CTRLA_CKEN1 (1 << 3) /* Bit 3: Clock Unit 1 Enable */
#define I2S_CTRLA_SEREN0 (1 << 4) /* Bit 4: Serializer 0 Enable */
#define I2S_CTRLA_SEREN1 (1 << 5) /* Bit 5: Seriailier 1 Enable */
/* Clock Unit Control Register */
#define I2S_CLKCTRL_SLOTSIZE_SHIFT (0) /* Bits [1:0]: Slot Size */
#define I2S_CLKCTRL_SLOTSIZE_MASK (3 << I2S_CLKCTRL_SLOTSIZE_SHIFT)
# define I2S_CLKCTRL_SLOTSIZE_8 (0 << I2S_CLKCTRL_SLOTSIZE_SHIFT)
# define I2S_CLKCTRL_SLOTSIZE_16 (1 << I2S_CLKCTRL_SLOTSIZE_SHIFT)
# define I2S_CLKCTRL_SLOTSIZE_24 (2 << I2S_CLKCTRL_SLOTSIZE_SHIFT)
# define I2S_CLKCTRL_SLOTSIZE_32 (3 << I2S_CLKCTRL_SLOTSIZE_SHIFT)
#define I2S_CLKCTRL_NBSLOTS_SHIFT (2) /* Bit 2: Number of Slots in Frame */
#define I2S_CLKCTRL_NBSLOTS_MASK (7 << I2S_CLKCTRL_NBSLOTS_SHIFT)
#define I2S_CLKCTRL_NBSLOTS(n) (((n) & 0x7) << I2S_CLKCTRL_NBSLOTS_SHIFT)
#define I2S_CLKCTRL_FSWIDTH_SHIFT (5) /* Bits [6:5]: Frame Sync Width */
#define I2S_CLKCTRL_FSWIDTH_MASK (3 << I2S_CLKCTRL_FSWIDTH_SHIFT)
# define I2S_CLKCTRL_FSWIDTH_SLOT (0 << I2S_CLKCTRL_FSWIDTH_SHIFT)
# define I2S_CLKCTRL_FSWIDTH_HALF (1 << I2S_CLKCTRL_FSWIDTH_SHIFT)
# define I2S_CLKCTRL_FSWIDTH_BIT (2 << I2S_CLKCTRL_FSWIDTH_SHIFT)
# define I2S_CLKCTRL_FSWIDTH_BURST (3 << I2S_CLKCTRL_FSWIDTH_SHIFT)
#define I2S_CLKCTRL_BITDELAY (1 << 7) /* Bit 7: Data Delay from Frame Sync */
#define I2S_CLKCTRL_FSSEL (1 << 8) /* Bit 8: Frame Sync Select */
#define I2S_CLKCTRL_FSINV (1 << 11) /* Bit 11: Frame Sync Invert */
#define I2S_CLKCTRL_SCKSEL (1 << 12) /* Bit 12: Serial Clock Select. 0: Divided Master clock, 1: SCKn input pin */
#define I2S_CLKCTRL_MCKSEL (1 << 16) /* Bit 16: Master Clock Select. 0: GCLK, 1: MCKn input pin */
#define I2S_CLKCTRL_MCKEN (1 << 18) /* Bit 18: Master Clock Enable */
#define I2S_CLKCTRL_MCKDIV_SHIFT (19) /* Bits [23:19]: Master Clock Division Factor */
#define I2S_CLKCTRL_MCKDIV_MASK (0x1f << I2S_CLKCTRL_MCKDIV_SHIFT)
#define I2S_CLKCTRL_MCKDIV(n) (((n) & 0x1f) << I2S_CLKCTRL_MCKDIV_SHIFT)
#define I2S_CLKCTRL_MCKOUTDIV_SHIFT (24) /* Bits [28:24]: Master Clock Output Division Factor */
#define I2S_CLKCTRL_MCKOUTDIV_MASK (0x1f << I2S_CLKCTRL_MCKOUTDIV_SHIFT)
#define I2S_CLKCTRL_MCKOUTDIV(n) (((n) & 0x1f) << I2S_CLKCTRL_MCKOUTDIV_SHIFT)
#define I2S_CLKCTRL_FSOUTINV (1 << 29) /* Bit 29: Frame Sync Output Invert */
#define I2S_CLKCTRL_SCKOUTINV (1 << 30) /* Bit 30: Serial Clock Output Invert */
#define I2S_CLKCTRL_MCKOUTINV (1 << 31) /* Bit 31: Master Clock Output Invert */
/* Interrupt register bits */
#define I2S_INT_RXRDY0 (1 << 0) /* Bit 0: Receive Ready 0 */
#define I2S_INT_RXRDY1 (1 << 1) /* Bit 1: Receive Ready 1 */
#define I2S_INT_RXOR0 (1 << 4) /* Bit 4: Receive Overrun 0 */
#define I2S_INT_RXOR1 (1 << 5) /* Bit 5: Receive Overrun 1 */
#define I2S_INT_TXRDY0 (1 << 8) /* Bit 8: Transmit Ready 0 */
#define I2S_INT_TXRDY1 (1 << 9) /* Bit 9: Transmit Ready 1 */
#define I2S_INT_TXUR0 (1 << 12) /* Bit 12: Transmit Underrun 0 */
#define I2S_INT_TXUR1 (1 << 13) /* Bit 13: Transmit Underrun 1 */
#define I2S_INT_ALL (0x3333)
/* Sync Busy register bits */
#define I2S_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software Reset Sync Status */
#define I2S_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: Enable Sync Status */
#define I2S_SYNCBUSY_CKEN0 (1 << 2) /* Bit 2: Clock Unit 0 Sync Status */
#define I2S_SYNCBUSY_CKEN1 (1 << 3) /* Bit 3: Clock Unit 1 Sync Status */
#define I2S_SYNCBUSY_SEREN0 (1 << 4) /* Bit 4: Serializer 0 Enable Sync Status */
#define I2S_SYNCBUSY_SEREN1 (1 << 5) /* Bit 5: Seriaiizer 1 Enable Sync Status */
#define I2S_SYNCBUSY_DATA0 (1 << 8) /* Bit 8: Data 0 Sync Status */
#define I2S_SYNCBUSY_DATA1 (1 << 9) /* Bit 9: Data 1 Sync Status */
/* Serializer Control register bits */
#define I2S_SERCTRL_SERMODE_SHIFT (0) /* Bits [1:0]: Seriailizer Mode */
#define I2S_SERCTRL_SERMODE_MASK (3 << I2S_SERCTRL_SERMODE_SHIFT)
# define I2S_SERCTRL_SERMODE_RX (0 << I2S_SERCTRL_SERMODE_SHIFT)
# define I2S_SERCTRL_SERMODE_TX (1 << I2S_SERCTRL_SERMODE_SHIFT)
# define I2S_SERCTRL_SERMODE_PDM2 (2 << I2S_SERCTRL_SERMODE_SHIFT)
#define I2S_SERCTRL_TXDEFAULT_SHIFT (2) /* Bits [3:2]: Line Default when Slot Disabled */
#define I2S_SERCTRL_TXDEFAULT_MASK (3 << I2S_SERCTRL_TXDEFAULT_SHIFT)
# define I2S_SERCTRL_TXDEFAULT_ZERO (0 << I2S_SERCTRL_TXDEFAULT_SHIFT)
# define I2S_SERCTRL_TXDEFAULT_ONE (1 << I2S_SERCTRL_TXDEFAULT_SHIFT)
# define I2S_SERCTRL_TXDEFAULT_HIZ (3 << I2S_SERCTRL_TXDEFAULT_SHIFT)
#define I2S_SERCTRL_TXSAME (1 << 4) /* Bit 4: Transmit last data when Underrun */
#define I2S_SERCTRL_CLKSEL (1 << 5) /* Bit 5: Clock Unit Selection. 0: Use Clock 0, 1: Use Clock 1 */
#define I2S_SERCTRL_SLOTADJ (1 << 7) /* Bit 7: Data slot formatting. 0: Right justified, 1: Left justified */
#define I2S_SERCTRL_DATASIZE_SHIFT (8) /* Bits [10:8]: Data Word Size */
#define I2S_SERCTRL_DATASIZE_MASK (7 << I2S_SERCTRL_DATASIZE_SHIFT)
# define I2S_SERCTRL_DATASIZE_32 (0 << I2S_SERCTRL_DATASIZE_SHIFT)
# define I2S_SERCTRL_DATASIZE_24 (1 << I2S_SERCTRL_DATASIZE_SHIFT)
# define I2S_SERCTRL_DATASIZE_20 (2 << I2S_SERCTRL_DATASIZE_SHIFT)
# define I2S_SERCTRL_DATASIZE_18 (3 << I2S_SERCTRL_DATASIZE_SHIFT)
# define I2S_SERCTRL_DATASIZE_16 (4 << I2S_SERCTRL_DATASIZE_SHIFT)
# define I2S_SERCTRL_DATASIZE_16C (5 << I2S_SERCTRL_DATASIZE_SHIFT)
# define I2S_SERCTRL_DATASIZE_8 (6 << I2S_SERCTRL_DATASIZE_SHIFT)
# define I2S_SERCTRL_DATASIZE_8C (7 << I2S_SERCTRL_DATASIZE_SHIFT)
#define I2S_SERCTRL_WORDADJ (1 << 12) /* Bit 12: Data word formatting. 0: Right justified, 1: Left justified */
#define I2S_SERCTRL_EXTEND_SHIFT (13) /* Bits [14:13]: Data formatting bit extension */
#define I2S_SERCTRL_EXTEND_MASK (3 << I2S_SERCTRL_EXTEND_SHIFT)
# define I2S_SERCTRL_EXTEND_ZERO (0 << I2S_SERCTRL_EXTEND_SHIFT)
# define I2S_SERCTRL_EXTEND_ONE (1 << I2S_SERCTRL_EXTEND_SHIFT)
# define I2S_SERCTRL_EXTEND_MSBIT (2 << I2S_SERCTRL_EXTEND_SHIFT)
# define I2S_SERCTRL_EXTEND_LSBIT (3 << I2S_SERCTRL_EXTEND_SHIFT)
#define I2S_SERCTRL_BITREV (1 << 15) /* Bit 15: Data formatting bit reverse */
#define I2S_SERCTRL_SLOTDIS_SHIFT (16) /* Bits [23:16]: Slot x Disabled */
#define I2S_SERCTRL_SLOTDIS_MASK (0xff << I2S_SERCTRL_SLOTDIS_SHIFT)
#define I2S_SERCTRL_SLOTDIS(n) (((n) & 0xff) << I2C_SERCTRL_SLOTDIS_SHIFT)
#define I2S_SERCTRL_MONO (1 << 24) /* Bit 24: Mono Mode */
#define I2S_SERCTRL_DMA (1 << 25) /* Bit 25: Single or Multiple DMA channels */
#define I2S_SERCTRL_RXLOOP (1 << 26) /* Bit 26: RX Loopback Test Mode */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2S_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_nvmctrl.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_NVMCTRL_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_NVMCTRL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* NVMCTRL register offsets *************************************************/
#define SAM_NVMCTRL_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_NVMCTRL_CTRLB_OFFSET 0x0004 /* Control B register */
#define SAM_NVMCTRL_PARAM_OFFSET 0x0008 /* NVM parameter register */
#define SAM_NVMCTRL_INTENCLR_OFFSET 0x000c /* Interrupt clear register */
#define SAM_NVMCTRL_INTENSET_OFFSET 0x0010 /* Interrupt set register */
#define SAM_NVMCTRL_INTFLAG_OFFSET 0x0014 /* Interface flags status and clear register */
#define SAM_NVMCTRL_STATUS_OFFSET 0x0018 /* Status register */
#define SAM_NVMCTRL_ADDR_OFFSET 0x001c /* Address register */
#define SAM_NVMCTRL_LOCK_OFFSET 0x0020 /* Lock section register */
/* NVMCTRL register addresses ***********************************************/
#define SAM_NVMCTRL_CTRLA (SAM_NVMCTRL_BASE+SAM_NVMCTRL_CTRLA_OFFSET)
#define SAM_NVMCTRL_CTRLB (SAM_NVMCTRL_BASE+SAM_NVMCTRL_CTRLB_OFFSET)
#define SAM_NVMCTRL_PARAM (SAM_NVMCTRL_BASE+SAM_NVMCTRL_PARAM_OFFSET)
#define SAM_NVMCTRL_INTENCLR (SAM_NVMCTRL_BASE+SAM_NVMCTRL_INTENCLR_OFFSET)
#define SAM_NVMCTRL_INTENSET (SAM_NVMCTRL_BASE+SAM_NVMCTRL_INTENSET_OFFSET)
#define SAM_NVMCTRL_INTFLAG (SAM_NVMCTRL_BASE+SAM_NVMCTRL_INTFLAG_OFFSET)
#define SAM_NVMCTRL_STATUS (SAM_NVMCTRL_BASE+SAM_NVMCTRL_STATUS_OFFSET)
#define SAM_NVMCTRL_ADDR (SAM_NVMCTRL_BASE+SAM_NVMCTRL_ADDR_OFFSET)
#define SAM_NVMCTRL_LOCK (SAM_NVMCTRL_BASE+SAM_NVMCTRL_LOCK_OFFSET)
/* NVMCTRL register bit definitions *****************************************/
/* Control A register */
#define NVMCTRL_CTRLA_CMD_SHIFT (0) /* Bits 0-6: Command */
#define NVMCTRL_CTRLA_CMD_MASK (0x7f << NVMCTRL_CTRLA_CMD_SHIFT)
# define NVMCTRL_CTRLA_CMD_ER (0x02 << NVMCTRL_CTRLA_CMD_SHIFT) /* Erase Row */
# define NVMCTRL_CTRLA_CMD_WP (0x04 << NVMCTRL_CTRLA_CMD_SHIFT) /* Write Page */
# define NVMCTRL_CTRLA_CMD_EAR (0x05 << NVMCTRL_CTRLA_CMD_SHIFT) /* Erase Auxiliary Row */
# define NVMCTRL_CTRLA_CMD_WAP (0x06 << NVMCTRL_CTRLA_CMD_SHIFT) /* Write Auxiliary Page */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define NVMCTRL_CTRLA_CMD_SF (0x0a << NVMCTRL_CTRLA_CMD_SHIFT) /* Security Flow Command */
# define NVMCTRL_CTRLA_CMD_WL (0x0f << NVMCTRL_CTRLA_CMD_SHIFT) /* Write lockbits */
# define NVMCTRL_CTRLA_CMD_RWWEEER (0x1a << NVMCTRL_CTRLA_CMD_SHIFT) /* RWWEE Erase Row */
# define NVMCTRL_CTRLA_CMD_RWWEEEP (0x1c << NVMCTRL_CTRLA_CMD_SHIFT) /* RWWEE Write Page */
#endif
# define NVMCTRL_CTRLA_CMD_LR (0x40 << NVMCTRL_CTRLA_CMD_SHIFT) /* Lock Region */
# define NVMCTRL_CTRLA_CMD_UR (0x41 << NVMCTRL_CTRLA_CMD_SHIFT) /* Unlock Region */
# define NVMCTRL_CTRLA_CMD_SPRM (0x42 << NVMCTRL_CTRLA_CMD_SHIFT) /* Set power reduction mode */
# define NVMCTRL_CTRLA_CMD_CPRM (0x43 << NVMCTRL_CTRLA_CMD_SHIFT) /* Clear power reduction mode */
# define NVMCTRL_CTRLA_CMD_PBC (0x44 << NVMCTRL_CTRLA_CMD_SHIFT) /* Page Buffer Clear */
# define NVMCTRL_CTRLA_CMD_SSB (0x45 << NVMCTRL_CTRLA_CMD_SHIFT) /* Set Security Bit */
# define NVMCTRL_CTRLA_CMD_INVALL (0x46 << NVMCTRL_CTRLA_CMD_SHIFT) /* Invalidate all cache lines */
#define NVMCTRL_CTRLA_CMDEX_SHIFT (8) /* Bits 8-15: Command Execution */
#define NVMCTRL_CTRLA_CMDEX_MASK (0xff << NVMCTRL_CTRLA_CMDEX_SHIFT)
# define NVMCTRL_CTRLA_CMDEX (0xa5 << NVMCTRL_CTRLA_CMDEX_SHIFT)
/* Control B register */
#define NVMCTRL_CTRLB_RWS_SHIFT (1) /* Bits 1-4: NVM Read Wait States */
#define NVMCTRL_CTRLB_RWS_MASK (15 << NVMCTRL_CTRLB_RWS_SHIFT)
# define NVMCTRL_CTRLB_RWS(n) ((n) << NVMCTRL_CTRLB_RWS_SHIFT)
#define NVMCTRL_CTRLB_MANW (1 << 7) /* Bit 7: Manual Write */
#define NVMCTRL_CTRLB_SLEEPPRM_SHIFT (8) /* Bits 8-9: Power Reduction Mode during Sleep */
#define NVMCTRL_CTRLB_SLEEPPRM_MASK (3 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT)
# define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (0 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Exit low power on first access */
# define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (1 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Exit low power when exit sleep */
# define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (3 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Auto power reduction disabled */
#define NVMCTRL_CTRLB_READMODE_SHIFT (16) /* Bits 16-17: NVMCTRL Read Mode */
#define NVMCTRL_CTRLB_READMODE_MASK (3 << NVMCTRL_CTRLB_READMODE_SHIFT)
# define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (0 << NVMCTRL_CTRLB_READMODE_SHIFT) /* No extra wait states on miss */
# define NVMCTRL_CTRLB_READMODE_LOW_POWER (1 << NVMCTRL_CTRLB_READMODE_SHIFT) /* Insert wait/reduce power */
# define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (2 << NVMCTRL_CTRLB_READMODE_SHIFT) /* Same wait on all access */
#define NVMCTRL_CTRLB_CACHEDIS (1 << 18) /* Bit 18: Cache Disable */
/* NVM parameter register */
#define NVMCTRL_PARAM_NVMP_SHIFT (0) /* Bits 0-15: NVM Pages */
#define NVMCTRL_PARAM_NVMP_MASK (0xffff << NVMCTRL_PARAM_NVMP_SHIFT)
# define NVMCTRL_PARAM_NVMP(n) ((n) << NVMCTRL_PARAM_NVMP_SHIFT)
#define NVMCTRL_PARAM_PSZ_SHIFT (16) /* Bits 16-18: Page Size */
#define NVMCTRL_PARAM_PSZ_MASK (7 << NVMCTRL_PARAM_PSZ_SHIFT)
# define NVMCTRL_PARAM_PSZ_8B (0 << NVMCTRL_PARAM_PSZ_SHIFT) /* 8 bytes */
# define NVMCTRL_PARAM_PSZ_16B (1 << NVMCTRL_PARAM_PSZ_SHIFT) /* 16 bytes */
# define NVMCTRL_PARAM_PSZ_32B (2 << NVMCTRL_PARAM_PSZ_SHIFT) /* 32 bytes */
# define NVMCTRL_PARAM_PSZ_64B (3 << NVMCTRL_PARAM_PSZ_SHIFT) /* 64 bytes */
# define NVMCTRL_PARAM_PSZ_128B (4 << NVMCTRL_PARAM_PSZ_SHIFT) /* 128 bytes */
# define NVMCTRL_PARAM_PSZ_256B (5 << NVMCTRL_PARAM_PSZ_SHIFT) /* 256 bytes */
# define NVMCTRL_PARAM_PSZ_512B (6 << NVMCTRL_PARAM_PSZ_SHIFT) /* 512 bytes */
# define NVMCTRL_PARAM_PSZ_1KB (7 << NVMCTRL_PARAM_PSZ_SHIFT) /* 1024 bytes */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define NVMCTRL_PARAM_RWWEEP_SHIFT (20) /* Bits 20-31: Read while write EEPROM emulation area pages */
# define NVMCTRL_PARAM_RWWEEP_MASK (0xfff << NVMCTRL_PARAM_RWWEEP_SHIFT)
#endif
/* Interrupt clear register */
/* Interrupt set register */
/* Interface flags status and clear register */
#define NVMCTRL_INT_READY (1 << 0) /* Bit 0: NVM Ready Interrupt */
#define NVMCTRL_INT_ERROR (1 << 1) /* Bit 1: Error Interrupt */
/* Status register */
#define NVMCTRL_STATUS_PRM (1 << 0) /* Bit 0: Power Reduction Mode */
#define NVMCTRL_STATUS_LOAD (1 << 1) /* Bit 1: NVM Page Buffer Active Loading */
#define NVMCTRL_STATUS_PROGE (1 << 2) /* Bit 2: Programming Error Status */
#define NVMCTRL_STATUS_LOCKE (1 << 3) /* Bit 3: Lock Error Status */
#define NVMCTRL_STATUS_NVME (1 << 4) /* Bit 4: NVM Error */
#define NVMCTRL_STATUS_SB (1 << 8) /* Bit 8: Security Bit Status */
/* Address register */
#define NVMCTRL_ADDR_MASK (0x003fffff) /* Bits 0-21: NVM Address */
/* Lock section register */
#define NVMCTRL_LOCK_REGION(n) (1 << (n)) /* Region n is locked */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_NVMCTRL_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_pm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PM_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* PM register offsets ******************************************************/
#define SAM_PM_CTRL_OFFSET 0x0000 /* Control register */
#define SAM_PM_SLEEP_OFFSET 0x0001 /* Sleep mode register */
#define SAM_PM_CPUSEL_OFFSET 0x0008 /* CPU clock select register */
#define SAM_PM_APBASEL_OFFSET 0x0009 /* APBA clock select register */
#define SAM_PM_APBBSEL_OFFSET 0x000a /* APBB clock select register */
#define SAM_PM_APBCSEL_OFFSET 0x000b /* APBC clock select register */
#define SAM_PM_AHBMASK_OFFSET 0x0014 /* AHB mask register */
#define SAM_PM_APBAMASK_OFFSET 0x0018 /* APBA mask register */
#define SAM_PM_APBBMASK_OFFSET 0x001c /* APBB mask register */
#define SAM_PM_APBCMASK_OFFSET 0x0020 /* APBC mask register */
#define SAM_PM_INTENCLR_OFFSET 0x0034 /* Interrupt enable clear register */
#define SAM_PM_INTENSET_OFFSET 0x0035 /* Interrupt enable set register */
#define SAM_PM_INTFLAG_OFFSET 0x0036 /* Interrupt flag status and clear register */
#define SAM_PM_RCAUSE_OFFSET 0x0038 /* Reset cause register */
/* PM register addresses ****************************************************/
#define SAM_PM_CTRL (SAM_PM_BASE+SAM_PM_CTRL_OFFSET)
#define SAM_PM_SLEEP (SAM_PM_BASE+SAM_PM_SLEEP_OFFSET)
#define SAM_PM_CPUSEL (SAM_PM_BASE+SAM_PM_CPUSEL_OFFSET)
#define SAM_PM_APBASEL (SAM_PM_BASE+SAM_PM_APBASEL_OFFSET)
#define SAM_PM_APBBSEL (SAM_PM_BASE+SAM_PM_APBBSEL_OFFSET)
#define SAM_PM_APBCSEL (SAM_PM_BASE+SAM_PM_APBCSEL_OFFSET)
#define SAM_PM_AHBMASK (SAM_PM_BASE+SAM_PM_AHBMASK_OFFSET)
#define SAM_PM_APBAMASK (SAM_PM_BASE+SAM_PM_APBAMASK_OFFSET)
#define SAM_PM_APBBMASK (SAM_PM_BASE+SAM_PM_APBBMASK_OFFSET)
#define SAM_PM_APBCMASK (SAM_PM_BASE+SAM_PM_APBCMASK_OFFSET)
#define SAM_PM_INTENCLR (SAM_PM_BASE+SAM_PM_INTENCLR_OFFSET)
#define SAM_PM_INTENSET (SAM_PM_BASE+SAM_PM_INTENSET_OFFSET)
#define SAM_PM_INTFLAG (SAM_PM_BASE+SAM_PM_INTFLAG_OFFSET)
#define SAM_PM_RCAUSE (SAM_PM_BASE+SAM_PM_RCAUSE_OFFSET)
/* PM register bit definitions **********************************************/
/* Control register */
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define PM_CTRL_CFDEN (1 << 2) /* Bit 2: Clock Failure Detector Enable */
# define PM_CTRL_BKUPCLK (1 << 4) /* Bit 4: Backup Clock Select */
#endif
/* Sleep mode register */
#define PM_SLEEP_IDLE_SHIFT (0) /* Bits 0-1: Idle Mode Configuration */
#define PM_SLEEP_IDLE_MASK (3 << PM_SLEEP_IDLE_SHIFT)
# define PM_SLEEP_IDLE_CPU (0 << PM_SLEEP_IDLE_SHIFT) /* CPU clock domain stopped */
# define PM_SLEEP_IDLE_CPUAHB (1 << PM_SLEEP_IDLE_SHIFT) /* CPU and AHB clock domains stopped */
# define PM_SLEEP_IDLE_CPUAHBAPB (2 << PM_SLEEP_IDLE_SHIFT) /* CPU, AHB, and APB clock domains stopped */
/* CPU clock select register */
#define PM_CPUSEL_CPUDIV_SHIFT (0) /* Bits 0-2: CPU Prescaler Selection */
#define PM_CPUSEL_CPUDIV_MASK (7 << PM_CPUSEL_CPUDIV_SHIFT)
# define PM_CPUSEL_CPUDIV_1 (0 << PM_CPUSEL_CPUDIV_SHIFT) /* Divide by 1 */
# define PM_CPUSEL_CPUDIV_2 (1 << PM_CPUSEL_CPUDIV_SHIFT) /* Divide by 2 */
# define PM_CPUSEL_CPUDIV_4 (2 << PM_CPUSEL_CPUDIV_SHIFT) /* Divide by 4 */
# define PM_CPUSEL_CPUDIV_8 (3 << PM_CPUSEL_CPUDIV_SHIFT) /* Divide by 8 */
# define PM_CPUSEL_CPUDIV_16 (4 << PM_CPUSEL_CPUDIV_SHIFT) /* Divide by 16 */
# define PM_CPUSEL_CPUDIV_32 (5 << PM_CPUSEL_CPUDIV_SHIFT) /* Divide by 32 */
# define PM_CPUSEL_CPUDIV_64 (6 << PM_CPUSEL_CPUDIV_SHIFT) /* Divide by 64 */
# define PM_CPUSEL_CPUDIV_128 (7 << PM_CPUSEL_CPUDIV_SHIFT) /* Divide by 128 */
/* APBA clock select register */
#define PM_APBASEL_APBADIV_SHIFT (0) /* Bits 0-2: APBA Prescaler Selection */
#define PM_APBASEL_APBADIV_MASK (7 << PM_APBASEL_APBADIV_SHIFT)
# define PM_APBASEL_APBADIV_1 (0 << PM_APBASEL_APBADIV_SHIFT) /* Divide by 1 */
# define PM_APBASEL_APBADIV_2 (1 << PM_APBASEL_APBADIV_SHIFT) /* Divide by 2 */
# define PM_APBASEL_APBADIV_4 (2 << PM_APBASEL_APBADIV_SHIFT) /* Divide by 4 */
# define PM_APBASEL_APBADIV_8 (3 << PM_APBASEL_APBADIV_SHIFT) /* Divide by 8 */
# define PM_APBASEL_APBADIV_16 (4 << PM_APBASEL_APBADIV_SHIFT) /* Divide by 16 */
# define PM_APBASEL_APBADIV_32 (5 << PM_APBASEL_APBADIV_SHIFT) /* Divide by 32 */
# define PM_APBASEL_APBADIV_64 (6 << PM_APBASEL_APBADIV_SHIFT) /* Divide by 64 */
# define PM_APBASEL_APBADIV_128 (7 << PM_APBASEL_APBADIV_SHIFT) /* Divide by 128 */
/* APBB clock select register */
#define PM_APBBSEL_APBBDIV_SHIFT (0) /* Bits 0-2: APBB Prescaler Selection */
#define PM_APBBSEL_APBBDIV_MASK (7 << PM_APBBSEL_APBBDIV_SHIFT)
# define PM_APBBSEL_APBBDIV_1 (0 << PM_APBBSEL_APBBDIV_SHIFT) /* Divide by 1 */
# define PM_APBBSEL_APBBDIV_2 (1 << PM_APBBSEL_APBBDIV_SHIFT) /* Divide by 2 */
# define PM_APBBSEL_APBBDIV_4 (2 << PM_APBBSEL_APBBDIV_SHIFT) /* Divide by 4 */
# define PM_APBBSEL_APBBDIV_8 (3 << PM_APBBSEL_APBBDIV_SHIFT) /* Divide by 8 */
# define PM_APBBSEL_APBBDIV_16 (4 << PM_APBBSEL_APBBDIV_SHIFT) /* Divide by 16 */
# define PM_APBBSEL_APBBDIV_32 (5 << PM_APBBSEL_APBBDIV_SHIFT) /* Divide by 32 */
# define PM_APBBSEL_APBBDIV_64 (6 << PM_APBBSEL_APBBDIV_SHIFT) /* Divide by 64 */
# define PM_APBBSEL_APBBDIV_128 (7 << PM_APBBSEL_APBBDIV_SHIFT) /* Divide by 128 */
/* APBC clock select register */
#define PM_APBCSEL_APBCDIV_SHIFT (0) /* Bits 0-2: APBC Prescaler Selection */
#define PM_APBCSEL_APBCDIV_MASK (7 << PM_APBCSEL_APBCDIV_SHIFT)
# define PM_APBCSEL_APBCDIV_1 (0 << PM_APBCSEL_APBCDIV_SHIFT) /* Divide by 1 */
# define PM_APBCSEL_APBCDIV_2 (1 << PM_APBCSEL_APBCDIV_SHIFT) /* Divide by 2 */
# define PM_APBCSEL_APBCDIV_4 (2 << PM_APBCSEL_APBCDIV_SHIFT) /* Divide by 4 */
# define PM_APBCSEL_APBCDIV_8 (3 << PM_APBCSEL_APBCDIV_SHIFT) /* Divide by 8 */
# define PM_APBCSEL_APBCDIV_16 (4 << PM_APBCSEL_APBCDIV_SHIFT) /* Divide by 16 */
# define PM_APBCSEL_APBCDIV_32 (5 << PM_APBCSEL_APBCDIV_SHIFT) /* Divide by 32 */
# define PM_APBCSEL_APBCDIV_64 (6 << PM_APBCSEL_APBCDIV_SHIFT) /* Divide by 64 */
# define PM_APBCSEL_APBCDIV_128 (7 << PM_APBCSEL_APBCDIV_SHIFT) /* Divide by 128 */
/* AHB mask register */
#define PM_AHBMASK_HPB0 (1 << 0) /* Bit 0: HPB0 */
#define PM_AHBMASK_HPB1 (1 << 1) /* Bit 1: HPB1 */
#define PM_AHBMASK_HPB2 (1 << 2) /* Bit 2: HPB2 */
#define PM_AHBMASK_DSU (1 << 3) /* Bit 3: DSU */
#define PM_AHBMASK_NVMCTRL (1 << 4) /* Bit 4: NVMCTRL */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define PM_AHBMASK_DMAC (1 << 5) /* Bit 4: DMA controller */
# define PM_AHBMASK_USB (1 << 6) /* Bit 4: USB */
#endif
/* APBA mask register */
#define PM_APBAMASK_PAC0 (1 << 0) /* Bit 0: PAC0 */
#define PM_APBAMASK_PM (1 << 1) /* Bit 1: PM */
#define PM_APBAMASK_SYSCTRL (1 << 2) /* Bit 2: SYSCTRL */
#define PM_APBAMASK_GCLK (1 << 3) /* Bit 3: GCLK */
#define PM_APBAMASK_WDT (1 << 4) /* Bit 4: WDT */
#define PM_APBAMASK_RTC (1 << 5) /* Bit 5: RTC */
#define PM_APBAMASK_EIC (1 << 6) /* Bit 6: EIC */
/* APBB mask register */
#define PM_APBBMASK_PAC1 (1 << 0) /* Bit 0: PAC1 */
#define PM_APBBMASK_DSU (1 << 1) /* Bit 1: DSU */
#define PM_APBBMASK_NVMCTRL (1 << 2) /* Bit 2: NVMCTRL */
#define PM_APBBMASK_PORT (1 << 3) /* Bit 3: PORT */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define PM_APBBMASK_DMAC (1 << 4) /* Bit 4: DMA controller */
# define PM_APBBMASK_USB (1 << 5) /* Bit 5: USB */
#endif
/* APBC mask register */
#define PM_APBCMASK_PAC2 (1 << 0) /* Bit 0: PAC2 */
#define PM_APBCMASK_EVSYS (1 << 1) /* Bit 1: EVSYS */
#define PM_APBCMASK_SERCOM(n) (1 << ((n)+2))
# define PM_APBCMASK_SERCOM0 (1 << 2) /* Bit 2: SERCOM0 */
# define PM_APBCMASK_SERCOM1 (1 << 3) /* Bit 3: SERCOM1 */
# define PM_APBCMASK_SERCOM2 (1 << 4) /* Bit 4: SERCOM2 */
# define PM_APBCMASK_SERCOM3 (1 << 5) /* Bit 5: SERCOM3 */
# define PM_APBCMASK_SERCOM4 (1 << 6) /* Bit 6: SERCOM4 */
# define PM_APBCMASK_SERCOM5 (1 << 7) /* Bit 7: SERCOM5 */
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define PM_APBCMASK_TC0 (1 << 8) /* Bit 8: TC0 */
# define PM_APBCMASK_TC1 (1 << 9) /* Bit 9: TC1 */
# define PM_APBCMASK_TC2 (1 << 10) /* Bit 10: TC2 */
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define PM_APBCMASK_TCC0 (1 << 8) /* Bit 8: TCC0 */
# define PM_APBCMASK_TCC1 (1 << 9) /* Bit 9: TCC1 */
# define PM_APBCMASK_TCC2 (1 << 10) /* Bit 10: TCC2 */
#endif
#define PM_APBCMASK_TC3 (1 << 11) /* Bit 11: TC3 */
#define PM_APBCMASK_TC4 (1 << 12) /* Bit 12: TC4 */
#define PM_APBCMASK_TC5 (1 << 13) /* Bit 13: TC5 */
#define PM_APBCMASK_TC6 (1 << 14) /* Bit 14: TC6 */
#define PM_APBCMASK_TC7 (1 << 15) /* Bit 15: TC7 */
#define PM_APBCMASK_ADC (1 << 16) /* Bit 16: ADC */
#define PM_APBCMASK_AC (1 << 17) /* Bit 17: AC */
#define PM_APBCMASK_DAC (1 << 18) /* Bit 18: DAC */
#define PM_APBCMASK_PTC (1 << 19) /* Bit 19: PTC */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define PM_APBCMASK_I2S (1 << 20) /* Bit 20: Inter IC Sound */
#endif
/* Interrupt enable clear, Interrupt enable set,
* and Interrupt flag status and clear registers
*/
#define PM_INT_CKRDY (1 << 0) /* Bit 0: Clock Ready Interrupt */
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define PM_INT_CFD (1 << 1) /* Bit 1: Clock Failure Detector Interrupt */
#endif
/* Reset cause register */
#define PM_RCAUSE_POR (1 << 0) /* Bit 0: Power-On Reset */
#define PM_RCAUSE_BOD12 (1 << 1) /* Bit 1: Brown Out 12 Detector Reset */
#define PM_RCAUSE_BOD33 (1 << 2) /* Bit 2: Brown Out 33 Detector Reset */
#define PM_RCAUSE_EXT (1 << 4) /* Bit 4: External Reset */
#define PM_RCAUSE_WDT (1 << 5) /* Bit 5: Watchdog Reset */
#define PM_RCAUSE_SYST (1 << 6) /* Bit 6: System Reset Request */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PM_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_port.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PORT_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PORT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* PORT register offsets ****************************************************/
#define SAM_PORTA (0)
#define SAM_PORTB (1)
#define SAM_PORTN_OFFSET(n) (0x0000 + ((n) << 7))
#define SAM_PORTA_OFFSET 0x0000 /* Port A register offset */
#define SAM_PORTB_OFFSET 0x0080 /* Port B register offset */
#define SAM_PORT_DIR_OFFSET 0x0000 /* Data direction register */
#define SAM_PORT_DIRCLR_OFFSET 0x0004 /* Data direction clear register */
#define SAM_PORT_DIRSET_OFFSET 0x0008 /* Data direction set register */
#define SAM_PORT_DIRTGL_OFFSET 0x000c /* Data direction toggle register */
#define SAM_PORT_OUT_OFFSET 0x0010 /* Data output value register */
#define SAM_PORT_OUTCLR_OFFSET 0x0014 /* Data output value clear register */
#define SAM_PORT_OUTSET_OFFSET 0x0018 /* Data output value set register */
#define SAM_PORT_OUTTGL_OFFSET 0x001c /* Data output value toggle register */
#define SAM_PORT_IN_OFFSET 0x0020 /* Data input value register */
#define SAM_PORT_CTRL_OFFSET 0x0024 /* Control register */
#define SAM_PORT_WRCONFIG_OFFSET 0x0028 /* Write configuration registers */
#define SAM_PORT_PMUX_OFFSET(n) (0x0030+((n)>>1))
#define SAM_PORT_PMUX0_OFFSET 0x0030 /* Peripheral multiplexing register 0 */
#define SAM_PORT_PMUX1_OFFSET 0x0031 /* Peripheral multiplexing register 1 */
#define SAM_PORT_PMUX2_OFFSET 0x0032 /* Peripheral multiplexing register 2 */
#define SAM_PORT_PMUX3_OFFSET 0x0033 /* Peripheral multiplexing register 3 */
#define SAM_PORT_PMUX4_OFFSET 0x0034 /* Peripheral multiplexing register 4 */
#define SAM_PORT_PMUX5_OFFSET 0x0035 /* Peripheral multiplexing register 5 */
#define SAM_PORT_PMUX6_OFFSET 0x0036 /* Peripheral multiplexing register 6 */
#define SAM_PORT_PMUX7_OFFSET 0x0037 /* Peripheral multiplexing register 7 */
#define SAM_PORT_PMUX8_OFFSET 0x0038 /* Peripheral multiplexing register 8 */
#define SAM_PORT_PMUX9_OFFSET 0x0039 /* Peripheral multiplexing register 9 */
#define SAM_PORT_PMUX10_OFFSET 0x003a /* Peripheral multiplexing register 10 */
#define SAM_PORT_PMUX11_OFFSET 0x003b /* Peripheral multiplexing register 11 */
#define SAM_PORT_PMUX12_OFFSET 0x003c /* Peripheral multiplexing register 12 */
#define SAM_PORT_PMUX13_OFFSET 0x003d /* Peripheral multiplexing register 13 */
#define SAM_PORT_PMUX14_OFFSET 0x003e /* Peripheral multiplexing register 14 */
#define SAM_PORT_PMUX15_OFFSET 0x003f /* Peripheral multiplexing register 15 */
#define SAM_PORT_PINCFG_OFFSET(n) (0x0040+(n))
#define SAM_PORT_PINCFG0_OFFSET 0x0040 /* Pin configuration register 0 */
#define SAM_PORT_PINCFG1_OFFSET 0x0041 /* Pin configuration register 1 */
#define SAM_PORT_PINCFG2_OFFSET 0x0042 /* Pin configuration register 2 */
#define SAM_PORT_PINCFG3_OFFSET 0x0043 /* Pin configuration register 3 */
#define SAM_PORT_PINCFG4_OFFSET 0x0044 /* Pin configuration register 4 */
#define SAM_PORT_PINCFG5_OFFSET 0x0045 /* Pin configuration register 5 */
#define SAM_PORT_PINCFG6_OFFSET 0x0046 /* Pin configuration register 6 */
#define SAM_PORT_PINCFG7_OFFSET 0x0047 /* Pin configuration register 7 */
#define SAM_PORT_PINCFG8_OFFSET 0x0048 /* Pin configuration register 8 */
#define SAM_PORT_PINCFG9_OFFSET 0x0049 /* Pin configuration register 9 */
#define SAM_PORT_PINCFG10_OFFSET 0x004a /* Pin configuration register 10 */
#define SAM_PORT_PINCFG11_OFFSET 0x004b /* Pin configuration register 11 */
#define SAM_PORT_PINCFG12_OFFSET 0x004c /* Pin configuration register 12 */
#define SAM_PORT_PINCFG13_OFFSET 0x004d /* Pin configuration register 13 */
#define SAM_PORT_PINCFG14_OFFSET 0x004e /* Pin configuration register 14 */
#define SAM_PORT_PINCFG15_OFFSET 0x004f /* Pin configuration register 15 */
#define SAM_PORT_PINCFG16_OFFSET 0x0050 /* Pin configuration register 16 */
#define SAM_PORT_PINCFG17_OFFSET 0x0051 /* Pin configuration register 17 */
#define SAM_PORT_PINCFG18_OFFSET 0x0052 /* Pin configuration register 18 */
#define SAM_PORT_PINCFG19_OFFSET 0x0053 /* Pin configuration register 19 */
#define SAM_PORT_PINCFG20_OFFSET 0x0054 /* Pin configuration register 20 */
#define SAM_PORT_PINCFG21_OFFSET 0x0055 /* Pin configuration register 21 */
#define SAM_PORT_PINCFG22_OFFSET 0x0056 /* Pin configuration register 22 */
#define SAM_PORT_PINCFG23_OFFSET 0x0057 /* Pin configuration register 23 */
#define SAM_PORT_PINCFG24_OFFSET 0x0058 /* Pin configuration register 24 */
#define SAM_PORT_PINCFG25_OFFSET 0x0059 /* Pin configuration register 25 */
#define SAM_PORT_PINCFG26_OFFSET 0x005a /* Pin configuration register 26 */
#define SAM_PORT_PINCFG27_OFFSET 0x005b /* Pin configuration register 27 */
#define SAM_PORT_PINCFG28_OFFSET 0x005c /* Pin configuration register 28 */
#define SAM_PORT_PINCFG29_OFFSET 0x005d /* Pin configuration register 29 */
#define SAM_PORT_PINCFG30_OFFSET 0x005e /* Pin configuration register 30 */
#define SAM_PORT_PINCFG31_OFFSET 0x005f /* Pin configuration register 31 */
/* PORT register addresses **************************************************/
#define SAM_PORTN_BASE(n) (SAM_PORT_BASE+SAM_PORTN_OFFSET(n))
#define SAM_PORTA_BASE (SAM_PORT_BASE+SAM_PORTA_OFFSET)
#define SAM_PORTB_BASE (SAM_PORT_BASE+SAM_PORTB_OFFSET)
#define SAM_PORTA_DIR (SAM_PORTA_BASE+SAM_PORT_DIR_OFFSET)
#define SAM_PORTA_DIRCLR (SAM_PORTA_BASE+SAM_PORT_DIRCLR_OFFSET)
#define SAM_PORTA_DIRSET (SAM_PORTA_BASE+SAM_PORT_DIRSET_OFFSET)
#define SAM_PORTA_DIRTGL (SAM_PORTA_BASE+SAM_PORT_DIRTGL_OFFSET)
#define SAM_PORTA_OUT (SAM_PORTA_BASE+SAM_PORT_OUT_OFFSET)
#define SAM_PORTA_OUTCLR (SAM_PORTA_BASE+SAM_PORT_OUTCLR_OFFSET)
#define SAM_PORTA_OUTSET (SAM_PORTA_BASE+SAM_PORT_OUTSET_OFFSET)
#define SAM_PORTA_OUTTGL (SAM_PORTA_BASE+SAM_PORT_OUTTGL_OFFSET)
#define SAM_PORTA_IN (SAM_PORTA_BASE+SAM_PORT_IN_OFFSET)
#define SAM_PORTA_CTRL (SAM_PORTA_BASE+SAM_PORT_CTRL_OFFSET)
#define SAM_PORTA_WRCONFIG (SAM_PORTA_BASE+SAM_PORT_WRCONFIG_OFFSET)
#define SAM_PORTA_PMUX(n) (SAM_PORTA_BASE+SAM_PORT_PMUX_OFFSET(n))
#define SAM_PORTA_PMUX0 (SAM_PORTA_BASE+SAM_PORT_PMUX0_OFFSET)
#define SAM_PORTA_PMUX1 (SAM_PORTA_BASE+SAM_PORT_PMUX1_OFFSET)
#define SAM_PORTA_PMUX2 (SAM_PORTA_BASE+SAM_PORT_PMUX2_OFFSET)
#define SAM_PORTA_PMUX3 (SAM_PORTA_BASE+SAM_PORT_PMUX3_OFFSET)
#define SAM_PORTA_PMUX4 (SAM_PORTA_BASE+SAM_PORT_PMUX4_OFFSET)
#define SAM_PORTA_PMUX5 (SAM_PORTA_BASE+SAM_PORT_PMUX5_OFFSET)
#define SAM_PORTA_PMUX6 (SAM_PORTA_BASE+SAM_PORT_PMUX6_OFFSET)
#define SAM_PORTA_PMUX7 (SAM_PORTA_BASE+SAM_PORT_PMUX7_OFFSET)
#define SAM_PORTA_PMUX8 (SAM_PORTA_BASE+SAM_PORT_PMUX8_OFFSET)
#define SAM_PORTA_PMUX9 (SAM_PORTA_BASE+SAM_PORT_PMUX9_OFFSET)
#define SAM_PORTA_PMUX10 (SAM_PORTA_BASE+SAM_PORT_PMUX10_OFFSET)
#define SAM_PORTA_PMUX11 (SAM_PORTA_BASE+SAM_PORT_PMUX11_OFFSET)
#define SAM_PORTA_PMUX12 (SAM_PORTA_BASE+SAM_PORT_PMUX12_OFFSET)
#define SAM_PORTA_PMUX13 (SAM_PORTA_BASE+SAM_PORT_PMUX13_OFFSET)
#define SAM_PORTA_PMUX14 (SAM_PORTA_BASE+SAM_PORT_PMUX14_OFFSET)
#define SAM_PORTA_PMUX15 (SAM_PORTA_BASE+SAM_PORT_PMUX15_OFFSET)
#define SAM_PORTA_PINCFG(n) (SAM_PORTA_BASE+SAM_PORT_PINCFG_OFFSET(n))
#define SAM_PORTA_PINCFG0 (SAM_PORTA_BASE+SAM_PORT_PINCFG0_OFFSET)
#define SAM_PORTA_PINCFG1 (SAM_PORTA_BASE+SAM_PORT_PINCFG1_OFFSET)
#define SAM_PORTA_PINCFG2 (SAM_PORTA_BASE+SAM_PORT_PINCFG2_OFFSET)
#define SAM_PORTA_PINCFG3 (SAM_PORTA_BASE+SAM_PORT_PINCFG3_OFFSET)
#define SAM_PORTA_PINCFG4 (SAM_PORTA_BASE+SAM_PORT_PINCFG4_OFFSET)
#define SAM_PORTA_PINCFG5 (SAM_PORTA_BASE+SAM_PORT_PINCFG5_OFFSET)
#define SAM_PORTA_PINCFG6 (SAM_PORTA_BASE+SAM_PORT_PINCFG6_OFFSET)
#define SAM_PORTA_PINCFG7 (SAM_PORTA_BASE+SAM_PORT_PINCFG7_OFFSET)
#define SAM_PORTA_PINCFG8 (SAM_PORTA_BASE+SAM_PORT_PINCFG8_OFFSET)
#define SAM_PORTA_PINCFG9 (SAM_PORTA_BASE+SAM_PORT_PINCFG9_OFFSET)
#define SAM_PORTA_PINCFG10 (SAM_PORTA_BASE+SAM_PORT_PINCFG10_OFFSET)
#define SAM_PORTA_PINCFG11 (SAM_PORTA_BASE+SAM_PORT_PINCFG11_OFFSET)
#define SAM_PORTA_PINCFG12 (SAM_PORTA_BASE+SAM_PORT_PINCFG12_OFFSET)
#define SAM_PORTA_PINCFG13 (SAM_PORTA_BASE+SAM_PORT_PINCFG13_OFFSET)
#define SAM_PORTA_PINCFG14 (SAM_PORTA_BASE+SAM_PORT_PINCFG14_OFFSET)
#define SAM_PORTA_PINCFG15 (SAM_PORTA_BASE+SAM_PORT_PINCFG15_OFFSET)
#define SAM_PORTA_PINCFG16 (SAM_PORTA_BASE+SAM_PORT_PINCFG16_OFFSET)
#define SAM_PORTA_PINCFG17 (SAM_PORTA_BASE+SAM_PORT_PINCFG17_OFFSET)
#define SAM_PORTA_PINCFG18 (SAM_PORTA_BASE+SAM_PORT_PINCFG18_OFFSET)
#define SAM_PORTA_PINCFG19 (SAM_PORTA_BASE+SAM_PORT_PINCFG19_OFFSET)
#define SAM_PORTA_PINCFG20 (SAM_PORTA_BASE+SAM_PORT_PINCFG20_OFFSET)
#define SAM_PORTA_PINCFG21 (SAM_PORTA_BASE+SAM_PORT_PINCFG21_OFFSET)
#define SAM_PORTA_PINCFG22 (SAM_PORTA_BASE+SAM_PORT_PINCFG22_OFFSET)
#define SAM_PORTA_PINCFG23 (SAM_PORTA_BASE+SAM_PORT_PINCFG23_OFFSET)
#define SAM_PORTA_PINCFG24 (SAM_PORTA_BASE+SAM_PORT_PINCFG24_OFFSET)
#define SAM_PORTA_PINCFG25 (SAM_PORTA_BASE+SAM_PORT_PINCFG25_OFFSET)
#define SAM_PORTA_PINCFG26 (SAM_PORTA_BASE+SAM_PORT_PINCFG26_OFFSET)
#define SAM_PORTA_PINCFG27 (SAM_PORTA_BASE+SAM_PORT_PINCFG27_OFFSET)
#define SAM_PORTA_PINCFG28 (SAM_PORTA_BASE+SAM_PORT_PINCFG28_OFFSET)
#define SAM_PORTA_PINCFG29 (SAM_PORTA_BASE+SAM_PORT_PINCFG29_OFFSET)
#define SAM_PORTA_PINCFG30 (SAM_PORTA_BASE+SAM_PORT_PINCFG30_OFFSET)
#define SAM_PORTA_PINCFG31 (SAM_PORTA_BASE+SAM_PORT_PINCFG31_OFFSET)
#define SAM_PORTB_DIR (SAM_PORTB_BASE+SAM_PORT_DIR_OFFSET)
#define SAM_PORTB_DIRCLR (SAM_PORTB_BASE+SAM_PORT_DIRCLR_OFFSET)
#define SAM_PORTB_DIRSET (SAM_PORTB_BASE+SAM_PORT_DIRSET_OFFSET)
#define SAM_PORTB_DIRTGL (SAM_PORTB_BASE+SAM_PORT_DIRTGL_OFFSET)
#define SAM_PORTB_OUT (SAM_PORTB_BASE+SAM_PORT_OUT_OFFSET)
#define SAM_PORTB_OUTCLR (SAM_PORTB_BASE+SAM_PORT_OUTCLR_OFFSET)
#define SAM_PORTB_OUTSET (SAM_PORTB_BASE+SAM_PORT_OUTSET_OFFSET)
#define SAM_PORTB_OUTTGL (SAM_PORTB_BASE+SAM_PORT_OUTTGL_OFFSET)
#define SAM_PORTB_IN (SAM_PORTB_BASE+SAM_PORT_IN_OFFSET)
#define SAM_PORTB_CTRL (SAM_PORTB_BASE+SAM_PORT_CTRL_OFFSET)
#define SAM_PORTB_WRCONFIG (SAM_PORTB_BASE+SAM_PORT_WRCONFIG_OFFSET)
#define SAM_PORTB_PMUX(n) (SAM_PORTB_BASE+SAM_PORT_PMUX_OFFSET(n))
#define SAM_PORTB_PMUX0 (SAM_PORTB_BASE+SAM_PORT_PMUX0_OFFSET)
#define SAM_PORTB_PMUX1 (SAM_PORTB_BASE+SAM_PORT_PMUX1_OFFSET)
#define SAM_PORTB_PMUX2 (SAM_PORTB_BASE+SAM_PORT_PMUX2_OFFSET)
#define SAM_PORTB_PMUX3 (SAM_PORTB_BASE+SAM_PORT_PMUX3_OFFSET)
#define SAM_PORTB_PMUX4 (SAM_PORTB_BASE+SAM_PORT_PMUX4_OFFSET)
#define SAM_PORTB_PMUX5 (SAM_PORTB_BASE+SAM_PORT_PMUX5_OFFSET)
#define SAM_PORTB_PMUX6 (SAM_PORTB_BASE+SAM_PORT_PMUX6_OFFSET)
#define SAM_PORTB_PMUX7 (SAM_PORTB_BASE+SAM_PORT_PMUX7_OFFSET)
#define SAM_PORTB_PMUX8 (SAM_PORTB_BASE+SAM_PORT_PMUX8_OFFSET)
#define SAM_PORTB_PMUX9 (SAM_PORTB_BASE+SAM_PORT_PMUX9_OFFSET)
#define SAM_PORTB_PMUX10 (SAM_PORTB_BASE+SAM_PORT_PMUX10_OFFSET)
#define SAM_PORTB_PMUX11 (SAM_PORTB_BASE+SAM_PORT_PMUX11_OFFSET)
#define SAM_PORTB_PMUX12 (SAM_PORTB_BASE+SAM_PORT_PMUX12_OFFSET)
#define SAM_PORTB_PMUX13 (SAM_PORTB_BASE+SAM_PORT_PMUX13_OFFSET)
#define SAM_PORTB_PMUX14 (SAM_PORTB_BASE+SAM_PORT_PMUX14_OFFSET)
#define SAM_PORTB_PMUX15 (SAM_PORTB_BASE+SAM_PORT_PMUX15_OFFSET)
#define SAM_PORTB_PINCFG(n) (SAM_PORTB_BASE+SAM_PORT_PINCFG_OFFSET(n))
#define SAM_PORTB_PINCFG0 (SAM_PORTB_BASE+SAM_PORT_PINCFG0_OFFSET)
#define SAM_PORTB_PINCFG1 (SAM_PORTB_BASE+SAM_PORT_PINCFG1_OFFSET)
#define SAM_PORTB_PINCFG2 (SAM_PORTB_BASE+SAM_PORT_PINCFG2_OFFSET)
#define SAM_PORTB_PINCFG3 (SAM_PORTB_BASE+SAM_PORT_PINCFG3_OFFSET)
#define SAM_PORTB_PINCFG4 (SAM_PORTB_BASE+SAM_PORT_PINCFG4_OFFSET)
#define SAM_PORTB_PINCFG5 (SAM_PORTB_BASE+SAM_PORT_PINCFG5_OFFSET)
#define SAM_PORTB_PINCFG6 (SAM_PORTB_BASE+SAM_PORT_PINCFG6_OFFSET)
#define SAM_PORTB_PINCFG7 (SAM_PORTB_BASE+SAM_PORT_PINCFG7_OFFSET)
#define SAM_PORTB_PINCFG8 (SAM_PORTB_BASE+SAM_PORT_PINCFG8_OFFSET)
#define SAM_PORTB_PINCFG9 (SAM_PORTB_BASE+SAM_PORT_PINCFG9_OFFSET)
#define SAM_PORTB_PINCFG10 (SAM_PORTB_BASE+SAM_PORT_PINCFG10_OFFSET)
#define SAM_PORTB_PINCFG11 (SAM_PORTB_BASE+SAM_PORT_PINCFG11_OFFSET)
#define SAM_PORTB_PINCFG12 (SAM_PORTB_BASE+SAM_PORT_PINCFG12_OFFSET)
#define SAM_PORTB_PINCFG13 (SAM_PORTB_BASE+SAM_PORT_PINCFG13_OFFSET)
#define SAM_PORTB_PINCFG14 (SAM_PORTB_BASE+SAM_PORT_PINCFG14_OFFSET)
#define SAM_PORTB_PINCFG15 (SAM_PORTB_BASE+SAM_PORT_PINCFG15_OFFSET)
#define SAM_PORTB_PINCFG16 (SAM_PORTB_BASE+SAM_PORT_PINCFG16_OFFSET)
#define SAM_PORTB_PINCFG17 (SAM_PORTB_BASE+SAM_PORT_PINCFG17_OFFSET)
#define SAM_PORTB_PINCFG18 (SAM_PORTB_BASE+SAM_PORT_PINCFG18_OFFSET)
#define SAM_PORTB_PINCFG19 (SAM_PORTB_BASE+SAM_PORT_PINCFG19_OFFSET)
#define SAM_PORTB_PINCFG20 (SAM_PORTB_BASE+SAM_PORT_PINCFG20_OFFSET)
#define SAM_PORTB_PINCFG21 (SAM_PORTB_BASE+SAM_PORT_PINCFG21_OFFSET)
#define SAM_PORTB_PINCFG22 (SAM_PORTB_BASE+SAM_PORT_PINCFG22_OFFSET)
#define SAM_PORTB_PINCFG23 (SAM_PORTB_BASE+SAM_PORT_PINCFG23_OFFSET)
#define SAM_PORTB_PINCFG24 (SAM_PORTB_BASE+SAM_PORT_PINCFG24_OFFSET)
#define SAM_PORTB_PINCFG25 (SAM_PORTB_BASE+SAM_PORT_PINCFG25_OFFSET)
#define SAM_PORTB_PINCFG26 (SAM_PORTB_BASE+SAM_PORT_PINCFG26_OFFSET)
#define SAM_PORTB_PINCFG27 (SAM_PORTB_BASE+SAM_PORT_PINCFG27_OFFSET)
#define SAM_PORTB_PINCFG28 (SAM_PORTB_BASE+SAM_PORT_PINCFG28_OFFSET)
#define SAM_PORTB_PINCFG29 (SAM_PORTB_BASE+SAM_PORT_PINCFG29_OFFSET)
#define SAM_PORTB_PINCFG30 (SAM_PORTB_BASE+SAM_PORT_PINCFG30_OFFSET)
#define SAM_PORTB_PINCFG31 (SAM_PORTB_BASE+SAM_PORT_PINCFG31_OFFSET)
/* PORT register bit definitions ********************************************/
/* Data direction, data direction clear, data direction set, and data
* direction toggle registers
*/
#define PORT_DIR(n) (1 << n) /* Port data n, direction, n=0-31 */
/* Data output value, data output value clear, data output value set,
* and data output value toggle registers
*/
#define PORT_OUT(n) (1 << n) /* Port data n output value, n=0-31 */
/* Data input value register */
#define PORT_IN(n) (1 << n) /* Port n data input value, n=0-31 */
/* Control register */
#define PORT_CTRL(n) (1 << n) /* Port n input sampling mode, n=0-31 */
/* Write configuration registers */
#define PORT_WRCONFIG_PINMASK_SHIFT (0) /* Bits 0-15: Pin Mask for Multiple Pin Configuration */
#define PORT_WRCONFIG_PINMASK_MASK (0xffff << PORT_WRCONFIG_PINMASK_SHIFT)
# define PORT_WRCONFIG_PINMASK(n) (1 << (PORT_WRCONFIG_PINMASK_SHIFT+(n)))
#define PORT_WRCONFIG_PMUXEN (1 << 16) /* Bit 16: Peripheral Multiplexer Enable */
#define PORT_WRCONFIG_INEN (1 << 17) /* Bit 17: Input Enable */
#define PORT_WRCONFIG_PULLEN (1 << 18) /* Bit 18: Pull Enable */
#define PORT_WRCONFIG_DRVSTR (1 << 22) /* Bit 22: Output Driver Strength Selection */
#define PORT_WRCONFIG_PMUX_SHIFT (24) /* Bits 24-27: Peripheral Multiplexing */
#define PORT_WRCONFIG_PMUX_MASK (15 << PORT_WRCONFIG_PMUX_SHIFT)
# define PORT_WRCONFIG_PMUX(n) ((uint32_t)(n) << PORT_WRCONFIG_PMUX_SHIFT)
#define PORT_WRCONFIG_WRPMUX (1 << 28) /* Bit 28: Write PMUX */
#define PORT_WRCONFIG_WRPINCFG (1 << 30) /* Bit 30: Write PINCFG */
#define PORT_WRCONFIG_HWSEL (1 << 31) /* Bit 31: Half-Word Select */
/* Peripheral multiplexing registers */
#define PORT_PMUX_PERIPHA 0x00 /* Peripheral function A */
#define PORT_PMUX_PERIPHB 0x01 /* Peripheral function B */
#define PORT_PMUX_PERIPHC 0x02 /* Peripheral function C */
#define PORT_PMUX_PERIPHD 0x03 /* Peripheral function D */
#define PORT_PMUX_PERIPHE 0x04 /* Peripheral function E */
#define PORT_PMUX_PERIPHF 0x05 /* Peripheral function F */
#define PORT_PMUX_PERIPHG 0x06 /* Peripheral function G */
#define PORT_PMUX_PERIPHH 0x07 /* Peripheral function H */
/* Pin configuration registers */
#define PORT_PINCFG_PMUXEN (1 << 0) /* Bit 0: Peripheral Multiplexer Enable */
#define PORT_PINCFG_INEN (1 << 1) /* Bit 1: Input Enable */
#define PORT_PINCFG_PULLEN (1 << 2) /* Bit 2: Pull Enable */
#define PORT_PINCFG_DRVSTR (1 << 6) /* Bit 6: Output Driver Strength Selection */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PORT_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_sercom.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SERCOM_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SERCOM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Two generic clocks are used by the SERCOM: GCLK_SERCOMx_CORE and
* GCLK_SERCOMx_SLOW. The core clock (GCLK_SERCOMx_CORE) is required to
* clock the SERCOM while operating as a master, while the slow clock
* (GCLK_SERCOM_SLOW) is only required for certain functions.
* SERCOM modules must share the same slow GCLK channel ID.
*
* The baud-rate generator runs off the GCLK_SERCOMx_CORE clock
* (or, optionally, external clock).
*
* These definitions must match the GCLK_CLKCTRL_ID_* values defined in
* samd_gclk.c.
*/
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define SERCOM_GCLK_ID_SLOW 12
# define SERCOM_GCLK_ID_CORE(n) (13+(n))
# define SERCOM0_GCLK_ID_CORE 13
# define SERCOM1_GCLK_ID_CORE 14
# define SERCOM2_GCLK_ID_CORE 15
# define SERCOM3_GCLK_ID_CORE 16
# define SERCOM4_GCLK_ID_CORE 17
# define SERCOM5_GCLK_ID_CORE 18
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SERCOM_GCLK_ID_SLOW 19
# define SERCOM_GCLK_ID_CORE(n) (20+(n))
# define SERCOM0_GCLK_ID_CORE 20
# define SERCOM1_GCLK_ID_CORE 21
# define SERCOM2_GCLK_ID_CORE 22
# define SERCOM3_GCLK_ID_CORE 23
# define SERCOM4_GCLK_ID_CORE 24
# define SERCOM5_GCLK_ID_CORE 25
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SERCOM_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_spi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SPI_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/samd_sercom.h"
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* SPI register offsets *****************************************************/
#define SAM_SPI_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_SPI_CTRLB_OFFSET 0x0004 /* Control B register */
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
# define SAM_SPI_DBGCTRL_OFFSET 0x0008 /* Debug control register */
# define SAM_SPI_BAUD_OFFSET 0x000a /* Baud register */
# define SAM_SPI_INTENCLR_OFFSET 0x000c /* Interrupt enable clear register */
# define SAM_SPI_INTENSET_OFFSET 0x000d /* Interrupt enable set register */
# define SAM_SPI_INTFLAG_OFFSET 0x000e /* Interrupt flag and status clear register */
# define SAM_SPI_STATUS_OFFSET 0x0010 /* Status register */
# define SAM_SPI_ADDR_OFFSET 0x0014 /* Address register */
# define SAM_SPI_DATA_OFFSET 0x0018 /* Data register */
#elif defined(CONFIG_ARCH_FAMILY_SAMD21)
# define SAM_SPI_BAUD_OFFSET 0x000c /* Baud register */
# define SAM_SPI_INTENCLR_OFFSET 0x0014 /* Interrupt enable clear register */
# define SAM_SPI_INTENSET_OFFSET 0x0016 /* Interrupt enable set register */
# define SAM_SPI_INTFLAG_OFFSET 0x0018 /* Interrupt flag and status clear register */
# define SAM_SPI_STATUS_OFFSET 0x001a /* Status register */
# define SAM_SPI_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */
# define SAM_SPI_ADDR_OFFSET 0x0024 /* Address register */
# define SAM_SPI_DATA_OFFSET 0x0028 /* Data register */
# define SAM_SPI_DBGCTRL_OFFSET 0x0030 /* Debug control register */
#endif
/* SPI register addresses ***************************************************/
#define SAM_SPI0_CTRLA (SAM_SERCOM0_BASE+SAM_SPI_CTRLA_OFFSET)
#define SAM_SPI0_CTRLB (SAM_SERCOM0_BASE+SAM_SPI_CTRLB_OFFSET)
#define SAM_SPI0_BAUD (SAM_SERCOM0_BASE+SAM_SPI_BAUD_OFFSET)
#define SAM_SPI0_INTENCLR (SAM_SERCOM0_BASE+SAM_SPI_INTENCLR_OFFSET)
#define SAM_SPI0_INTENSET (SAM_SERCOM0_BASE+SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI0_INTFLAG (SAM_SERCOM0_BASE+SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI0_STATUS (SAM_SERCOM0_BASE+SAM_SPI_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SPI0_SYNCBUSY (SAM_SERCOM0_BASE+SAM_SPI_SYNCBUSY_OFFSET)
#endif
#define SAM_SPI0_ADDR (SAM_SERCOM0_BASE+SAM_SPI_ADDR_OFFSET)
#define SAM_SPI0_DATA (SAM_SERCOM0_BASE+SAM_SPI_DATA_OFFSET)
#define SAM_SPI0_DBGCTRL (SAM_SERCOM0_BASE+SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI1_CTRLA (SAM_SERCOM1_BASE+SAM_SPI_CTRLA_OFFSET)
#define SAM_SPI1_CTRLB (SAM_SERCOM1_BASE+SAM_SPI_CTRLB_OFFSET)
#define SAM_SPI1_BAUD (SAM_SERCOM1_BASE+SAM_SPI_BAUD_OFFSET)
#define SAM_SPI1_INTENCLR (SAM_SERCOM1_BASE+SAM_SPI_INTENCLR_OFFSET)
#define SAM_SPI1_INTENSET (SAM_SERCOM1_BASE+SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI1_INTFLAG (SAM_SERCOM1_BASE+SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI1_STATUS (SAM_SERCOM1_BASE+SAM_SPI_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SPI1_SYNCBUSY (SAM_SERCOM1_BASE+SAM_SPI_SYNCBUSY_OFFSET)
#endif
#define SAM_SPI1_ADDR (SAM_SERCOM1_BASE+SAM_SPI_ADDR_OFFSET)
#define SAM_SPI1_DATA (SAM_SERCOM1_BASE+SAM_SPI_DATA_OFFSET)
#define SAM_SPI1_DBGCTRL (SAM_SERCOM1_BASE+SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI2_CTRLA (SAM_SERCOM2_BASE+SAM_SPI_CTRLA_OFFSET)
#define SAM_SPI2_CTRLB (SAM_SERCOM2_BASE+SAM_SPI_CTRLB_OFFSET)
#define SAM_SPI2_BAUD (SAM_SERCOM2_BASE+SAM_SPI_BAUD_OFFSET)
#define SAM_SPI2_INTENCLR (SAM_SERCOM2_BASE+SAM_SPI_INTENCLR_OFFSET)
#define SAM_SPI2_INTENSET (SAM_SERCOM2_BASE+SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI2_INTFLAG (SAM_SERCOM2_BASE+SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI2_STATUS (SAM_SERCOM2_BASE+SAM_SPI_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SPI2_SYNCBUSY (SAM_SERCOM2_BASE+SAM_SPI_SYNCBUSY_OFFSET)
#endif
#define SAM_SPI2_ADDR (SAM_SERCOM2_BASE+SAM_SPI_ADDR_OFFSET)
#define SAM_SPI2_DATA (SAM_SERCOM2_BASE+SAM_SPI_DATA_OFFSET)
#define SAM_SPI2_DBGCTRL (SAM_SERCOM2_BASE+SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI3_CTRLA (SAM_SERCOM3_BASE+SAM_SPI_CTRLA_OFFSET)
#define SAM_SPI3_CTRLB (SAM_SERCOM3_BASE+SAM_SPI_CTRLB_OFFSET)
#define SAM_SPI3_BAUD (SAM_SERCOM3_BASE+SAM_SPI_BAUD_OFFSET)
#define SAM_SPI3_INTENCLR (SAM_SERCOM3_BASE+SAM_SPI_INTENCLR_OFFSET)
#define SAM_SPI3_INTENSET (SAM_SERCOM3_BASE+SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI3_INTFLAG (SAM_SERCOM3_BASE+SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI3_STATUS (SAM_SERCOM3_BASE+SAM_SPI_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SPI3_SYNCBUSY (SAM_SERCOM3_BASE+SAM_SPI_SYNCBUSY_OFFSET)
#endif
#define SAM_SPI3_ADDR (SAM_SERCOM3_BASE+SAM_SPI_ADDR_OFFSET)
#define SAM_SPI3_DATA (SAM_SERCOM3_BASE+SAM_SPI_DATA_OFFSET)
#define SAM_SPI3_DBGCTRL (SAM_SERCOM3_BASE+SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI4_CTRLA (SAM_SERCOM4_BASE+SAM_SPI_CTRLA_OFFSET)
#define SAM_SPI4_CTRLB (SAM_SERCOM4_BASE+SAM_SPI_CTRLB_OFFSET)
#define SAM_SPI4_BAUD (SAM_SERCOM4_BASE+SAM_SPI_BAUD_OFFSET)
#define SAM_SPI4_INTENCLR (SAM_SERCOM4_BASE+SAM_SPI_INTENCLR_OFFSET)
#define SAM_SPI4_INTENSET (SAM_SERCOM4_BASE+SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI4_INTFLAG (SAM_SERCOM4_BASE+SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI4_STATUS (SAM_SERCOM4_BASE+SAM_SPI_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SPI4_SYNCBUSY (SAM_SERCOM4_BASE+SAM_SPI_SYNCBUSY_OFFSET)
#endif
#define SAM_SPI4_ADDR (SAM_SERCOM4_BASE+SAM_SPI_ADDR_OFFSET)
#define SAM_SPI4_DATA (SAM_SERCOM4_BASE+SAM_SPI_DATA_OFFSET)
#define SAM_SPI5_CTRLA (SAM_SERCOM5_BASE+SAM_SPI_CTRLA_OFFSET)
#define SAM_SPI5_CTRLB (SAM_SERCOM5_BASE+SAM_SPI_CTRLB_OFFSET)
#define SAM_SPI5_DBGCTRL (SAM_SERCOM5_BASE+SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI5_BAUD (SAM_SERCOM5_BASE+SAM_SPI_BAUD_OFFSET)
#define SAM_SPI5_INTENCLR (SAM_SERCOM5_BASE+SAM_SPI_INTENCLR_OFFSET)
#define SAM_SPI5_INTENSET (SAM_SERCOM5_BASE+SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI5_INTFLAG (SAM_SERCOM5_BASE+SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI5_STATUS (SAM_SERCOM5_BASE+SAM_SPI_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SPI5_SYNCBUSY (SAM_SERCOM5_BASE+SAM_SPI_SYNCBUSY_OFFSET)
#endif
#define SAM_SPI5_ADDR (SAM_SERCOM5_BASE+SAM_SPI_ADDR_OFFSET)
#define SAM_SPI5_DATA (SAM_SERCOM5_BASE+SAM_SPI_DATA_OFFSET)
#define SAM_SPI4_DBGCTRL (SAM_SERCOM4_BASE+SAM_SPI_DBGCTRL_OFFSET)
/* SPI register bit definitions *********************************************/
/* Control A register */
#define SPI_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
#define SPI_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
#define SPI_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */
#define SPI_CTRLA_MODE_MASK (7 << SPI_CTRLA_MODE_SHIFT)
# define SPI_CTRLA_MODE_SLAVE (2 << SPI_CTRLA_MODE_SHIFT) /* SPI slave operation */
# define SPI_CTRLA_MODE_MASTER (3 << SPI_CTRLA_MODE_SHIFT) /* SPI master operation */
#define SPI_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */
#define SPI_CTRLA_IBON (1 << 8) /* Bit 8: Immediate BUFOVF notification */
#define SPI_CTRLA_DOPO_SHIFT (16) /* Bit 16-17: Data out pinout */
#define SPI_CTRLA_DOPO_MASK (3 << SPI_CTRLA_DOPO_SHIFT) /* Bit 16-17: Data out pinout */
# define SPI_CTRLA_DOPO_DOPAD012 (0 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD0 SCK=PAD1 SS=PAD2 */
# define SPI_CTRLA_DOPO_DOPAD231 (1 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD2 SCK=PAD3 SS=PAD1 */
# define SPI_CTRLA_DOPO_DOPAD312 (2 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD3 SCK=PAD1 SS=PAD2 */
# define SPI_CTRLA_DOPO_DOPAD031 (3 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD0 SCK=PAD3 SS=PAD1 */
#define SPI_CTRLA_DIPO_SHIFT (20) /* Bits 20-21: Data in pinout */
#define SPI_CTRLA_DIPO_MASK (3 << SPI_CTRLA_DIPO_SHIFT)
# define SPI_CTRLA_DIPAD0 (0 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD0 for DI */
# define SPI_CTRLA_DIPAD1 (1 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD1 for DI */
# define SPI_CTRLA_DIPAD2 (2 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD2 for DI */
# define SPI_CTRLA_DIPAD3 (3 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD3 for DI */
#define SPI_CTRLA_FORM_SHIFT (24) /* Bits 24-27: Frame format */
#define SPI_CTRLA_FORM_MASK (7 << SPI_CTRLA_FORM_SHIFT)
# define SPI_CTRLA_FORM_SPI (0 << SPI_CTRLA_FORM_SHIFT) /* SPI frame (no address) */
# define SPI_CTRLA_FORM_ADDR (2 << SPI_CTRLA_FORM_SHIFT) /* SPI frame (w/address) */
#define SPI_CTRLA_CPHA (1 << 28) /* Bit 28: Clock phase */
#define SPI_CTRLA_CPOL (1 << 29) /* Bit 29: Clock polarity */
#define SPI_CTRLA_DORD (1 << 30) /* Bit 30: Data order */
# define SPI_CTRLA_MSBFIRST (0)
# define SPI_CTRLA_LSBFIRST SPI_CTRLA_DORD
/* Control B register */
#define SPI_CTRLB_CHSIZE_SHIFT (0) /* Bits 0-2: Character Size */
#define SPI_CTRLB_CHSIZE_MASK (7 << SPI_CTRLB_CHSIZE_SHIFT)
# define SPI_CTRLB_CHSIZE_8BITS (0 << SPI_CTRLB_CHSIZE_SHIFT) /* 8 bits */
# define SPI_CTRLB_CHSIZE_9BITS (1 << SPI_CTRLB_CHSIZE_SHIFT) /* 9 bits */
#define SPI_CTRLB_PLOADEN (1 << 6) /* Bit 6: Slave Data Preload Enable */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SPI_CTRLB_SSDE (1 << 9) /* Bit 9: Slave Select Low Detect Enable */
# define SPI_CTRLB_MSSEN (1 << 13) /* Bit 13: Master Slave Select Enable */
#endif
#define SPI_CTRLB_AMODE_SHIFT (14) /* Bits 14-15: Address Mode */
#define SPI_CTRLB_AMODE_MASK (3 << SPI_CTRLB_AMODE_SHIFT)
# define SPI_CTRLB_AMODE_ADDRMASK (0 << SPI_CTRLB_AMODE_SHIFT) /* ADDRMASK used to mask ADDR */
# define SPI_CTRLB_AMODE_2ADDRS (1 << SPI_CTRLB_AMODE_SHIFT) /* Slave 2 addresses: ADDR & ADDRMASK */
# define SPI_CTRLB_AMODE_RANGE (2 << SPI_CTRLB_AMODE_SHIFT) /* Slave range of addresses: ADDRMASK-ADDR */
#define SPI_CTRLB_RXEN (1 << 17) /* Bit 17: Receiver enable */
/* Baud register (8-bit baud value) */
/* Interrupt enable clear, interrupt enable set, interrupt enable set,
* interrupt flag and status clear registers.
*/
#define SPI_INT_DRE (1 << 0) /* Bit 0: Data register empty interrupt */
#define SPI_INT_TXC (1 << 1) /* Bit 1: Transmit complete interrupt */
#define SPI_INT_RXC (1 << 2) /* Bit 2: Receive complete interrupt */
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define SPI_INT_ALL (0x07)
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SPI_INT_SSL (1 << 3) /* Bit 3: Slave select low interrupt */
# define SPI_INT_ERROR (1 << 7) /* Bit 7: Error interrupt */
# define SPI_INT_ALL (0x8f)
#endif
/* Status register */
#define SPI_STATUS_BUFOVF (1 << 2) /* Bit 2: Buffer overflow */
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define SPI_STATUS_SYNCBUSY (1 << 15) /* Bit 15: Synchronization busy */
#endif
#define SPI_STATUS_CLRALL SPI_STATUS_BUFOVF
/* Synchronization busy register */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SPI_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset synchronization busy */
# define SPI_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: SERCOM enable synchronization busy */
# define SPI_SYNCBUSY_CTRLB (1 << 2) /* Bit 2: CTRLB synchronization busy */
# define SPI_SYNCBUSY_ALL 0x0007
#endif
/* Address register */
#define SPI_ADDR_SHIFT (0) /* Bits 0-7: Address */
#define SPI_ADDR_MASK (0xff << SPI_ADDR_SHIFT)
# define SPI_ADDR(n) ((uint32_t)(n) << SPI_ADDR_SHIFT)
#define SPI_ADDRMASK_SHIFT (16) /* Bits 16-23: Address Mask */
#define SPI_ADDRMASK_MASK (0xff << SPI_ADDRMASK_SHIFT)
# define SPI_ADDRMASK(n) ((uint32_t)(n) << SPI_ADDRMASK_SHIFT)
/* Data register */
#define SPI_DATA_MASK (0x1ff) /* Bits 0-8: Data */
/* Debug control register */
#define SPI_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SPI_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_sysctrl.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SYSCTRL_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SYSCTRL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* SYSCTRL register offsets *************************************************/
#define SAM_SYSCTRL_INTENCLR_OFFSET 0x0000 /* Interrupt enable clear */
#define SAM_SYSCTRL_INTENSET_OFFSET 0x0004 /* Interrupt enable set */
#define SAM_SYSCTRL_INTFLAG_OFFSET 0x0008 /* Interrupt flag status and clear */
#define SAM_SYSCTRL_PCLKSR_OFFSET 0x000c /* Power and clocks status */
#define SAM_SYSCTRL_XOSC_OFFSET 0x0010 /* External multi-purpose crystal oscillator control */
#define SAM_SYSCTRL_XOSC32K_OFFSET 0x0014 /* 32kHz external crystal oscillator control */
#define SAM_SYSCTRL_OSC32K_OFFSET 0x0018 /* 32kHz internal oscillator control */
#define SAM_SYSCTRL_OSCULP32K_OFFSET 0x001c /* 32kHz ultra low power internal oscillator control */
#define SAM_SYSCTRL_OSC8M_OFFSET 0x0020 /* 8MHz internal oscillator control */
#define SAM_SYSCTRL_DFLLCTRL_OFFSET 0x0024 /* DFLL48M control */
#define SAM_SYSCTRL_DFLLVAL_OFFSET 0x0028 /* DFLL48M value */
#define SAM_SYSCTRL_DFLLMUL_OFFSET 0x002c /* DFLL48M multiplier */
#define SAM_SYSCTRL_DFLLSYNC_OFFSET 0x0030 /* DFLL48M synchronization */
#define SAM_SYSCTRL_BOD33_OFFSET 0x0034 /* 3.3V brown-out detector control */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SYSCTRL_VREG_OFFSET 0x003c /* Voltage regulator system control */
#endif
#define SAM_SYSCTRL_VREF_OFFSET 0x0040 /* Voltage references system control */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SYSCTRL_DPLLCTRLA_OFFSET 0x0044 /* DPLL Control A */
# define SAM_SYSCTRL_DPLLRATIO_OFFSET 0x0048 /* DPLL ratio control */
# define SAM_SYSCTRL_DPLLCTRLB_OFFSET 0x004c /* DPLL Control B */
# define SAM_SYSCTRL_DPLLSTATUS_OFFSET 0x0050 /* DPLL status */
#endif
/* SYSCTRL register addresses ***********************************************/
#define SAM_SYSCTRL_INTENCLR (SAM_SYSCTRL_BASE+SAM_SYSCTRL_INTENCLR_OFFSET)
#define SAM_SYSCTRL_INTENSET (SAM_SYSCTRL_BASE+SAM_SYSCTRL_INTENSET_OFFSET)
#define SAM_SYSCTRL_INTFLAG (SAM_SYSCTRL_BASE+SAM_SYSCTRL_INTFLAG_OFFSET)
#define SAM_SYSCTRL_PCLKSR (SAM_SYSCTRL_BASE+SAM_SYSCTRL_PCLKSR_OFFSET)
#define SAM_SYSCTRL_XOSC (SAM_SYSCTRL_BASE+SAM_SYSCTRL_XOSC_OFFSET)
#define SAM_SYSCTRL_XOSC32K (SAM_SYSCTRL_BASE+SAM_SYSCTRL_XOSC32K_OFFSET)
#define SAM_SYSCTRL_OSC32K (SAM_SYSCTRL_BASE+SAM_SYSCTRL_OSC32K_OFFSET)
#define SAM_SYSCTRL_OSCULP32K (SAM_SYSCTRL_BASE+SAM_SYSCTRL_OSCULP32K_OFFSET)
#define SAM_SYSCTRL_OSC8M (SAM_SYSCTRL_BASE+SAM_SYSCTRL_OSC8M_OFFSET)
#define SAM_SYSCTRL_DFLLCTRL (SAM_SYSCTRL_BASE+SAM_SYSCTRL_DFLLCTRL_OFFSET)
#define SAM_SYSCTRL_DFLLVAL (SAM_SYSCTRL_BASE+SAM_SYSCTRL_DFLLVAL_OFFSET)
#define SAM_SYSCTRL_DFLLMUL (SAM_SYSCTRL_BASE+SAM_SYSCTRL_DFLLMUL_OFFSET)
#define SAM_SYSCTRL_DFLLSYNC (SAM_SYSCTRL_BASE+SAM_SYSCTRL_DFLLSYNC_OFFSET)
#define SAM_SYSCTRL_BOD33 (SAM_SYSCTRL_BASE+SAM_SYSCTRL_BOD33_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SYSCTRL_VREG (SAM_SYSCTRL_BASE+SAM_SYSCTRL_VREG_OFFSET)
#endif
#define SAM_SYSCTRL_VREF (SAM_SYSCTRL_BASE+SAM_SYSCTRL_VREF_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SYSCTRL_DPLLCTRLA (SAM_SYSCTRL_BASE+SAM_SYSCTRL_DPLLCTRLA_OFFSET)
# define SAM_SYSCTRL_DPLLRATIO (SAM_SYSCTRL_BASE+SAM_SYSCTRL_DPLLRATIO_OFFSET)
# define SAM_SYSCTRL_DPLLCTRLB (SAM_SYSCTRL_BASE+SAM_SYSCTRL_DPLLCTRLB_OFFSET)
# define SAM_SYSCTRL_DPLLSTATUS (SAM_SYSCTRL_BASE+SAM_SYSCTRL_DPLLSTATUS_OFFSET)
#endif
/* SYSCTRL register bit definitions *****************************************/
/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and
* clear, and Power and clocks status registers.
*/
#define SYSCTRL_INT_XOSCRDY (1 << 0) /* Bit 0: XOSC ready interrupt */
#define SYSCTRL_INT_XOSC32KRDY (1 << 1) /* Bit 1: XOSC32K ready interrupt */
#define SYSCTRL_INT_OSC32KRDY (1 << 2) /* Bit 2: OSC32K ready interrupt */
#define SYSCTRL_INT_OSC8MRDY (1 << 3) /* Bit 3: OSC8M ready interrupt */
#define SYSCTRL_INT_DFLLRDY (1 << 4) /* Bit 4: DFLL ready interrupt */
#define SYSCTRL_INT_DFLLOOB (1 << 5) /* Bit 5: DFLL out of bounds interrupt */
#define SYSCTRL_INT_DFLLLCKF (1 << 6) /* Bit 6: DFLL lock fine interrupt */
#define SYSCTRL_INT_DFLLLCKC (1 << 7) /* Bit 7: DFLL lock coarse interrupt */
#define SYSCTRL_INT_DFLLRCS (1 << 8) /* Bit 8: DFLL reference clock stopped interrupt */
#define SYSCTRL_INT_BOD33RDY (1 << 9) /* Bit 9: BOD33 ready interrupt */
#define SYSCTRL_INT_BOD33DET (1 << 10) /* Bit 10: BOD33 detection interrupt */
#define SYSCTRL_INT_B33SRDY (1 << 11) /* Bit 11: BOD33 synchronization ready interrupt */
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
# define SYSCTRL_INT_BOD12RDY (1 << 12) /* Bit 12: BOD12 ready interrupt */
# define SYSCTRL_INT_BOD12DET (1 << 13) /* Bit 13: BOD12 detection interrupt */
# define SYSCTRL_INT_B12SRDY (1 << 14) /* Bit 14: BOD12 synchronization ready interrupt */
# define SYSCTRL_INT_ALL (0x00007fff)
#elif defined(CONFIG_ARCH_FAMILY_SAMD21)
# define SYSCTRL_INT_DPLLLCKR (1 << 15) /* Bit 15: DPLL lock rise interrupt */
# define SYSCTRL_INT_DPLLLCKF (1 << 16) /* Bit 16: DPLL lock fall interrupt */
# define SYSCTRL_INT_DPLLLTO (1 << 17) /* Bit 17: DPLL lock timeout interrupt */
# define SYSCTRL_INT_ALL (0x00038fff)
#endif
/* External multi-purpose crystal oscillator control register */
#define SYSCTRL_XOSC_ENABLE (1 << 1) /* Bit 1: Oscillator enable */
#define SYSCTRL_XOSC_XTALEN (1 << 2) /* Bit 2: Crystal oscillator enable */
#define SYSCTRL_XOSC_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
#define SYSCTRL_XOSC_ONDEMAND (1 << 7) /* Bit 7: On demand control */
#define SYSCTRL_XOSC_GAIN_SHIFT (8) /* Bits 8-10: Oscillator gain */
#define SYSCTRL_XOSC_GAIN_MASK (7 << SYSCTRL_XOSC_GAIN_SHIFT)
# define SYSCTRL_XOSC_GAIN(n) ((n) << SYSCTRL_XOSC_GAIN_SHIFT)
# define SYSCTRL_XOSC_GAIN_2MHZ (0 << SYSCTRL_XOSC_GAIN_SHIFT) /* 2MHz */
# define SYSCTRL_XOSC_GAIN_4MHZ (1 << SYSCTRL_XOSC_GAIN_SHIFT) /* 4MHz */
# define SYSCTRL_XOSC_GAIN_8MHZ (2 << SYSCTRL_XOSC_GAIN_SHIFT) /* 8MHz */
# define SYSCTRL_XOSC_GAIN_16MHZ (3 << SYSCTRL_XOSC_GAIN_SHIFT) /* 16MHz */
# define SYSCTRL_XOSC_GAIN_30MHZ (4 << SYSCTRL_XOSC_GAIN_SHIFT) /* 30MHz */
#define SYSCTRL_XOSC_AMPGC (1 << 11) /* Bit 11: Automatic amplitude gain control */
#define SYSCTRL_XOSC_STARTUP_SHIFT (12) /* Bits 12-15: Start-up time */
#define SYSCTRL_XOSC_STARTUP_MASK (15 << SYSCTRL_XOSC_STARTUP_SHIFT)
# define SYSCTRL_XOSC_STARTUP(n) ((n) << SYSCTRL_XOSC_STARTUP_SHIFT)
# define SYSCTRL_XOSC_STARTUP_31US (0 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 31µs */
# define SYSCTRL_XOSC_STARTUP_61US (1 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 61µs */
# define SYSCTRL_XOSC_STARTUP_122US (2 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 122µs */
# define SYSCTRL_XOSC_STARTUP_244US (3 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 244µs */
# define SYSCTRL_XOSC_STARTUP_488US (4 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 488µs */
# define SYSCTRL_XOSC_STARTUP_977US (5 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 977µs */
# define SYSCTRL_XOSC_STARTUP_2MS (6 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 1953µs */
# define SYSCTRL_XOSC_STARTUP_4MS (7 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 3906µs */
# define SYSCTRL_XOSC_STARTUP_8MS (8 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 7813µs */
# define SYSCTRL_XOSC_STARTUP_16MS (9 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 15625µs */
# define SYSCTRL_XOSC_STARTUP_31MS (10 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 31250µs */
# define SYSCTRL_XOSC_STARTUP_63MS (11 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 62500µs */
# define SYSCTRL_XOSC_STARTUP_125MS (12 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 125000µs */
# define SYSCTRL_XOSC_STARTUP_250MS (13 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 250000µs */
# define SYSCTRL_XOSC_STARTUP_500MS (14 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 500000µs */
# define SYSCTRL_XOSC_STARTUP_1S (15 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 1000000µs */
/* 32kHz external crystal oscillator control register */
#define SYSCTRL_XOSC32K_ENABLE (1 << 1) /* Bit 1: Oscillator enable */
#define SYSCTRL_XOSC32K_XTALEN (1 << 2) /* Bit 2: Crystal oscillator enable */
#define SYSCTRL_XOSC32K_EN32K (1 << 3) /* Bit 3: 32kHz Output enable */
#define SYSCTRL_XOSC32K_EN1K (1 << 4) /* Bit 4: 1kHz Output enable */
#define SYSCTRL_XOSC32K_AAMPEN (1 << 5) /* Bit 5: Automatic amplitude control enable */
#define SYSCTRL_XOSC32K_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
#define SYSCTRL_XOSC32K_ONDEMAND (1 << 7) /* Bit 7: On demand control */
#define SYSCTRL_XOSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */
#define SYSCTRL_XOSC32K_STARTUP_MASK (7 << SYSCTRL_XOSC32K_STARTUP_SHIFT)
# define SYSCTRL_XOSC32K_STARTUP(n) ((n) << SYSCTRL_XOSC32K_STARTUP_SHIFT)
# define SYSCTRL_XOSC32K_STARTUP_122US (0 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 122µs */
# define SYSCTRL_XOSC32K_STARTUP_1MS (1 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 1068µs */
# define SYSCTRL_XOSC32K_STARTUP_63MS (2 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 62592µs */
# define SYSCTRL_XOSC32K_STARTUP_125MS (3 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 125092µs */
# define SYSCTRL_XOSC32K_STARTUP_500MS (4 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 500092µs */
# define SYSCTRL_XOSC32K_STARTUP_1S (5 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 1000092µs */
# define SYSCTRL_XOSC32K_STARTUP_2S (6 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 2000092µs */
# define SYSCTRL_XOSC32K_STARTUP_4S (7 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 4000092µs */
#define SYSCTRL_XOSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */
/* 32kHz internal oscillator control register */
#define SYSCTRL_OSC32K_ENABLE (1 << 1) /* Bit 1: Oscillator enable */
#define SYSCTRL_OSC32K_EN32K (1 << 2) /* Bit 2: 32kHz Output enable */
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define SYSCTRL_OSC32K_EN1K (1 << 3) /* Bit 3: 1kHz Output enable */
#endif
#define SYSCTRL_OSC32K_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
#define SYSCTRL_OSC32K_ONDEMAND (1 << 7) /* Bit 7: On demand control */
#define SYSCTRL_OSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */
#define SYSCTRL_OSC32K_STARTUP_MASK (7 << SYSCTRL_OSC32K_STARTUP_SHIFT)
# define SYSCTRL_OSC32K_STARTUP(n) ((n) << SYSCTRL_OSC32K_STARTUP_SHIFT)
# define SYSCTRL_OSC32K_STARTUP_92US (0 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 92µs */
# define SYSCTRL_OSC32K_STARTUP_122US (1 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 122µs */
# define SYSCTRL_OSC32K_STARTUP_183US (2 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 183µs */
# define SYSCTRL_OSC32K_STARTUP_305US (3 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 305µs */
# define SYSCTRL_OSC32K_STARTUP_549US (4 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 549µs */
# define SYSCTRL_OSC32K_STARTUP_1MS (5 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 1038µs */
# define SYSCTRL_OSC32K_STARTUP_2MS (6 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 2014µs */
# define SYSCTRL_OSC32K_STARTUP_4MS (7 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 3967µs */
#define SYSCTRL_OSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */
#define SYSCTRL_OSC32K_CALIB_SHIFT (16) /* Bits 16-22: Oscillator calibration */
#define SYSCTRL_OSC32K_CALIB_MASK (0x7f << SYSCTRL_OSC32K_CALIB_SHIFT)
# define SYSCTRL_OSC32K_CALIB(n) ((n) << SYSCTRL_OSC32K_CALIB_SHIFT)
/* 32kHz ultra low power internal oscillator control register */
#define SYSCTRL_OSCULP32K_CALIB_SHIFT (0) /* Bits 0-4: Oscillator Calibration */
#define SYSCTRL_OSCULP32K_CALIB_MASK (0x7f << SYSCTRL_OSCULP32K_CALIB_SHIFT)
# define SYSCTRL_OSCULP32K_CALIB(n) ((n) << SYSCTRL_OSCULP32K_CALIB_SHIFT)
#define SYSCTRL_OSCULP32K_WRTLOCK (1 << 7) /* Bit 7: Write Lock */
/* 8MHz internal oscillator control register */
#define SYSCTRL_OSC8M_ENABLE (1 << 1) /* Bit 1: Oscillator enable */
#define SYSCTRL_OSC8M_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
#define SYSCTRL_OSC8M_ONDEMAND (1 << 7) /* Bit 7: On demand control */
#define SYSCTRL_OSC8M_PRESC_SHIFT (8) /* Bits 8-9: Oscillator prescaler */
#define SYSCTRL_OSC8M_PRESC_MASK (3 << SYSCTRL_OSC8M_PRESC_SHIFT)
# define SYSCTRL_OSC8M_PRESC(n) ((n) << SYSCTRL_OSC8M_PRESC_SHIFT)
# define SYSCTRL_OSC8M_PRESC_DIV1 (0 << SYSCTRL_OSC8M_PRESC_SHIFT) /* 1 */
# define SYSCTRL_OSC8M_PRESC_DIV2 (1 << SYSCTRL_OSC8M_PRESC_SHIFT) /* 2 */
# define SYSCTRL_OSC8M_PRESC_DIV3 (2 << SYSCTRL_OSC8M_PRESC_SHIFT) /* 4 */
# define SYSCTRL_OSC8M_PRESC_DIV8 (3 << SYSCTRL_OSC8M_PRESC_SHIFT) /* 8 */
#define SYSCTRL_OSC8M_CALIB_SHIFT (16) /* Bits 16-27: Oscillator calibration */
#define SYSCTRL_OSC8M_CALIB_MASK (0xfff << SYSCTRL_OSC8M_CALIB_SHIFT)
# define SYSCTRL_OSC8M_CALIB(n) ((n) << SYSCTRL_OSC8M_CALIB_SHIFT)
#define SYSCTRL_OSC8M_FRANGE_SHIFT (30) /* Bits 30-31: Oscillator frequency range */
#define SYSCTRL_OSC8M_FRANGE_MASK (3 << SYSCTRL_OSC8M_FRANGE_SHIFT)
# define SYSCTRL_OSC8M_FRANGE(n) ((n) << SYSCTRL_OSC8M_FRANGE_SHIFT)
# define SYSCTRL_OSC8M_FRANGE_LOW (0 << SYSCTRL_OSC8M_FRANGE_SHIFT) /* 4 to 6MHz */
# define SYSCTRL_OSC8M_FRANGE_MEDLOW (1 << SYSCTRL_OSC8M_FRANGE_SHIFT) /* 6 to 8MHz */
# define SYSCTRL_OSC8M_FRANGE_MEDHI (2 << SYSCTRL_OSC8M_FRANGE_SHIFT) /* 8 to 11MHz */
# define SYSCTRL_OSC8M_FRANGE_HI (3 << SYSCTRL_OSC8M_FRANGE_SHIFT) /* 11 to 15MHz */
/* DFLL48M control register */
#define SYSCTRL_DFLLCTRL_ENABLE (1 << 1) /* Bit 1: DFLL enable */
#define SYSCTRL_DFLLCTRL_MODE (1 << 2) /* Bit 2: Operating mode selection */
#define SYSCTRL_DFLLCTRL_STABLE (1 << 3) /* Bit 3: Stable DFLL frequency */
#define SYSCTRL_DFLLCTRL_LLAW (1 << 4) /* Bit 4: Lose lock after wake */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SYSCTRL_DFLLCTRL_USBCRM (1 << 5) /* Bit 5: USB clock recovery mode */
# define SYSCTRL_DFLLCTRL_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
#endif
#define SYSCTRL_DFLLCTRL_ONDEMAND (1 << 7) /* Bit 7: On demand control */
#define SYSCTRL_DFLLCTRL_CCDIS (1 << 8) /* Bit 8: Chill cycle disable */
#define SYSCTRL_DFLLCTRL_QLDIS (1 << 9) /* Bit 9: Quick Lock Disable */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SYSCTRL_DFLLCTRL_BPLCKC (1 << 10) /* Bit 10: Bypass coards lock */
# define SYSCTRL_DFLLCTRL_WAITLOCK (1 << 11) /* Bit 11: Wait lock */
#endif
/* DFLL48M value register */
#define SYSCTRL_DFLLVAL_FINE_SHIFT (0) /* Bits 0-9: Fine value */
#define SYSCTRL_DFLLVAL_FINE_MASK (0x3ff << SYSCTRL_DFLLVAL_FINE_SHIFT)
# define SYSCTRL_DFLLVAL_FINE(n) ((n) << SYSCTRL_DFLLVAL_FINE_SHIFT)
#define SYSCTRL_DFLLVAL_COARSE_SHIFT (10) /* Bits 10-15: Coarse value */
#define SYSCTRL_DFLLVAL_COARSE_MASK (0x3f << SYSCTRL_DFLLVAL_COARSE_SHIFT)
# define SYSCTRL_DFLLVAL_COARSE(n) ((n) << SYSCTRL_DFLLVAL_COARSE_SHIFT)
#define SYSCTRL_DFLLVAL_DIFF_SHIFT (16) /* Bits 16-31: Multiplication ratio difference */
#define SYSCTRL_DFLLVAL_DIFF_MASK (0xffff << SYSCTRL_DFLLVAL_DIFF_SHIFT)
# define SYSCTRL_DFLLVAL_DIFF(n) ((n) << SYSCTRL_DFLLVAL_DIFF_SHIFT)
/* DFLL48M multiplier register */
#define SYSCTRL_DFLLMUL_MUL_SHIFT (0) /* Bits 0-15: DFLL multiply factor */
#define SYSCTRL_DFLLMUL_MUL_MASK (0xffff << SYSCTRL_DFLLMUL_MUL_SHIFT)
# define SYSCTRL_DFLLMUL_MUL(n) ((n) << SYSCTRL_DFLLMUL_MUL_SHIFT)
#define SYSCTRL_DFLLMUL_FSTEP_SHIFT (16) /* Bits 16-25: Fine maximum step */
#define SYSCTRL_DFLLMUL_FSTEP_MASK (0x3ff << SYSCTRL_DFLLMUL_FSTEP_SHIFT)
# define SYSCTRL_DFLLMUL_FSTEP(n) ((n) << SYSCTRL_DFLLMUL_FSTEP_SHIFT)
#define SYSCTRL_DFLLMUL_CSTEP_SHIFT (26) /* Bits 26-31: Coarse maximum step */
#define SYSCTRL_DFLLMUL_CSTEP_MASK (0x3f << SYSCTRL_DFLLMUL_CSTEP_SHIFT)
# define SYSCTRL_DFLLMUL_CSTEP(n) ((n) << SYSCTRL_DFLLMUL_CSTEP_SHIFT)
/* DFLL48M synchronization register */
#define SYSCTRL_DFLLSYNC_READREQ (1 << 7) /* Bit 7: Read request */
/* 3.3V brown-out detector control register */
#define SYSCTRL_BOD33_ENABLE (1 << 1) /* Bit 1: Enable */
#define SYSCTRL_BOD33_HYST (1 << 2) /* Bit 2: Hysteresis */
#define SYSCTRL_BOD33_ACTION_SHIFT (3) /* Bits 3-4: BOD33 action */
#define SYSCTRL_BOD33_ACTION_MASK (3 << SYSCTRL_BOD33_ACTION_SHIFT)
# define SYSCTRL_BOD33_ACTION(n) ((n) << SYSCTRL_BOD33_ACTION_SHIFT)
# define SYSCTRL_BOD33_ACTION_NONE (0 << SYSCTRL_BOD33_ACTION_SHIFT) /* No action */
# define SYSCTRL_BOD33_ACTION_RESET (1 << SYSCTRL_BOD33_ACTION_SHIFT) /* BOD33 generates reset */
# define SYSCTRL_BOD33_ACTION_INTR (2 << SYSCTRL_BOD33_ACTION_SHIFT) /* BOD33 generates interrupt */
#define SYSCTRL_BOD33_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
#define SYSCTRL_BOD33_MODE (1 << 8) /* Bit 8: Operation mode */
#define SYSCTRL_BOD33_CEN (1 << 9) /* Bit 9: Clock enable */
#define SYSCTRL_BOD33_PSEL_SHIFT (12) /* Bits 12-15: Prescaler select */
#define SYSCTRL_BOD33_PSEL_MASK (15 << SYSCTRL_BOD33_PSEL_SHIFT)
# define SYSCTRL_BOD33_PSEL(n) ((n) << SYSCTRL_BOD33_PSEL_SHIFT)
# define SYSCTRL_BOD33_PSEL_DIV2 (0 << SYSCTRL_BOD33_PSEL_SHIFT) /* Divide clock by 2 */
# define SYSCTRL_BOD33_PSEL_DIV4 (1 << SYSCTRL_BOD33_PSEL_SHIFT) /* Divide clock by 4 */
# define SYSCTRL_BOD33_PSEL_DIV8 (2 << SYSCTRL_BOD33_PSEL_SHIFT) /* Divide clock by 8 */
# define SYSCTRL_BOD33_PSEL_DIV16 (3 << SYSCTRL_BOD33_PSEL_SHIFT) /* Divide clock by 16 */
# define SYSCTRL_BOD33_PSEL_DIV32 (4 << SYSCTRL_BOD33_PSEL_SHIFT) /* Divide clock by 32 */
# define SYSCTRL_BOD33_PSEL_DIV64 (5 << SYSCTRL_BOD33_PSEL_SHIFT) /* Divide clock by 64 */
# define SYSCTRL_BOD33_PSEL_DIV128 (6 << SYSCTRL_BOD33_PSEL_SHIFT) /* Divide clock by 128 */
# define SYSCTRL_BOD33_PSEL_DIV256 (7 << SYSCTRL_BOD33_PSEL_SHIFT) /* Divide clock by 256 */
# define SYSCTRL_BOD33_PSEL_DIV512 (8 << SYSCTRL_BOD33_PSEL_SHIFT) /* Divide clock by 512 */
# define SYSCTRL_BOD33_PSEL_DIV1K (9 << SYSCTRL_BOD33_PSEL_SHIFT) /* Divide clock by 1024 */
# define SYSCTRL_BOD33_PSEL_DIV2K (10 << SYSCTRL_BOD33_PSEL_SHIFT) /* Divide clock by 2048 */
# define SYSCTRL_BOD33_PSEL_DIV4K (11 << SYSCTRL_BOD33_PSEL_SHIFT) /* Divide clock by 4096 */
# define SYSCTRL_BOD33_PSEL_DIV8K (12 << SYSCTRL_BOD33_PSEL_SHIFT) /* Divide clock by 8192 */
# define SYSCTRL_BOD33_PSEL_DIV16K (13 << SYSCTRL_BOD33_PSEL_SHIFT) /* Divide clock by 16384 */
# define SYSCTRL_BOD33_PSEL_DIV32K (14 << SYSCTRL_BOD33_PSEL_SHIFT) /* Divide clock by 32768 */
# define SYSCTRL_BOD33_PSEL_DIV64K (15 << SYSCTRL_BOD33_PSEL_SHIFT) /* Divide clock by 65536 */
#define SYSCTRL_BOD33_LEVEL_SHIFT (16) /* Bits 16-21: BOD33 threshold level */
#define SYSCTRL_BOD33_LEVEL_MASK (0x3f << SYSCTRL_BOD33_LEVEL_SHIFT)
# define SYSCTRL_BOD33_LEVEL(n) ((n) << SYSCTRL_BOD33_LEVEL_SHIFT)
/* Voltage regulator system control register */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SYSCTRL_VREG_RUNSTDBY (1 << 6) /* Bit 6: Run in Standby */
# define SYSCTRL_VREG_FORCELDO (1 << 13) /* Bit 13: Force LDO voltage regulator */
#endif
/* Voltage references system control register */
#define SYSCTRL_VREF_TSEN (1 << 1) /* Bit 1: Temperature sensor enable */
#define SYSCTRL_VREF_BGOUTEN (1 << 2) /* Bit 2: Bandgap output enable */
#define SYSCTRL_VREF_CALIB_SHIFT (16) /* Bits 16-26: Bandgap voltage generator calibration */
#define SYSCTRL_VREF_CALIB_MASK (0x7ff << SYSCTRL_VREF_CALIB_SHIFT)
# define SYSCTRL_VREF_CALIB(n) ((n) << SYSCTRL_VREF_CALIB_SHIFT)
/* DPLL Control A register */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SYSCTRL_DPLLCTRLA_ENABLE (1 << 1) /* Bit 1: DPLL Enable */
# define SYSCTRL_DPLLCTRLA_RUNSTDBY (1 << 6) /* Bit 6: Run in Standby */
# define SYSCTRL_DPLLCTRLA_ONDEMAND (1 << 7) /* Bit 7: On Demand Clock Activation */
#endif
/* DPLL ratio control registers */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SYSCTRL_DPLLRATIO_LDR_SHIFT (0) /* Bits 0-11: Loop Divider Ratio */
# define SYSCTRL_DPLLRATIO_LDR_MASK (0xfff << SYSCTRL_DPLLRATIO_LDR_SHIFT)
# define SYSCTRL_DPLLRATIO_LDR(n) ((uint32_t)(n) << SYSCTRL_DPLLRATIO_LDR_SHIFT)
# define SYSCTRL_DPLLRATIO_LDRFRAC_SHIFT (16) /* Bits 16-19: Loop Divider Ratio Fractional Part */
# define SYSCTRL_DPLLRATIO_LDRFRAC_MASK (15 << SYSCTRL_DPLLRATIO_LDRFRAC_SHIFT)
# define SYSCTRL_DPLLRATIO_LDRFRAC(n) ((uint32_t)(n) << SYSCTRL_DPLLRATIO_LDRFRAC_SHIFT)
#endif
/* DPLL Control B register */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SYSCTRL_DPLLCTRLB_FILTER_SHIFT (0) /* Bits 0-1: Proportional Integral Filter Selection */
# define SYSCTRL_DPLLCTRLB_FILTER_MASK (3 << SYSCTRL_DPLLCTRLB_FILTER_SHIFT)
# define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT (0 << SYSCTRL_DPLLCTRLB_FILTER_SHIFT) /* Default filter mode */
# define SYSCTRL_DPLLCTRLB_FILTER_LBFILT (1 << SYSCTRL_DPLLCTRLB_FILTER_SHIFT) /* Low bandwidth filter */
# define SYSCTRL_DPLLCTRLB_FILTER_HBFILT (2 << SYSCTRL_DPLLCTRLB_FILTER_SHIFT) /* High bandwidth filter */
# define SYSCTRL_DPLLCTRLB_FILTER_HDFILT (3 << SYSCTRL_DPLLCTRLB_FILTER_SHIFT) /* High damping filter */
# define SYSCTRL_DPLLCTRLB_LPEN (1 << 2) /* Bit 2: Low-Power Enable */
# define SYSCTRL_DPLLCTRLB_WUF (1 << 3) /* Bit 3: Wake Up Fast */
# define SYSCTRL_DPLLCTRLB_REFCLK_SHIFT (4) /* Bits 4-5: Reference Clock Selection */
# define SYSCTRL_DPLLCTRLB_REFCLK_MASK (3 << SYSCTRL_DPLLCTRLB_REFCLK_SHIFT)
# define SYSCTRL_DPLLCTRLB_REFCLK_XOSC32 (0 << SYSCTRL_DPLLCTRLB_REFCLK_SHIFT) /* XOSC32 clock reference */
# define SYSCTRL_DPLLCTRLB_REFCLK_XOSC (1 << SYSCTRL_DPLLCTRLB_REFCLK_SHIFT) /* XOSC clock reference */
# define SYSCTRL_DPLLCTRLB_REFCLK_GCLKDPLL (2 << SYSCTRL_DPLLCTRLB_REFCLK_SHIFT) /* GCLK_DPLL clock reference */
# define SYSCTRL_DPLLCTRLB_LTIME_SHIFT (8) /* Bits 8-10: Lock Time */
# define SYSCTRL_DPLLCTRLB_LTIME_MASK (7 << SYSCTRL_DPLLCTRLB_LTIME_SHIFT)
# define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT (0 << SYSCTRL_DPLLCTRLB_LTIME_SHIFT) /* No time-out */
# define SYSCTRL_DPLLCTRLB_LTIME_8MS (4 << SYSCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no lock within 8 ms */
# define SYSCTRL_DPLLCTRLB_LTIME_9MS (5 << SYSCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no lock within 9 ms */
# define SYSCTRL_DPLLCTRLB_LTIME_10MS (6 << SYSCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no lock within 10 ms */
# define SYSCTRL_DPLLCTRLB_LTIME_11MS (7 << SYSCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no lock within 11 ms */
# define SYSCTRL_DPLLCTRLB_LBYPASS (1 << 12) /* Bit 12: Lock Bypass */
# define SYSCTRL_DPLLCTRLB_DIV_SHIFT (16) /* Bits 16-26: */
# define SYSCTRL_DPLLCTRLB_DIV_MASK (0x7ff << SYSCTRL_DPLLCTRLB_DIV_SHIFT)
# define SYSCTRL_DPLLCTRLB_DIV(n) ((uint32_t)(n) << SYSCTRL_DPLLCTRLB_DIV_SHIFT)
#endif
/* DPLL status register */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SYSCTRL_DPLLSTATUS_LOCK (1 << 0) /* Bit 0: DPLL Lock Status */
# define SYSCTRL_DPLLSTATUS_CLKRDY (1 << 1) /* Bit 1: Output Clock Ready */
# define SYSCTRL_DPLLSTATUS_ENABLE (1 << 2) /* Bit 2: DPLL Enable */
# define SYSCTRL_DPLLSTATUS_DIV (1 << 3) /* Bit 3: Divider Enable */
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SYSCTRL_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_tc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Matt Thompson <matt@extent3d.com>
*
* References:
* "Microchip SAMD21 datasheet"
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TC_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_ARCH_FAMILY_SAMD21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* TC register offsets ******************************************************/
#define SAM_TC_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_TC_READREQ_OFFSET 0x0002 /* Read request register */
#define SAM_TC_CTRLBCLR_OFFSET 0x0004 /* Control B clear register */
#define SAM_TC_CTRLBSET_OFFSET 0x0005 /* Control B clear register */
#define SAM_TC_CTRLC_OFFSET 0x0006 /* Control C register */
#define SAM_TC_DBGCTRL_OFFSET 0x0008 /* Debug control register */
#define SAM_TC_EVCTRL_OFFSET 0x000A /* Event control register */
#define SAM_TC_INTENCLR_OFFSET 0x000C /* Interrupt enable clear register */
#define SAM_TC_INTENSET_OFFSET 0x000D /* Interrupt enable set register */
#define SAM_TC_INTFLAG_OFFSET 0x000E /* Interrupt flag register */
#define SAM_TC_STATUS_OFFSET 0x000F /* Status register */
#define SAM_TC_COUNT_OFFSET 0x0010 /* Count register */
#define SAM_TC_CC0_OFFSET 0x0018 /* Capture Compare 0 register */
#define SAM_TC_CC1_OFFSET 0x001C /* Capture Compare 1 register */
/* TC register addresses ****************************************************/
#define SAM_TC3_CTRLA (SAM_TC3_BASE+SAM_TC_CTRLA_OFFSET)
#define SAM_TC3_READREQ (SAM_TC3_BASE+SAM_TC_READREQ_OFFSET)
#define SAM_TC3_CTRLBCLR (SAM_TC3_BASE+SAM_TC_CTRLBCLR_OFFSET)
#define SAM_TC3_CTRLBSET (SAM_TC3_BASE+SAM_TC_CTRLBSET_OFFSET)
#define SAM_TC3_CTRLC (SAM_TC3_BASE+SAM_TC_CTRLC_OFFSET)
#define SAM_TC3_DBGCTRL (SAM_TC3_BASE+SAM_TC_DBGCTRL_OFFSET)
#define SAM_TC3_EVCTRL (SAM_TC3_BASE+SAM_TC_EVCTRL_OFFSET)
#define SAM_TC3_INTENCLR (SAM_TC3_BASE+SAM_TC_INTENCLR_OFFSET)
#define SAM_TC3_INTENSET (SAM_TC3_BASE+SAM_TC_INTENSET_OFFSET)
#define SAM_TC3_INTFLAG (SAM_TC3_BASE+SAM_TC_INTFLAG_OFFSET)
#define SAM_TC3_STATUS (SAM_TC3_BASE+SAM_TC_STATUS_OFFSET)
#define SAM_TC3_COUNT (SAM_TC3_BASE+SAM_TC_COUNT_OFFSET)
#define SAM_TC3_CC0 (SAM_TC3_BASE+SAM_TC_CC0_OFFSET)
#define SAM_TC3_CC1 (SAM_TC3_BASE+SAM_TC_CC1_OFFSET)
#define SAM_TC4_CTRLA (SAM_TC4_BASE+SAM_TC_CTRLA_OFFSET)
#define SAM_TC4_READREQ (SAM_TC4_BASE+SAM_TC_READREQ_OFFSET)
#define SAM_TC4_CTRLBCLR (SAM_TC4_BASE+SAM_TC_CTRLBCLR_OFFSET)
#define SAM_TC4_CTRLBSET (SAM_TC4_BASE+SAM_TC_CTRLBSET_OFFSET)
#define SAM_TC4_CTRLC (SAM_TC4_BASE+SAM_TC_CTRLC_OFFSET)
#define SAM_TC4_DBGCTRL (SAM_TC4_BASE+SAM_TC_DBGCTRL_OFFSET)
#define SAM_TC4_EVCTRL (SAM_TC4_BASE+SAM_TC_EVCTRL_OFFSET)
#define SAM_TC4_INTENCLR (SAM_TC4_BASE+SAM_TC_INTENCLR_OFFSET)
#define SAM_TC4_INTENSET (SAM_TC4_BASE+SAM_TC_INTENSET_OFFSET)
#define SAM_TC4_INTFLAG (SAM_TC4_BASE+SAM_TC_INTFLAG_OFFSET)
#define SAM_TC4_STATUS (SAM_TC4_BASE+SAM_TC_STATUS_OFFSET)
#define SAM_TC4_COUNT (SAM_TC4_BASE+SAM_TC_COUNT_OFFSET)
#define SAM_TC4_CC0 (SAM_TC4_BASE+SAM_TC_CC0_OFFSET)
#define SAM_TC4_CC1 (SAM_TC4_BASE+SAM_TC_CC1_OFFSET)
#define SAM_TC5_CTRLA (SAM_TC5_BASE+SAM_TC_CTRLA_OFFSET)
#define SAM_TC5_READREQ (SAM_TC5_BASE+SAM_TC_READREQ_OFFSET)
#define SAM_TC5_CTRLBCLR (SAM_TC5_BASE+SAM_TC_CTRLBCLR_OFFSET)
#define SAM_TC5_CTRLBSET (SAM_TC5_BASE+SAM_TC_CTRLBSET_OFFSET)
#define SAM_TC5_CTRLC (SAM_TC5_BASE+SAM_TC_CTRLC_OFFSET)
#define SAM_TC5_DBGCTRL (SAM_TC5_BASE+SAM_TC_DBGCTRL_OFFSET)
#define SAM_TC5_EVCTRL (SAM_TC5_BASE+SAM_TC_EVCTRL_OFFSET)
#define SAM_TC5_INTENCLR (SAM_TC5_BASE+SAM_TC_INTENCLR_OFFSET)
#define SAM_TC5_INTENSET (SAM_TC5_BASE+SAM_TC_INTENSET_OFFSET)
#define SAM_TC5_INTFLAG (SAM_TC5_BASE+SAM_TC_INTFLAG_OFFSET)
#define SAM_TC5_STATUS (SAM_TC5_BASE+SAM_TC_STATUS_OFFSET)
#define SAM_TC5_COUNT (SAM_TC5_BASE+SAM_TC_COUNT_OFFSET)
#define SAM_TC5_CC0 (SAM_TC5_BASE+SAM_TC_CC0_OFFSET)
#define SAM_TC5_CC1 (SAM_TC5_BASE+SAM_TC_CC1_OFFSET)
#define SAM_TC6_CTRLA (SAM_TC6_BASE+SAM_TC_CTRLA_OFFSET)
#define SAM_TC6_READREQ (SAM_TC6_BASE+SAM_TC_READREQ_OFFSET)
#define SAM_TC6_CTRLBCLR (SAM_TC6_BASE+SAM_TC_CTRLBCLR_OFFSET)
#define SAM_TC6_CTRLBSET (SAM_TC6_BASE+SAM_TC_CTRLBSET_OFFSET)
#define SAM_TC6_CTRLC (SAM_TC6_BASE+SAM_TC_CTRLC_OFFSET)
#define SAM_TC6_DBGCTRL (SAM_TC6_BASE+SAM_TC_DBGCTRL_OFFSET)
#define SAM_TC6_EVCTRL (SAM_TC6_BASE+SAM_TC_EVCTRL_OFFSET)
#define SAM_TC6_INTENCLR (SAM_TC6_BASE+SAM_TC_INTENCLR_OFFSET)
#define SAM_TC6_INTENSET (SAM_TC6_BASE+SAM_TC_INTENSET_OFFSET)
#define SAM_TC6_INTFLAG (SAM_TC6_BASE+SAM_TC_INTFLAG_OFFSET)
#define SAM_TC6_STATUS (SAM_TC6_BASE+SAM_TC_STATUS_OFFSET)
#define SAM_TC6_COUNT (SAM_TC6_BASE+SAM_TC_COUNT_OFFSET)
#define SAM_TC6_CC0 (SAM_TC6_BASE+SAM_TC_CC0_OFFSET)
#define SAM_TC6_CC1 (SAM_TC6_BASE+SAM_TC_CC1_OFFSET)
#define SAM_TC7_CTRLA (SAM_TC7_BASE+SAM_TC_CTRLA_OFFSET)
#define SAM_TC7_READREQ (SAM_TC7_BASE+SAM_TC_READREQ_OFFSET)
#define SAM_TC7_CTRLBCLR (SAM_TC7_BASE+SAM_TC_CTRLBCLR_OFFSET)
#define SAM_TC7_CTRLBSET (SAM_TC7_BASE+SAM_TC_CTRLBSET_OFFSET)
#define SAM_TC7_CTRLC (SAM_TC7_BASE+SAM_TC_CTRLC_OFFSET)
#define SAM_TC7_DBGCTRL (SAM_TC7_BASE+SAM_TC_DBGCTRL_OFFSET)
#define SAM_TC7_EVCTRL (SAM_TC7_BASE+SAM_TC_EVCTRL_OFFSET)
#define SAM_TC7_INTENCLR (SAM_TC7_BASE+SAM_TC_INTENCLR_OFFSET)
#define SAM_TC7_INTENSET (SAM_TC7_BASE+SAM_TC_INTENSET_OFFSET)
#define SAM_TC7_INTFLAG (SAM_TC7_BASE+SAM_TC_INTFLAG_OFFSET)
#define SAM_TC7_STATUS (SAM_TC7_BASE+SAM_TC_STATUS_OFFSET)
#define SAM_TC7_COUNT (SAM_TC7_BASE+SAM_TC_COUNT_OFFSET)
#define SAM_TC7_CC0 (SAM_TC7_BASE+SAM_TC_CC0_OFFSET)
#define SAM_TC7_CC1 (SAM_TC7_BASE+SAM_TC_CC1_OFFSET)
/* TC register bit definitions **********************************************/
/* Control A register */
#define TC_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
#define TC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
#define TC_CTRLA_MODE_SHIFT (2)
#define TC_CTRLA_MODE_MASK (3 << TC_CTRLA_MODE_SHIFT)
# define TC_CTRLA_MODE_COUNT16 (0 << TC_CTRLA_MODE_SHIFT)
# define TC_CTRLA_MODE_COUNT8 (1 << TC_CTRLA_MODE_SHIFT)
# define TC_CTRLA_MODE_COUNT32 (2 << TC_CTRLA_MODE_SHIFT)
#define TC_CTRLA_WAVEGEN_SHIFT (5)
#define TC_CTRLA_WAVEGEN_MASK (3 << TC_CTRLA_WAVEGEN_SHIFT)
# define TC_CTRLA_WAVEGEN_NFRQ (0 << TC_CTRLA_WAVEGEN_SHIFT)
# define TC_CTRLA_WAVEGEN_MFRQ (1 << TC_CTRLA_WAVEGEN_SHIFT)
# define TC_CTRLA_WAVEGEN_NPWM (2 << TC_CTRLA_WAVEGEN_SHIFT)
# define TC_CTRLA_WAVEGEN_MPWM (3 << TC_CTRLA_WAVEGEN_SHIFT)
#define TC_CTRLA_PRESCALER_SHIFT (8)
#define TC_CTRLA_PRESCALER_MASK (7 << TC_CTRLA_PRESCALER_SHIFT)
# define TC_CTRLA_PRESCALER_DIV1 (0 << TC_CTRLA_PRESCALER_SHIFT)
# define TC_CTRLA_PRESCALER_DIV2 (1 << TC_CTRLA_PRESCALER_SHIFT)
# define TC_CTRLA_PRESCALER_DIV4 (2 << TC_CTRLA_PRESCALER_SHIFT)
# define TC_CTRLA_PRESCALER_DIV8 (3 << TC_CTRLA_PRESCALER_SHIFT)
# define TC_CTRLA_PRESCALER_DIV16 (4 << TC_CTRLA_PRESCALER_SHIFT)
# define TC_CTRLA_PRESCALER_DIV64 (5 << TC_CTRLA_PRESCALER_SHIFT)
# define TC_CTRLA_PRESCALER_DIV256 (6 << TC_CTRLA_PRESCALER_SHIFT)
# define TC_CTRLA_PRESCALER_DIV1024 (7 << TC_CTRLA_PRESCALER_SHIFT)
#define TC_CTRLA_RUNSTDBY (1 << 11)
#define TC_CTRLA_PRESCSYNC_SHIFT (12)
#define TC_CTRLA_PRESCSYNC_MASK (3 << TC_CTRLA_PRESCSYNC_SHIFT)
# define TC_CTRLA_PRESCSYNC_GCLK (0 << TC_CTRLA_PRESCSYNC_SHIFT)
# define TC_CTRLA_PRESCSYNC_PRESC (1 << TC_CTRLA_PRESCSYNC_SHIFT)
# define TC_CTRLA_PRESCSYNC_RESYNC (2 << TC_CTRLA_PRESCSYNC_SHIFT)
/* Read Request register */
#define TC_READREQ_ADDR_SHIFT (0)
#define TC_READREQ_ADDR_MASK (0x1F << TC_READREQ_ADDR_SHIFT)
#define TC_READREQ_RCONT (1 << 14)
#define TC_READREQ_RREQ (1 << 15)
/* Control B Set/Clear register */
#define TC_CTRLB_DIR (1 << 0)
#define TC_CTRLB_ONESHOT (1 << 2)
#define TC_CTRLB_CMD_SHIFT (6)
#define TC_CTRLB_CMD_MASK (3 << TC_CTRLB_CMD_SHIFT)
# define TC_CTRLB_CMD_NONE (0 << TC_CTRLB_CMD_SHIFT)
# define TC_CTRLB_CMD_RETRIGGER (1 << TC_CTRLB_CMD_SHIFT)
# define TC_CTRLB_CMD_STOP (2 << TC_CTRLB_CMD_SHIFT)
/* Control C register */
#define TC_CTRLC_INVEN0 (1 << 0)
#define TC_CTRLC_INVEN1 (1 << 1)
#define TC_CTRLC_CPTEN0 (1 << 4)
#define TC_CTRLC_CPTEN1 (1 << 5)
/* Debug control register */
#define TC_DBGCTRL_DBGRUN (1 << 0)
/* Event control register */
#define TC_EVCTRL_EVACT_SHIFT (0)
#define TC_EVCTRL_EVACT_MASK (7 << TC_EVCTRL_EVACT_SHIFT)
# define TC_EVCTRL_EVACT_OFF (0 << TC_EVCTRL_EVACT_SHIFT)
# define TC_EVCTRL_EVACT_RETRIGGER (1 << TC_EVCTRL_EVACT_SHIFT)
# define TC_EVCTRL_EVACT_COUNT (2 << TC_EVCTRL_EVACT_SHIFT)
# define TC_EVCTRL_EVACT_START (3 << TC_EVCTRL_EVACT_SHIFT)
# define TC_EVCTRL_EVACT_PPW (5 << TC_EVCTRL_EVACT_SHIFT)
# define TC_EVCTRL_EVACT_PWP (6 << TC_EVCTRL_EVACT_SHIFT)
#define TC_EVCTRL_TCINV (1 << 4)
#define TC_EVCTRL_TCEI (1 << 5)
#define TC_EVCTRL_OVFEO (1 << 8)
#define TC_EVCTRL_MCEO0 (1 << 12)
#define TC_EVCTRL_MCEO1 (1 << 13)
/* Interrupt register bits */
#define TC_INT_OVF (1 << 0)
#define TC_INT_ERR (1 << 1)
#define TC_INT_SYNCRDY (1 << 3)
#define TC_INT_MC0 (1 << 4)
#define TC_INT_MC1 (1 << 5)
/* Status register */
#define TC_STATUS_STOP (1 << 3)
#define TC_STATUS_SLAVE (1 << 4)
#define TC_STATUS_SYNCBUSY (1 << 7)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TC_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_tcc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Matt Thompson <matt@extent3d.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* References:
* "Microchip SAMD21 datasheet"
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TCC_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TCC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_ARCH_FAMILY_SAMD21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* TCC register offsets *****************************************************/
#define SAM_TCC_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_TCC_CTRLBCLR_OFFSET 0x0004 /* Control B clear register */
#define SAM_TCC_CTRLBSET_OFFSET 0x0005 /* Control B clear register */
#define SAM_TCC_SYNCBUSY_OFFSET 0x0008 /* Sync Busy register */
#define SAM_TCC_FCTRLA_OFFSET 0x000C /* Fault control A register */
#define SAM_TCC_FCTRLB_OFFSET 0x0010 /* Fault control B register */
#define SAM_TCC_WEXCTRL_OFFSET 0x0014 /* Waveform extension control register */
#define SAM_TCC_DRVCTRL_OFFSET 0x0018 /* Event control register */
#define SAM_TCC_DBGCTRL_OFFSET 0x001E /* Debug control register */
#define SAM_TCC_EVCTRL_OFFSET 0x0020 /* Event control register */
#define SAM_TCC_INTENCLR_OFFSET 0x0024 /* Interrupt enable clear register */
#define SAM_TCC_INTENSET_OFFSET 0x0028 /* Interrupt enable set register */
#define SAM_TCC_INTFLAG_OFFSET 0x002C /* Interrupt flag register */
#define SAM_TCC_STATUS_OFFSET 0x0030 /* Status register */
#define SAM_TCC_COUNT_OFFSET 0x0034 /* Count register */
#define SAM_TCC_PATT_OFFSET 0x0038 /* Pattern register */
#define SAM_TCC_WAVE_OFFSET 0x003C /* Waveform register */
#define SAM_TCC_PER_OFFSET 0x0040 /* Period register */
#define SAM_TCC_CC0_OFFSET 0x0044 /* Capture Compare 0 register */
#define SAM_TCC_CC1_OFFSET 0x0048 /* Capture Compare 1 register */
#define SAM_TCC_CC2_OFFSET 0x004C /* Capture Compare 2 register */
#define SAM_TCC_CC3_OFFSET 0x0050 /* Capture Compare 3 register */
#define SAM_TCC_PATTB_OFFSET 0x0064 /* Capture Compare 3 register */
#define SAM_TCC_WAVEB_OFFSET 0x0068 /* Capture Compare 3 register */
#define SAM_TCC_PERB_OFFSET 0x006C /* Capture Compare 3 register */
#define SAM_TCC_CCB0_OFFSET 0x0070 /* Capture Compare B0 register */
#define SAM_TCC_CCB1_OFFSET 0x0074 /* Capture Compare B0 register */
#define SAM_TCC_CCB2_OFFSET 0x0078 /* Capture Compare B0 register */
#define SAM_TCC_CCB3_OFFSET 0x007C /* Capture Compare B0 register */
/* TC register addresses ****************************************************/
#define SAM_TCC0_CTRLA (SAM_TCC0_BASE+SAM_TCC_CTRLA_OFFSET)
#define SAM_TCC0_CTRLBCLR (SAM_TCC0_BASE+SAM_TCC_CTRLBCLR_OFFSET)
#define SAM_TCC0_CTRLBSET (SAM_TCC0_BASE+SAM_TCC_CTRLBSET_OFFSET)
#define SAM_TCC0_SYNCBUSY (SAM_TCC0_BASE+SAM_TCC_SYNCBUSY_OFFSET)
#define SAM_TCC0_FCTRLA (SAM_TCC0_BASE+SAM_TCC_FCTRLA_OFFSET)
#define SAM_TCC0_FCTRLB (SAM_TCC0_BASE+SAM_TCC_FCTRLB_OFFSET)
#define SAM_TCC0_WEXCTRL (SAM_TCC0_BASE+SAM_TCC_WEXCTRL_OFFSET)
#define SAM_TCC0_DRVCTRL (SAM_TCC0_BASE+SAM_TCC_DRVCTRL_OFFSET)
#define SAM_TCC0_DBGCTRL (SAM_TCC0_BASE+SAM_TCC_DBGCTRL_OFFSET)
#define SAM_TCC0_EVCTRL (SAM_TCC0_BASE+SAM_TCC_EVCTRL_OFFSET)
#define SAM_TCC0_INTENCLR (SAM_TCC0_BASE+SAM_TCC_INTENCLR_OFFSET)
#define SAM_TCC0_INTENSET (SAM_TCC0_BASE+SAM_TCC_INTENSET_OFFSET)
#define SAM_TCC0_INTFLAG (SAM_TCC0_BASE+SAM_TCC_INTFLAG_OFFSET)
#define SAM_TCC0_STATUS (SAM_TCC0_BASE+SAM_TCC_STATUS_OFFSET)
#define SAM_TCC0_COUNT (SAM_TCC0_BASE+SAM_TCC_COUNT_OFFSET)
#define SAM_TCC0_PATT (SAM_TCC0_BASE+SAM_TCC_PATT_OFFSET)
#define SAM_TCC0_WAVE (SAM_TCC0_BASE+SAM_TCC_WAVE_OFFSET)
#define SAM_TCC0_PER (SAM_TCC0_BASE+SAM_TCC_PER_OFFSET)
#define SAM_TCC0_CC0 (SAM_TCC0_BASE+SAM_TCC_CC0_OFFSET)
#define SAM_TCC0_CC1 (SAM_TCC0_BASE+SAM_TCC_CC1_OFFSET)
#define SAM_TCC0_CC2 (SAM_TCC0_BASE+SAM_TCC_CC2_OFFSET)
#define SAM_TCC0_CC3 (SAM_TCC0_BASE+SAM_TCC_CC3_OFFSET)
#define SAM_TCC0_PATTB (SAM_TCC0_BASE+SAM_TCC_PATTB_OFFSET)
#define SAM_TCC0_WAVEB (SAM_TCC0_BASE+SAM_TCC_WAVEB_OFFSET)
#define SAM_TCC0_PERB (SAM_TCC0_BASE+SAM_TCC_PERB_OFFSET)
#define SAM_TCC0_CCB0 (SAM_TCC0_BASE+SAM_TCC_CCB0_OFFSET)
#define SAM_TCC0_CCB1 (SAM_TCC0_BASE+SAM_TCC_CCB1_OFFSET)
#define SAM_TCC0_CCB2 (SAM_TCC0_BASE+SAM_TCC_CCB2_OFFSET)
#define SAM_TCC0_CCB3 (SAM_TCC0_BASE+SAM_TCC_CCB3_OFFSET)
#define SAM_TCC1_CTRLA (SAM_TCC1_BASE+SAM_TCC_CTRLA_OFFSET)
#define SAM_TCC1_CTRLBCLR (SAM_TCC1_BASE+SAM_TCC_CTRLBCLR_OFFSET)
#define SAM_TCC1_CTRLBSET (SAM_TCC1_BASE+SAM_TCC_CTRLBSET_OFFSET)
#define SAM_TCC1_SYNCBUSY (SAM_TCC1_BASE+SAM_TCC_SYNCBUSY_OFFSET)
#define SAM_TCC1_FCTRLA (SAM_TCC1_BASE+SAM_TCC_FCTRLA_OFFSET)
#define SAM_TCC1_FCTRLB (SAM_TCC1_BASE+SAM_TCC_FCTRLB_OFFSET)
#define SAM_TCC1_WEXCTRL (SAM_TCC1_BASE+SAM_TCC_WEXCTRL_OFFSET)
#define SAM_TCC1_DRVCTRL (SAM_TCC1_BASE+SAM_TCC_DRVCTRL_OFFSET)
#define SAM_TCC1_DBGCTRL (SAM_TCC1_BASE+SAM_TCC_DBGCTRL_OFFSET)
#define SAM_TCC1_EVCTRL (SAM_TCC1_BASE+SAM_TCC_EVCTRL_OFFSET)
#define SAM_TCC1_INTENCLR (SAM_TCC1_BASE+SAM_TCC_INTENCLR_OFFSET)
#define SAM_TCC1_INTENSET (SAM_TCC1_BASE+SAM_TCC_INTENSET_OFFSET)
#define SAM_TCC1_INTFLAG (SAM_TCC1_BASE+SAM_TCC_INTFLAG_OFFSET)
#define SAM_TCC1_STATUS (SAM_TCC1_BASE+SAM_TCC_STATUS_OFFSET)
#define SAM_TCC1_COUNT (SAM_TCC1_BASE+SAM_TCC_COUNT_OFFSET)
#define SAM_TCC1_PATT (SAM_TCC1_BASE+SAM_TCC_PATT_OFFSET)
#define SAM_TCC1_WAVE (SAM_TCC1_BASE+SAM_TCC_WAVE_OFFSET)
#define SAM_TCC1_PER (SAM_TCC1_BASE+SAM_TCC_PER_OFFSET)
#define SAM_TCC1_CC0 (SAM_TCC1_BASE+SAM_TCC_CC0_OFFSET)
#define SAM_TCC1_CC1 (SAM_TCC1_BASE+SAM_TCC_CC1_OFFSET)
#define SAM_TCC1_CC2 (SAM_TCC1_BASE+SAM_TCC_CC2_OFFSET)
#define SAM_TCC1_CC3 (SAM_TCC1_BASE+SAM_TCC_CC3_OFFSET)
#define SAM_TCC1_PATTB (SAM_TCC1_BASE+SAM_TCC_PATTB_OFFSET)
#define SAM_TCC1_WAVEB (SAM_TCC1_BASE+SAM_TCC_WAVEB_OFFSET)
#define SAM_TCC1_PERB (SAM_TCC1_BASE+SAM_TCC_PERB_OFFSET)
#define SAM_TCC1_CCB0 (SAM_TCC1_BASE+SAM_TCC_CCB0_OFFSET)
#define SAM_TCC1_CCB1 (SAM_TCC1_BASE+SAM_TCC_CCB1_OFFSET)
#define SAM_TCC1_CCB2 (SAM_TCC1_BASE+SAM_TCC_CCB2_OFFSET)
#define SAM_TCC1_CCB3 (SAM_TCC1_BASE+SAM_TCC_CCB3_OFFSET)
#define SAM_TCC2_CTRLA (SAM_TCC2_BASE+SAM_TCC_CTRLA_OFFSET)
#define SAM_TCC2_CTRLBCLR (SAM_TCC2_BASE+SAM_TCC_CTRLBCLR_OFFSET)
#define SAM_TCC2_CTRLBSET (SAM_TCC2_BASE+SAM_TCC_CTRLBSET_OFFSET)
#define SAM_TCC2_SYNCBUSY (SAM_TCC2_BASE+SAM_TCC_SYNCBUSY_OFFSET)
#define SAM_TCC2_FCTRLA (SAM_TCC2_BASE+SAM_TCC_FCTRLA_OFFSET)
#define SAM_TCC2_FCTRLB (SAM_TCC2_BASE+SAM_TCC_FCTRLB_OFFSET)
#define SAM_TCC2_WEXCTRL (SAM_TCC2_BASE+SAM_TCC_WEXCTRL_OFFSET)
#define SAM_TCC2_DRVCTRL (SAM_TCC2_BASE+SAM_TCC_DRVCTRL_OFFSET)
#define SAM_TCC2_DBGCTRL (SAM_TCC2_BASE+SAM_TCC_DBGCTRL_OFFSET)
#define SAM_TCC2_EVCTRL (SAM_TCC2_BASE+SAM_TCC_EVCTRL_OFFSET)
#define SAM_TCC2_INTENCLR (SAM_TCC2_BASE+SAM_TCC_INTENCLR_OFFSET)
#define SAM_TCC2_INTENSET (SAM_TCC2_BASE+SAM_TCC_INTENSET_OFFSET)
#define SAM_TCC2_INTFLAG (SAM_TCC2_BASE+SAM_TCC_INTFLAG_OFFSET)
#define SAM_TCC2_STATUS (SAM_TCC2_BASE+SAM_TCC_STATUS_OFFSET)
#define SAM_TCC2_COUNT (SAM_TCC2_BASE+SAM_TCC_COUNT_OFFSET)
#define SAM_TCC2_PATT (SAM_TCC2_BASE+SAM_TCC_PATT_OFFSET)
#define SAM_TCC2_WAVE (SAM_TCC2_BASE+SAM_TCC_WAVE_OFFSET)
#define SAM_TCC2_PER (SAM_TCC2_BASE+SAM_TCC_PER_OFFSET)
#define SAM_TCC2_CC0 (SAM_TCC2_BASE+SAM_TCC_CC0_OFFSET)
#define SAM_TCC2_CC1 (SAM_TCC2_BASE+SAM_TCC_CC1_OFFSET)
#define SAM_TCC2_CC2 (SAM_TCC2_BASE+SAM_TCC_CC2_OFFSET)
#define SAM_TCC2_CC3 (SAM_TCC2_BASE+SAM_TCC_CC3_OFFSET)
#define SAM_TCC2_PATTB (SAM_TCC2_BASE+SAM_TCC_PATTB_OFFSET)
#define SAM_TCC2_WAVEB (SAM_TCC2_BASE+SAM_TCC_WAVEB_OFFSET)
#define SAM_TCC2_PERB (SAM_TCC2_BASE+SAM_TCC_PERB_OFFSET)
#define SAM_TCC2_CCB0 (SAM_TCC2_BASE+SAM_TCC_CCB0_OFFSET)
#define SAM_TCC2_CCB1 (SAM_TCC2_BASE+SAM_TCC_CCB1_OFFSET)
#define SAM_TCC2_CCB2 (SAM_TCC2_BASE+SAM_TCC_CCB2_OFFSET)
#define SAM_TCC2_CCB3 (SAM_TCC2_BASE+SAM_TCC_CCB3_OFFSET)
/* TC register bit definitions **********************************************/
/* Control A register */
#define TCC_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
#define TCC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
#define TCC_CTRLA_RES_SHIFT (5)
#define TCC_CTRLA_RES_MASK (3 << TCC_CTRLA_RES_SHIFT)
# define TCC_CTRLA_RES_NONE (0 << TCC_CTRLA_RES_SHIFT)
# define TCC_CTRLA_RES_DITH4 (1 << TCC_CTRLA_RES_SHIFT)
# define TCC_CTRLA_RES_DITH5 (2 << TCC_CTRLA_RES_SHIFT)
# define TCC_CTRLA_RES_DITH6 (3 << TCC_CTRLA_RES_SHIFT)
#define TCC_CTRLA_PRESCALER_SHIFT (8)
#define TCC_CTRLA_PRESCALER_MASK (7 << TCC_CTRLA_PRESCALER_SHIFT)
# define TCC_CTRLA_PRESCALER_DIV1 (0 << TCC_CTRLA_PRESCALER_SHIFT)
# define TCC_CTRLA_PRESCALER_DIV2 (1 << TCC_CTRLA_PRESCALER_SHIFT)
# define TCC_CTRLA_PRESCALER_DIV4 (2 << TCC_CTRLA_PRESCALER_SHIFT)
# define TCC_CTRLA_PRESCALER_DIV8 (3 << TCC_CTRLA_PRESCALER_SHIFT)
# define TCC_CTRLA_PRESCALER_DIV16 (4 << TCC_CTRLA_PRESCALER_SHIFT)
# define TCC_CTRLA_PRESCALER_DIV64 (5 << TCC_CTRLA_PRESCALER_SHIFT)
# define TCC_CTRLA_PRESCALER_DIV256 (6 << TCC_CTRLA_PRESCALER_SHIFT)
# define TCC_CTRLA_PRESCALER_DIV1024 (7 << TCC_CTRLA_PRESCALER_SHIFT)
#define TCC_CTRLA_RUNSTDBY (1 << 11)
#define TCC_CTRLA_PRESCSYNC_SHIFT (12)
#define TCC_CTRLA_PRESCSYNC_MASK (3 << TCC_CTRLA_PRESCSYNC_SHIFT)
# define TCC_CTRLA_PRESCSYNC_GCLK (0 << TCC_CTRLA_PRESCSYNC_SHIFT)
# define TCC_CTRLA_PRESCSYNC_PRESC (1 << TCC_CTRLA_PRESCSYNC_SHIFT)
# define TCC_CTRLA_PRESCSYNC_RESYNC (2 << TCC_CTRLA_PRESCSYNC_SHIFT)
#define TCC_CTRLA_ALOCK (1 << 14)
#define TCC_CTRLA_CPTEN0 (1 << 24)
#define TCC_CTRLA_CPTEN1 (1 << 25)
#define TCC_CTRLA_CPTEN2 (1 << 26)
#define TCC_CTRLA_CPTEN3 (1 << 27)
/* Control B Set/Clear register */
#define TCC_CTRLB_DIR (1 << 0)
#define TCC_CTRLB_LUPD (1 << 1)
#define TCC_CTRLB_ONESHOT (1 << 2)
#define TCC_CTRLB_IDXCMD_SHIFT (3)
#define TCC_CTRLB_IDXCMD_MASK (3 << TCC_CTRLB_IDXCMD_SHIFT)
# define TCC_CTRLB_IDXCMD_DISABLE (0 << TCC_CTRLB_IDXCMD_SHIFT)
# define TCC_CTRLB_IDXCMD_SET (1 << TCC_CTRLB_IDXCMD_SHIFT)
# define TCC_CTRLB_IDXCMD_CLEAR (2 << TCC_CTRLB_IDXCMD_SHIFT)
# define TCC_CTRLB_IDXCMD_HOLD (3 << TCC_CTRLB_IDXCMD_SHIFT)
#define TCC_CTRLB_CMD_SHIFT (6)
#define TCC_CTRLB_CMD_MASK (7 << TCC_CTRLB_CMD_SHIFT)
# define TCC_CTRLB_CMD_NONE (0 << TCC_CTRLB_CMD_SHIFT)
# define TCC_CTRLB_CMD_RETRIGGER (1 << TCC_CTRLB_CMD_SHIFT)
# define TCC_CTRLB_CMD_STOP (2 << TCC_CTRLB_CMD_SHIFT)
# define TCC_CTRLB_CMD_UPDATE (3 << TCC_CTRLB_CMD_SHIFT)
# define TCC_CTRLB_CMD_READSYNC (4 << TCC_CTRLB_CMD_SHIFT)
/* Sync Busy register */
#define TCC_SYNCBUSY_SWRST (1 << 0)
#define TCC_SYNCBUSY_ENABLE (1 << 1)
#define TCC_SYNCBUSY_CTRLB (1 << 2)
#define TCC_SYNCBUSY_STATUS (1 << 3)
#define TCC_SYNCBUSY_COUNT (1 << 4)
#define TCC_SYNCBUSY_PATT (1 << 5)
#define TCC_SYNCBUSY_WAVE (1 << 6)
#define TCC_SYNCBUSY_PER (1 << 7)
#define TCC_SYNCBUSY_CC0 (1 << 8)
#define TCC_SYNCBUSY_CC1 (1 << 9)
#define TCC_SYNCBUSY_CC2 (1 << 10)
#define TCC_SYNCBUSY_CC3 (1 << 11)
#define TCC_SYNCBUSY_PATTB (1 << 16)
#define TCC_SYNCBUSY_WAVEB (1 << 17)
#define TCC_SYNCBUSY_PERB (1 << 18)
#define TCC_SYNCBUSY_CCB0 (1 << 19)
#define TCC_SYNCBUSY_CCB1 (1 << 20)
#define TCC_SYNCBUSY_CCB2 (1 << 21)
#define TCC_SYNCBUSY_CCB3 (1 << 22)
/* Fault Control A and B */
#define TCC_FCTRL_SRC_SHIFT (0)
#define TCC_FCTRL_SRC_MASK (3 << TCC_FCTRL_SRC_SHIFT)
# define TCC_FCTRL_SRC_DISABLE (0 << TCC_FCTRL_SRC_SHIFT)
# define TCC_FCTRL_SRC_ENABLE (1 << TCC_FCTRL_SRC_SHIFT)
# define TCC_FCTRL_SRC_INVERT (2 << TCC_FCTRL_SRC_SHIFT)
# define TCC_FCTRL_SRC_ALTFAULT (3 << TCC_FCTRL_SRC_SHIFT)
#define TCC_FCTRL_KEEP (1 << 3)
#define TCC_FCTRL_QUAL (1 << 4)
#define TCC_FCTRL_BLANK_SHIFT (5)
#define TCC_FCTRL_BLANK_MASK (3 << TCC_FCTRL_BLANK_SHIFT)
# define TCC_FCTRL_BLANK_START (0 << TCC_FCTRL_BLANK_SHIFT)
# define TCC_FCTRL_BLANK_RISE (1 << TCC_FCTRL_BLANK_SHIFT)
# define TCC_FCTRL_BLANK_FALL (2 << TCC_FCTRL_BLANK_SHIFT)
# define TCC_FCTRL_BLANK_BOTH (3 << TCC_FCTRL_BLANK_SHIFT)
#define TCC_FCTRL_RESTART (1 << 7)
#define TCC_FCTRL_HALT_SHIFT (8)
#define TCC_FCTRL_HALT_MASK (3 << TCC_FCTRL_HALT_SHIFT)
# define TCC_FCTRL_HALT_DISABLE (0 << TCC_FCTRL_HALT_SHIFT)
# define TCC_FCTRL_HALT_HW (1 << TCC_FCTRL_HALT_SHIFT)
# define TCC_FCTRL_HALT_SW (2 << TCC_FCTRL_HALT_SHIFT)
# define TCC_FCTRL_HALT_NR (3 << TCC_FCTRL_HALT_SHIFT)
#define TCC_FCTRL_CHSEL_SHIFT (10)
#define TCC_FCTRL_CHSEL_MASK (3 << TCC_FCTRL_CHSEL_SHIFT)
# define TCC_FCTRL_CHSEL_CC0 (0 << TCC_FCTRL_CHSEL_SHIFT)
# define TCC_FCTRL_CHSEL_CC1 (1 << TCC_FCTRL_CHSEL_SHIFT)
# define TCC_FCTRL_CHSEL_CC2 (2 << TCC_FCTRL_CHSEL_SHIFT)
# define TCC_FCTRL_CHSEL_CC3 (3 << TCC_FCTRL_CHSEL_SHIFT)
#define TCC_FCTRL_CAPTURE_SHIFT (12)
#define TCC_FCTRL_CAPTURE_MASK (7 << TCC_FCTRL_CAPTURE_SHIFT)
# define TCC_FCTRL_CAPTURE_DISABLE (0 << TCC_FCTRL_CAPTURE_SHIFT)
# define TCC_FCTRL_CAPTURE_CAPT (1 << TCC_FCTRL_CAPTURE_SHIFT)
# define TCC_FCTRL_CAPTURE_CAPTMIN (2 << TCC_FCTRL_CAPTURE_SHIFT)
# define TCC_FCTRL_CAPTURE_CAPTMAX (3 << TCC_FCTRL_CAPTURE_SHIFT)
# define TCC_FCTRL_CAPTURE_LOCMIN (4 << TCC_FCTRL_CAPTURE_SHIFT)
# define TCC_FCTRL_CAPTURE_LOCMAX (5 << TCC_FCTRL_CAPTURE_SHIFT)
# define TCC_FCTRL_CAPTURE_DERIV0 (6 << TCC_FCTRL_CAPTURE_SHIFT)
#define TCC_FCTRL_BLANKVAL_SHIFT (16)
#define TCC_FCTRL_BLANKVAL_MASK (0xff << TCC_FCTRL_BLANKVAL_SHIFT)
#define TCC_FCTRL_FILTERVAL_SHIFT (24)
#define TCC_FCTRL_FILTERVAL_MASK (0xf << TCC_FCTRL_FILTERVAL_SHIFT)
/* Waveform Extension Control register */
#define TCC_WEXCTRL_OTMX_SHIFT (0)
#define TCC_WEXCTRL_OTMX_MASK (3 << TCC_WEXCTRL_OTMX_SHIFT)
#define TCC_WEXCTRL_DTIEN0 (1 << 8)
#define TCC_WEXCTRL_DTIEN1 (1 << 9)
#define TCC_WEXCTRL_DTIEN2 (1 << 10)
#define TCC_WEXCTRL_DTIEN3 (1 << 11)
#define TCC_WEXCTRL_DTLS_SHIFT (16)
#define TCC_WEXCTRL_DTLS_MASK (0xff << TCC_WEXCTRL_DTLS_SHIFT)
#define TCC_WEXCTRL_DTHS_SHIFT (24)
#define TCC_WEXCTRL_DTHS_MASK (0xff << TCC_WEXCTRL_DTHS_SHIFT)
/* Driver Control register */
#define TCC_DRVCTRL_NRE(n) (1 << n)
#define TCC_DRVCTRL_NRV(n) (1 << (8+n))
#define TCC_DRVCTRL_INVEN(n) (1 << (16+n))
#define TCC_DRVCTRL_FILTERVAL0_SHIFT (24)
#define TCC_DRVCTRL_FILTERVAL0_MASK (0xf << TCC_DRVCTRL_FILTERVAL0_SHIFT)
#define TCC_DRVCTRL_FILTERVAL1_SHIFT (28)
#define TCC_DRVCTRL_FILTERVAL1_MASK (0xf << TCC_DRVCTRL_FILTERVAL1_SHIFT)
/* Debug control register */
#define TCC_DBGCTRL_DBGRUN (1 << 0)
#define TCC_DBGCTRL_FDDBD (1 << 2)
/* Event control register */
#define TCC_EVCTRL_EVACT0_SHIFT (0)
#define TCC_EVCTRL_EVACT0_MASK (7 << TCC_EVCTRL_EVACT0_SHIFT)
# define TCC_EVCTRL_EVACT0_OFF (0 << TCC_EVCTRL_EVACT0_SHIFT)
# define TCC_EVCTRL_EVACT0_RETRIGGER (1 << TCC_EVCTRL_EVACT0_SHIFT)
# define TCC_EVCTRL_EVACT0_COUNTEV (2 << TCC_EVCTRL_EVACT0_SHIFT)
# define TCC_EVCTRL_EVACT0_START (3 << TCC_EVCTRL_EVACT0_SHIFT)
# define TCC_EVCTRL_EVACT0_INC (4 << TCC_EVCTRL_EVACT0_SHIFT)
# define TCC_EVCTRL_EVACT0_COUNT (5 << TCC_EVCTRL_EVACT0_SHIFT)
# define TCC_EVCTRL_EVACT0_FAULT (7 << TCC_EVCTRL_EVACT0_SHIFT)
#define TCC_EVCTRL_EVACT1_SHIFT (3)
#define TCC_EVCTRL_EVACT1_MASK (7 << TCC_EVCTRL_EVACT1_SHIFT)
# define TCC_EVCTRL_EVACT1_OFF (0 << TCC_EVCTRL_EVACT1_SHIFT)
# define TCC_EVCTRL_EVACT1_RETRIGGER (1 << TCC_EVCTRL_EVACT1_SHIFT)
# define TCC_EVCTRL_EVACT1_DIR (2 << TCC_EVCTRL_EVACT1_SHIFT)
# define TCC_EVCTRL_EVACT1_STOP (3 << TCC_EVCTRL_EVACT1_SHIFT)
# define TCC_EVCTRL_EVACT1_DEC (4 << TCC_EVCTRL_EVACT1_SHIFT)
# define TCC_EVCTRL_EVACT1_PPW (5 << TCC_EVCTRL_EVACT1_SHIFT)
# define TCC_EVCTRL_EVACT1_PWP (6 << TCC_EVCTRL_EVACT1_SHIFT)
# define TCC_EVCTRL_EVACT1_FAULT (7 << TCC_EVCTRL_EVACT1_SHIFT)
#define TCC_EVCTRL_CNTSEL_SHIFT (6)
#define TCC_EVCTRL_CNTSEL_MASK (3 << TCC_EVCTRL_CNTSEL_SHIFT)
# define TCC_EVCTRL_CNTSEL_BEGIN (0 << TCC_EVCTRL_CNTSEL_SHIFT)
# define TCC_EVCTRL_CNTSEL_END (1 << TCC_EVCTRL_CNTSEL_SHIFT)
# define TCC_EVCTRL_CNTSEL_BETWEEN (2 << TCC_EVCTRL_CNTSEL_SHIFT)
# define TCC_EVCTRL_CNTSEL_BOUNDARY (3 << TCC_EVCTRL_CNTSEL_SHIFT)
#define TCC_EVCTRL_OVFEO (1 << 8)
#define TCC_EVCTRL_TRGEO (1 << 9)
#define TCC_EVCTRL_CNTEO (1 << 10)
#define TCC_EVCTRL_TCINV0 (1 << 12)
#define TCC_EVCTRL_TCINV1 (1 << 13)
#define TCC_EVCTRL_TCEI0 (1 << 14)
#define TCC_EVCTRL_TCEI1 (1 << 15)
#define TCC_EVCTRL_MCEI0 (1 << 16)
#define TCC_EVCTRL_MCEI1 (1 << 17)
#define TCC_EVCTRL_MCEI2 (1 << 18)
#define TCC_EVCTRL_MCEI3 (1 << 19)
#define TCC_EVCTRL_MCEO0 (1 << 24)
#define TCC_EVCTRL_MCEO1 (1 << 25)
#define TCC_EVCTRL_MCEO2 (1 << 26)
#define TCC_EVCTRL_MCEO3 (1 << 27)
/* Interrupt register bits */
#define TCC_INT_OVF (1 << 0)
#define TCC_INT_TRG (1 << 1)
#define TCC_INT_CNT (1 << 2)
#define TCC_INT_ERR (1 << 3)
#define TCC_INT_DFS (1 << 11)
#define TCC_INT_FAULTA (1 << 12)
#define TCC_INT_FAULTB (1 << 13)
#define TCC_INT_FAULT0 (1 << 14)
#define TCC_INT_FAULT1 (1 << 15)
#define TCC_INT_MC0 (1 << 16)
#define TCC_INT_MC1 (1 << 17)
#define TCC_INT_MC2 (1 << 18)
#define TCC_INT_MC3 (1 << 19)
/* Status register */
#define TCC_STATUS_STOP (1 << 0)
#define TCC_STATUS_IDX (1 << 1)
#define TCC_STATUS_DFS (1 << 3)
#define TCC_STATUS_PATTBV (1 << 5)
#define TCC_STATUS_WAVEBV (1 << 6)
#define TCC_STATUS_PERBV (1 << 7)
#define TCC_STATUS_FAULTAIN (1 << 8)
#define TCC_STATUS_FAULTBIN (1 << 9)
#define TCC_STATUS_FAULT0IN (1 << 10)
#define TCC_STATUS_FAULT1IN (1 << 11)
#define TCC_STATUS_FAULTA (1 << 12)
#define TCC_STATUS_FAULTB (1 << 13)
#define TCC_STATUS_FAULT0 (1 << 14)
#define TCC_STATUS_FAULT1 (1 << 15)
#define TCC_STATUS_CCBV0 (1 << 16)
#define TCC_STATUS_CCBV1 (1 << 17)
#define TCC_STATUS_CCBV2 (1 << 18)
#define TCC_STATUS_CCBV3 (1 << 19)
#define TCC_STATUS_CMP0 (1 << 24)
#define TCC_STATUS_CMP1 (1 << 25)
#define TCC_STATUS_CMP2 (1 << 26)
#define TCC_STATUS_CMP3 (1 << 27)
/* Waveform register */
#define TCC_WAVE_WAVEGEN_SHIFT (0)
#define TCC_WAVE_WAVEGEN_MASK (7 << TCC_WAVE_WAVEGEN_SHIFT)
# define TCC_WAVE_WAVEGEN_NFRQ (0 << TCC_WAVE_WAVEGEN_SHIFT)
# define TCC_WAVE_WAVEGEN_MFRQ (1 << TCC_WAVE_WAVEGEN_SHIFT)
# define TCC_WAVE_WAVEGEN_NPWM (2 << TCC_WAVE_WAVEGEN_SHIFT)
# define TCC_WAVE_WAVEGEN_DSCRITICAL (4 << TCC_WAVE_WAVEGEN_SHIFT)
# define TCC_WAVE_WAVEGEN_DSBOTTOM (5 << TCC_WAVE_WAVEGEN_SHIFT)
# define TCC_WAVE_WAVEGEN_DSBOTH (6 << TCC_WAVE_WAVEGEN_SHIFT)
# define TCC_WAVE_WAVEGEN_DSTOP (7 << TCC_WAVE_WAVEGEN_SHIFT)
#define TCC_WAVE_RAMP_SHIFT (4)
#define TCC_WAVE_RAMP_MASK (3 << TCC_WAVE_RAMP_SHIFT)
# define TCC_WAVE_RAMP_RAMP1 (0 << TCC_WAVE_RAMP_SHIFT)
# define TCC_WAVE_RAMP_RAMP2A (1 << TCC_WAVE_RAMP_SHIFT)
# define TCC_WAVE_RAMP_RAMP2 (2 << TCC_WAVE_RAMP_SHIFT)
#define TCC_WAVE_CIPEREN (1 << 7)
#define TCC_WAVE_CICCEN0 (1 << 8)
#define TCC_WAVE_CICCEN1 (1 << 9)
#define TCC_WAVE_CICCEN2 (1 << 10)
#define TCC_WAVE_CICCEN3 (1 << 11)
#define TCC_WAVE_POL0 (1 << 16)
#define TCC_WAVE_POL1 (1 << 17)
#define TCC_WAVE_POL2 (1 << 18)
#define TCC_WAVE_POL3 (1 << 19)
#define TCC_WAVE_SWAP0 (1 << 24)
#define TCC_WAVE_SWAP1 (1 << 25)
#define TCC_WAVE_SWAP2 (1 << 26)
#define TCC_WAVE_SWAP3 (1 << 27)
/* Period, CCx, PERB, CCBx register */
#define TCC_DITHER_SHIFT (0)
#define TCC_DITHER_MASK (0x3f << TCC_PER_DITHER_SHIFT)
# define TCC_DITHER_NONE (0 << TCC_DITHER_SHIFT)
# define TCC_DITHER_DITH4 (1 << TCC_DITHER_SHIFT)
# define TCC_DITHER_DITH5 (2 << TCC_DITHER_SHIFT)
# define TCC_DITHER_DITH6 (3 << TCC_DITHER_SHIFT)
#define TCC_VALUE_SHIFT (6)
#define TCC_VALUE_MASK (0x3ff << TCC_VALUE_SHIFT)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TCC_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_usart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_USART_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_USART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/samd_sercom.h"
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* USART register offsets ***************************************************/
#define SAM_USART_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_USART_CTRLB_OFFSET 0x0004 /* Control B register */
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
# define SAM_USART_DBGCTRL_OFFSET 0x0008 /* Debug control register */
# define SAM_USART_BAUD_OFFSET 0x000a /* Baud register */
# define SAM_USART_INTENCLR_OFFSET 0x000c /* Interrupt enable clear register */
# define SAM_USART_INTENSET_OFFSET 0x000d /* Interrupt enable set register */
# define SAM_USART_INTFLAG_OFFSET 0x000e /* Interrupt flag and status clear register */
# define SAM_USART_STATUS_OFFSET 0x0010 /* Status register */
# define SAM_USART_DATA_OFFSET 0x0018 /* Data register */
#elif defined(CONFIG_ARCH_FAMILY_SAMD21)
# define SAM_USART_BAUD_OFFSET 0x000c /* Baud register */
# define SAM_USART_RXPL_OFFSET 0x000e /* Receive pulse length register */
# define SAM_USART_INTENCLR_OFFSET 0x0014 /* Interrupt enable clear register */
# define SAM_USART_INTENSET_OFFSET 0x0016 /* Interrupt enable set register */
# define SAM_USART_INTFLAG_OFFSET 0x0018 /* Interrupt flag and status clear register */
# define SAM_USART_STATUS_OFFSET 0x001a /* Status register */
# define SAM_USART_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */
# define SAM_USART_DATA_OFFSET 0x0028 /* Data register */
# define SAM_USART_DBGCTRL_OFFSET 0x0030 /* Debug control register */
#endif
/* USART register addresses *************************************************/
#define SAM_USART0_CTRLA (SAM_SERCOM0_BASE+SAM_USART_CTRLA_OFFSET)
#define SAM_USART0_CTRLB (SAM_SERCOM0_BASE+SAM_USART_CTRLB_OFFSET)
#define SAM_USART0_BAUD (SAM_SERCOM0_BASE+SAM_USART_BAUD_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_USART0_RXPL (SAM_SERCOM0_BASE+SAM_USART_RXPL_OFFSET)
#endif
#define SAM_USART0_INTENCLR (SAM_SERCOM0_BASE+SAM_USART_INTENCLR_OFFSET)
#define SAM_USART0_INTENSET (SAM_SERCOM0_BASE+SAM_USART_INTENSET_OFFSET)
#define SAM_USART0_INTFLAG (SAM_SERCOM0_BASE+SAM_USART_INTFLAG_OFFSET)
#define SAM_USART0_STATUS (SAM_SERCOM0_BASE+SAM_USART_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_USART0_SYNCBUSY (SAM_SERCOM0_BASE+SAM_USART_SYNCBUSY_OFFSET)
#endif
#define SAM_USART0_DATA (SAM_SERCOM0_BASE+SAM_USART_DATA_OFFSET)
#define SAM_USART0_DBGCTRL (SAM_SERCOM0_BASE+SAM_USART_DBGCTRL_OFFSET)
#define SAM_USART1_CTRLA (SAM_SERCOM1_BASE+SAM_USART_CTRLA_OFFSET)
#define SAM_USART1_CTRLB (SAM_SERCOM1_BASE+SAM_USART_CTRLB_OFFSET)
#define SAM_USART1_BAUD (SAM_SERCOM1_BASE+SAM_USART_BAUD_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_USART1_RXPL (SAM_SERCOM1_BASE+SAM_USART_RXPL_OFFSET)
#endif
#define SAM_USART1_INTENCLR (SAM_SERCOM1_BASE+SAM_USART_INTENCLR_OFFSET)
#define SAM_USART1_INTENSET (SAM_SERCOM1_BASE+SAM_USART_INTENSET_OFFSET)
#define SAM_USART1_INTFLAG (SAM_SERCOM1_BASE+SAM_USART_INTFLAG_OFFSET)
#define SAM_USART1_STATUS (SAM_SERCOM1_BASE+SAM_USART_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_USART1_SYNCBUSY (SAM_SERCOM1_BASE+SAM_USART_SYNCBUSY_OFFSET)
#endif
#define SAM_USART1_DATA (SAM_SERCOM1_BASE+SAM_USART_DATA_OFFSET)
#define SAM_USART1_DBGCTRL (SAM_SERCOM1_BASE+SAM_USART_DBGCTRL_OFFSET)
#define SAM_USART2_CTRLA (SAM_SERCOM2_BASE+SAM_USART_CTRLA_OFFSET)
#define SAM_USART2_CTRLB (SAM_SERCOM2_BASE+SAM_USART_CTRLB_OFFSET)
#define SAM_USART2_BAUD (SAM_SERCOM2_BASE+SAM_USART_BAUD_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_USART2_RXPL (SAM_SERCOM2_BASE+SAM_USART_RXPL_OFFSET)
#endif
#define SAM_USART2_INTENCLR (SAM_SERCOM2_BASE+SAM_USART_INTENCLR_OFFSET)
#define SAM_USART2_INTENSET (SAM_SERCOM2_BASE+SAM_USART_INTENSET_OFFSET)
#define SAM_USART2_INTFLAG (SAM_SERCOM2_BASE+SAM_USART_INTFLAG_OFFSET)
#define SAM_USART2_STATUS (SAM_SERCOM2_BASE+SAM_USART_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_USART2_SYNCBUSY (SAM_SERCOM2_BASE+SAM_USART_SYNCBUSY_OFFSET)
#endif
#define SAM_USART2_DATA (SAM_SERCOM2_BASE+SAM_USART_DATA_OFFSET)
#define SAM_USART2_DBGCTRL (SAM_SERCOM2_BASE+SAM_USART_DBGCTRL_OFFSET)
#define SAM_USART3_CTRLA (SAM_SERCOM3_BASE+SAM_USART_CTRLA_OFFSET)
#define SAM_USART3_CTRLB (SAM_SERCOM3_BASE+SAM_USART_CTRLB_OFFSET)
#define SAM_USART3_BAUD (SAM_SERCOM3_BASE+SAM_USART_BAUD_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_USART3_RXPL (SAM_SERCOM3_BASE+SAM_USART_RXPL_OFFSET)
#endif
#define SAM_USART3_INTENCLR (SAM_SERCOM3_BASE+SAM_USART_INTENCLR_OFFSET)
#define SAM_USART3_INTENSET (SAM_SERCOM3_BASE+SAM_USART_INTENSET_OFFSET)
#define SAM_USART3_INTFLAG (SAM_SERCOM3_BASE+SAM_USART_INTFLAG_OFFSET)
#define SAM_USART3_STATUS (SAM_SERCOM3_BASE+SAM_USART_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_USART3_SYNCBUSY (SAM_SERCOM3_BASE+SAM_USART_SYNCBUSY_OFFSET)
#endif
#define SAM_USART3_DATA (SAM_SERCOM3_BASE+SAM_USART_DATA_OFFSET)
#define SAM_USART3_DBGCTRL (SAM_SERCOM3_BASE+SAM_USART_DBGCTRL_OFFSET)
#define SAM_USART4_CTRLA (SAM_SERCOM4_BASE+SAM_USART_CTRLA_OFFSET)
#define SAM_USART4_CTRLB (SAM_SERCOM4_BASE+SAM_USART_CTRLB_OFFSET)
#define SAM_USART4_BAUD (SAM_SERCOM4_BASE+SAM_USART_BAUD_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_USART4_RXPL (SAM_SERCOM4_BASE+SAM_USART_RXPL_OFFSET)
#endif
#define SAM_USART4_INTENCLR (SAM_SERCOM4_BASE+SAM_USART_INTENCLR_OFFSET)
#define SAM_USART4_INTENSET (SAM_SERCOM4_BASE+SAM_USART_INTENSET_OFFSET)
#define SAM_USART4_INTFLAG (SAM_SERCOM4_BASE+SAM_USART_INTFLAG_OFFSET)
#define SAM_USART4_STATUS (SAM_SERCOM4_BASE+SAM_USART_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_USART4_SYNCBUSY (SAM_SERCOM4_BASE+SAM_USART_SYNCBUSY_OFFSET)
#endif
#define SAM_USART4_DATA (SAM_SERCOM4_BASE+SAM_USART_DATA_OFFSET)
#define SAM_USART4_DBGCTRL (SAM_SERCOM4_BASE+SAM_USART_DBGCTRL_OFFSET)
#define SAM_USART5_CTRLA (SAM_SERCOM5_BASE+SAM_USART_CTRLA_OFFSET)
#define SAM_USART5_CTRLB (SAM_SERCOM5_BASE+SAM_USART_CTRLB_OFFSET)
#define SAM_USART5_BAUD (SAM_SERCOM5_BASE+SAM_USART_BAUD_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_USART5_RXPL (SAM_SERCOM5_BASE+SAM_USART_RXPL_OFFSET)
#endif
#define SAM_USART5_INTENCLR (SAM_SERCOM5_BASE+SAM_USART_INTENCLR_OFFSET)
#define SAM_USART5_INTENSET (SAM_SERCOM5_BASE+SAM_USART_INTENSET_OFFSET)
#define SAM_USART5_INTFLAG (SAM_SERCOM5_BASE+SAM_USART_INTFLAG_OFFSET)
#define SAM_USART5_STATUS (SAM_SERCOM5_BASE+SAM_USART_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_USART5_SYNCBUSY (SAM_SERCOM5_BASE+SAM_USART_SYNCBUSY_OFFSET)
#endif
#define SAM_USART5_DATA (SAM_SERCOM5_BASE+SAM_USART_DATA_OFFSET)
#define SAM_USART5_DBGCTRL (SAM_SERCOM5_BASE+SAM_USART_DBGCTRL_OFFSET)
/* USART register bit definitions *******************************************/
/* Control A register */
#define USART_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
#define USART_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
#define USART_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */
#define USART_CTRLA_MODE_MASK (7 << USART_CTRLA_MODE_SHIFT)
# define USART_CTRLA_MODE_EXTUSART (0 << USART_CTRLA_MODE_SHIFT) /* USART with external clock */
# define USART_CTRLA_MODE_INTUSART (1 << USART_CTRLA_MODE_SHIFT) /* USART with internal clock */
/* Bits 5-6: reserved */
#define USART_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */
#define USART_CTRLA_IBON (1 << 8) /* Bit 8: Immediate BUFOVF notification */
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
/* Bits 9-15: reserved */
# define USART_CTRLA_TXPO (1 << 16) /* Bit 16: Transmit data pinout */
# define USART_CTRLA_TXPAD0 (0)
# define USART_CTRLA_TXPAD2 USART_CTRLA_TXPO
#elif defined(CONFIG_ARCH_FAMILY_SAMD21)
/* Bits 9-12: reserved */
# define USART_CTRLA_SAMPR_SHIFT (13) /* Bits 13-15: Sample rate */
# define USART_CTRLA_SAMPR_MASK (3 << USART_CTRLA_SAMPR_SHIFT)
# define USART_CTRLA_SAMPR_16XA (0 << USART_CTRLA_SAMPR_SHIFT) /* 16x oversampling; arithmetic baud */
# define USART_CTRLA_SAMPR_16XF (1 << USART_CTRLA_SAMPR_SHIFT) /* 16x oversampling; fractional baud */
# define USART_CTRLA_SAMPR_8XA (2 << USART_CTRLA_SAMPR_SHIFT) /* 8x oversampling; arithmetic baud */
# define USART_CTRLA_SAMPR_8XF (3 << USART_CTRLA_SAMPR_SHIFT) /* 8x oversampling; fractional baud */
# define USART_CTRLA_SAMPR_3XA (4 << USART_CTRLA_SAMPR_SHIFT) /* 3x oversampling; arithmetic baud */
# define USART_CTRLA_TXPO_SHIFT (16) /* Bits 16-17: Transmit data pinout */
# define USART_CTRLA_TXPO_MASK (3 << USART_CTRLA_TXPO_SHIFT)
# define USART_CTRLA_TXPAD0_1 (0 << USART_CTRLA_TXPO_SHIFT) /* TxD=SERCOM PAD[0]; XCK=PAD[1] */
# define USART_CTRLA_TXPAD2 (1 << USART_CTRLA_TXPO_SHIFT) /* TxD=SERCOM PAD[2]; XCK=PAD[3] */
# define USART_CTRLA_TXPAD0_2 (2 << USART_CTRLA_TXPO_SHIFT) /* TxD=SERCOM PAD[0]; RTS=PAD[2]; CTS=PAD[3] */
#endif
#define USART_CTRLA_RXPO_SHIFT (20) /* Bits 20-21: Receive data pinout */
#define USART_CTRLA_RXPO_MASK (3 << USART_CTRLA_RXPO_SHIFT)
# define USART_CTRLA_RXPAD0 (0 << USART_CTRLA_RXPO_SHIFT) /* SERCOM PAD[0] for RxD */
# define USART_CTRLA_RXPAD1 (1 << USART_CTRLA_RXPO_SHIFT) /* SERCOM PAD[1] for RxD */
# define USART_CTRLA_RXPAD2 (2 << USART_CTRLA_RXPO_SHIFT) /* SERCOM PAD[2] for RxD */
# define USART_CTRLA_RXPAD3 (3 << USART_CTRLA_RXPO_SHIFT) /* SERCOM PAD[3] for RxD */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define USART_CTRLA_SAMPA_SHIFT (22) /* Bits 22-23: Sample adjustment */
# define USART_CTRLA_SAMPA_MASK (3 << USART_CTRLA_SAMPA_SHIFT)
# define USART_CTRLA_SAMPA_789 (0 << USART_CTRLA_SAMPA_SHIFT) /* 16x oversampling 7-8-9 */
# define USART_CTRLA_SAMPA_91011 (1 << USART_CTRLA_SAMPA_SHIFT) /* 16x oversampling 9-10-11 */
# define USART_CTRLA_SAMPA_111213 (2 << USART_CTRLA_SAMPA_SHIFT) /* 16x oversampling 11-12-13 */
# define USART_CTRLA_SAMPA_131415 (3 << USART_CTRLA_SAMPA_SHIFT) /* 16x oversampling 13-14-15 */
#endif
#define USART_CTRLA_FORM_SHIFT (24) /* Bits 24-27: Frame format */
#define USART_CTRLA_FORM_MASK (7 << USART_CTRLA_FORM_SHIFT)
# define USART_CTRLA_FORM_NOPARITY (0 << USART_CTRLA_FORM_SHIFT) /* USART frame (no parity) */
# define USART_CTRLA_FORM_PARITY (1 << USART_CTRLA_FORM_SHIFT) /* USART frame (w/parity) */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define USART_CTRLA_FORM_AUTOBAUD (4 << USART_CTRLA_FORM_SHIFT) /* Auto-baud (no parity) */
# define USART_CTRLA_FORM_AUTOBAUDP (5 << USART_CTRLA_FORM_SHIFT) /* Auto-baud (parity) */
#endif
#define USART_CTRLA_CMODE (1 << 28) /* Bit 28: Communication mode */
# define USART_CTRLA_ASYNCH (0)
# define USART_CTRLA_SYNCH USART_CTRLA_CMODE
#define USART_CTRLA_CPOL (1 << 29) /* Bit 29: Clock polarity */
# define USART_CTRLA_CPOL_NORMAL (0) /* Rising XCK edge Falling XCK edge */
# define USART_CTRLA_CPOL_INVERTED USART_CTRLA_CPOL /* Falling XCK edge Rising XCK edge */
#define USART_CTRLA_DORD (1 << 30) /* Bit 30: Data order */
# define USART_CTRLA_MSBFIRST (0)
# define USART_CTRLA_LSBFIRST USART_CTRLA_DORD
/* Control B register */
#define USART_CTRLB_CHSIZE_SHIFT (0) /* Bits 0-2: Character Size */
#define USART_CTRLB_CHSIZE_MASK (7 << USART_CTRLB_CHSIZE_SHIFT)
# define USART_CTRLB_CHSIZE_8BITS (0 << USART_CTRLB_CHSIZE_SHIFT) /* 8 bits */
# define USART_CTRLB_CHSIZE_9BITS (1 << USART_CTRLB_CHSIZE_SHIFT) /* 9 bits */
# define USART_CTRLB_CHSIZE_5BITS (5 << USART_CTRLB_CHSIZE_SHIFT) /* 5 bits */
# define USART_CTRLB_CHSIZE_6BITS (6 << USART_CTRLB_CHSIZE_SHIFT) /* 6 bits */
# define USART_CTRLB_CHSIZE_7BITS (7 << USART_CTRLB_CHSIZE_SHIFT) /* 7 bits */
#define USART_CTRLB_SBMODE (1 << 6) /* Bit 6: Stop bit mode */
# define USART_CTRLB_SBMODE_1 (0)
# define USART_CTRLB_SBMODE_2 USART_CTRLB_SBMODE
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define USART_CTRLB_COLDEN (1 << 8) /* Bit 8: Collision detection enable */
#endif
#define USART_CTRLB_SFDE (1 << 9) /* Bit 9: Start of frame detection enable */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define USART_CTRLB_ENC (1 << 10) /* Bit 10: Encoding format */
# define USART_CTRLB_UNENCODED (0)
# define USART_CTRLB_IRDA USART_CTRLB_ENC
#endif
#define USART_CTRLB_PMODE (1 << 13) /* Bit 13: Parity mode */
# define USART_CTRLB_PEVEN (0)
# define USART_CTRLB_PODD USART_CTRLB_PMODE
#define USART_CTRLB_TXEN (1 << 16) /* Bit 16: Transmitter enable */
#define USART_CTRLB_RXEN (1 << 17) /* Bit 17: Receiver enable */
/* Baud register (For SAMD20, this is a 16-bit baud value) */
/* For SAMD20 or for SAMD21 with SAMPR[0]=0 */
#define USART_BAUD_SHIFT (0) /* Bits 0-15: Baud Value */
#define USART_BAUD_MASK (0xffff)
# define USART_BAUD(n) ((uint16_t)(n))
/* For SAMD20 or for SAMD21 with SAMPR[0]=0 */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define USART_BAUD_IP_SHIFT (0) /* Bits 0-12: Baud Value (integer part) */
# define USART_BAUD_IP_MASK (0x1fff)
# define USART_IP_BAUD(n) ((uint16_t)(n))
# define USART_BAUD_FP_SHIFT (13) /* Bits 13-15: Fractional part */
# define USART_BAUD_FP_MASK (7 << USART_BAUD_FP_SHIFT)
# define USART_BAUD_FP(n) ((uint16_t)(n) << USART_BAUD_FP_SHIFT)
#endif
/* Receive pulse length register (8-bit value) */
/* Interrupt enable clear, interrupt enable set, interrupt enable set,
* interrupt flag and status clear registers.
*/
#define USART_INT_DRE (1 << 0) /* Bit 0: Data register empty interrupt */
#define USART_INT_TXC (1 << 1) /* Bit 1: Transmit complete interrupt */
#define USART_INT_RXC (1 << 2) /* Bit 2: Receive complete interrupt */
#define USART_INT_RXS (1 << 3) /* Bit 3: Receive start interrupt */
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
# define USART_INT_CTSIC (1 << 4) /* Bit 4: Clear to send input change interrupt */
# define USART_INT_RXBRK (1 << 5) /* Bit 5: Receive break interrupt */
# define USART_INT_ERROR (1 << 7) /* Bit 6: Error interrupt */
# define USART_INT_ALL (0xbf)
#elif defined(CONFIG_ARCH_FAMILY_SAMD21)
# define USART_INT_ALL (0x0f)
#endif
/* Status register */
#define USART_STATUS_PERR (1 << 0) /* Bit 0: Parity error */
#define USART_STATUS_FERR (1 << 1) /* Bit 1: Frame error */
#define USART_STATUS_BUFOVF (1 << 2) /* Bit 2: Buffer overflow */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define USART_STATUS_CTS (1 << 3) /* Bit 3: Clear to send */
# define USART_STATUS_ISF (1 << 4) /* Bit 4: Inconsistent sync field */
# define USART_STATUS_COLL (1 << 5) /* Bit 5: Collision detected */
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define USART_STATUS_SYNCBUSY (1 << 15) /* Bit 15: Synchronization busy */
#endif
/* Synchronization busy register */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define USART_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset synchronization busy */
# define USART_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: SERCOM enable synchronization busy */
# define USART_SYNCBUSY_CTRLB (1 << 2) /* Bit 2: CTRLB synchronization busy */
# define USART_SYNCBUSY_ALL 0x0007
#endif
/* Data register */
#define USART_DATA_MASK (0x1ff) /* Bits 0-8: Data */
/* Debug control register */
#define USART_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_USART_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/samd_wdt.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAM_WDT_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAM_WDT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* WDT register offsets *****************************************************/
#define SAM_WDT_CTRL_OFFSET 0x0000 /* Control register */
#define SAM_WDT_CONFIG_OFFSET 0x0001 /* Configuration register */
#define SAM_WDT_EWCTRL_OFFSET 0x0002 /* Early warning interrupt control register */
#define SAM_WDT_INTENCLR_OFFSET 0x0004 /* Interrupt enable clear register */
#define SAM_WDT_INTENSET_OFFSET 0x0005 /* Interrupt enable set register */
#define SAM_WDT_INTFLAG_OFFSET 0x0006 /* Interrupt flag and status clear register */
#define SAM_WDT_STATUS_OFFSET 0x0007 /* Status register */
#define SAM_WDT_CLEAR_OFFSET 0x0008 /* Clear register */
/* WDT register addresses ***************************************************/
#define SAM_WDT_CTRL (SAM_WDT_BASE+SAM_WDT_CTRL_OFFSET)
#define SAM_WDT_CONFIG (SAM_WDT_BASE+SAM_WDT_CONFIG_OFFSET)
#define SAM_WDT_EWCTRL (SAM_WDT_BASE+SAM_WDT_EWCTRL_OFFSET)
#define SAM_WDT_INTENCLR (SAM_WDT_BASE+SAM_WDT_INTENCLR_OFFSET)
#define SAM_WDT_INTENSET (SAM_WDT_BASE+SAM_WDT_INTENSET_OFFSET)
#define SAM_WDT_INTFLAG (SAM_WDT_BASE+SAM_WDT_INTFLAG_OFFSET)
#define SAM_WDT_STATUS (SAM_WDT_BASE+SAM_WDT_STATUS_OFFSET)
#define SAM_WDT_CLEAR (SAM_WDT_BASE+SAM_WDT_CLEAR_OFFSET)
/* WDT register bit definitions *********************************************/
/* Control register */
#define WDT_CTRL_ENABLE (1 << 1) /* Bit 1: Enable */
#define WDT_CTRL_WEN (1 << 2) /* Bit 2: Watchdog Timer Window Mode Enable */
#define WDT_CTRL_ALWAYSON (1 << 7) /* Bit 7: Always-On */
/* Configuration register */
#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0–3: Time-Out Period */
#define WDT_CONFIG_PER_MASK (15 << WDT_CONFIG_PER_SHIFT)
# define WDT_CONFIG_PER_8 (0 << WDT_CONFIG_PER_SHIFT) /* 8 clock cycles */
# define WDT_CONFIG_PER_16 (1 << WDT_CONFIG_PER_SHIFT) /* 16 clock cycles */
# define WDT_CONFIG_PER_32 (2 << WDT_CONFIG_PER_SHIFT) /* 32 clock cycles */
# define WDT_CONFIG_PER_64 (3 << WDT_CONFIG_PER_SHIFT) /* 64 clock cycles */
# define WDT_CONFIG_PER_128 (4 << WDT_CONFIG_PER_SHIFT) /* 128 clock cycles */
# define WDT_CONFIG_PER_256 (5 << WDT_CONFIG_PER_SHIFT) /* 256 clocks cycles */
# define WDT_CONFIG_PER_512 (6 << WDT_CONFIG_PER_SHIFT) /* 512 clocks cycles */
# define WDT_CONFIG_PER_1K (7 << WDT_CONFIG_PER_SHIFT) /* 1024 clock cycles */
# define WDT_CONFIG_PER_2K (8 << WDT_CONFIG_PER_SHIFT) /* 2048 clock cycles */
# define WDT_CONFIG_PER_4K (9 << WDT_CONFIG_PER_SHIFT) /* 4096 clock cycles */
# define WDT_CONFIG_PER_8k (10 << WDT_CONFIG_PER_SHIFT) /* 8192 clock cycles */
# define WDT_CONFIG_PER_16K (11 << WDT_CONFIG_PER_SHIFT) /* 16384 clock cycles */
#define WDT_CONFIG_WINDOW_SHIFT (4) /* Bits 4-7: Window Mode Time-Out Period */
#define WDT_CONFIG_WINDOW_MASK (15 << WDT_CONFIG_WINDOW_SHIFT)
# define WDT_CONFIG_WINDOW_8 (0 << WDT_CONFIG_WINDOW_SHIFT) /* 8 clock cycles */
# define WDT_CONFIG_WINDOW_16 (1 << WDT_CONFIG_WINDOW_SHIFT) /* 16 clock cycles */
# define WDT_CONFIG_WINDOW_32 (2 << WDT_CONFIG_WINDOW_SHIFT) /* 32 clock cycles */
# define WDT_CONFIG_WINDOW_64 (3 << WDT_CONFIG_WINDOW_SHIFT) /* 64 clock cycles */
# define WDT_CONFIG_WINDOW_128 (4 << WDT_CONFIG_WINDOW_SHIFT) /* 128 clock cycles */
# define WDT_CONFIG_WINDOW_256 (5 << WDT_CONFIG_WINDOW_SHIFT) /* 256 clocks cycles */
# define WDT_CONFIG_WINDOW_512 (6 << WDT_CONFIG_WINDOW_SHIFT) /* 512 clocks cycles */
# define WDT_CONFIG_WINDOW_1K (7 << WDT_CONFIG_WINDOW_SHIFT) /* 1024 clock cycles */
# define WDT_CONFIG_WINDOW_2K (8 << WDT_CONFIG_WINDOW_SHIFT) /* 2048 clock cycles */
# define WDT_CONFIG_WINDOW_4K (9 << WDT_CONFIG_WINDOW_SHIFT) /* 4096 clock cycles */
# define WDT_CONFIG_WINDOW_8k (10 << WDT_CONFIG_WINDOW_SHIFT) /* 8192 clock cycles */
# define WDT_CONFIG_WINDOW_16K (11 << WDT_CONFIG_WINDOW_SHIFT) /* 16384 clock cycles */
/* Early warning interrupt control register */
#define WDT_EWCTRL_EWOFFSET_SHIFT (0) /* Bits 0-3: Early warning interrupt time offset */
#define WDT_EWCTRL_EWOFFSET_MASK (15 << WDT_EWCTRL_EWOFFSET_SHIFT)
# define WDT_EWCTRL_EWOFFSET_8 (0 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 8 clock cycles */
# define WDT_EWCTRL_EWOFFSET_16 (1 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 16 clock cycles */
# define WDT_EWCTRL_EWOFFSET_32 (2 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 32 clock cycles */
# define WDT_EWCTRL_EWOFFSET_64 (3 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 64 clock cycles */
# define WDT_EWCTRL_EWOFFSET_128 (4 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 128 clock cycles */
# define WDT_EWCTRL_EWOFFSET_256 (5 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 256 clocks cycles */
# define WDT_EWCTRL_EWOFFSET_512 (6 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 512 clocks cycles */
# define WDT_EWCTRL_EWOFFSET_1K (7 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 1024 clock cycles */
# define WDT_EWCTRL_EWOFFSET_2K (8 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 2048 clock cycles */
# define WDT_EWCTRL_EWOFFSET_4K (9 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 4096 clock cycles */
# define WDT_EWCTRL_EWOFFSET_8k (10 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 8192 clock cycles */
# define WDT_EWCTRL_EWOFFSET_16K (11 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 16384 clock cycles */
/* Interrupt enable clear, interrupt enable set register,
* interrupt flag status and clear registers
*/
#define WDT_INT_EW (1 << 0) /* Bit 0: Early warning interrupt */
#define WDT_INT_All (0x01)
/* Status register */
#define WDT_STATUS_SYNCBUSY (1 << 7) /* Bit 7: Synchronization Busy */
/* Clear register */
#define WDT_CLEAR_CLEAR_SHIFT (0) /* Bits 0-7: Watchdog clear */
#define WDT_CLEAR_CLEAR_MASK (0xff << WDT_CLEAR_CLEAR_SHIFT)
# define WDT_CLEAR_CLEAR (0xa5 << WDT_CLEAR_CLEAR_SHIFT)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAM_WDT_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/saml21_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML21_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML21_MEMORYMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* System Memory Map */
#define SAM_FLASH_BASE 0x00000000 /* Embedded FLASH memory space (<= 256KB) */
#define SAM_FLASHRWW_BASE 0x00400000 /* Embedded FLASH RWW memory space (<= 8KB) */
#define SAM_NVM_BASE 0x00800000 /* Readable NVM content */
#define SAM_SRAM_BASE 0x20000000 /* Embedded SRAM memory space (<= 32KB) */
#define SAM_LPSRAM_BASE 0x30000000 /* Embedded low-power SRAM memory space (<= 8KB) */
#define SAM_AHBA_BASE 0x40000000 /* AHB-APB Bridge A (64KB) */
#define SAM_AHBB_BASE 0x41000000 /* AHB-APB Bridge B (64KB) */
#define SAM_AHBC_BASE 0x42000000 /* AHB-APB Bridge C (64KB) */
#define SAM_AHBD_BASE 0x43000000 /* AHB-APB Bridge D (64KB) */
#define SAM_AHBE_BASE 0x44000000 /* AHB-APB Bridge D (64KB) */
#define SAM_IOBUS_BASE 0x60000000 /* IOBUS (O.5KB) */
#define SAM_SYSTEM_BASE 0x60000200 /* System */
/* Non-volatile memory */
#define SAM_NVMUSER_ROW 0x00804000 /* NVM user row */
#define SAM_NVMCALIB_AREA 0x00806020 /* NVM software calibration area */
#define SAM_NVM_SERIALNO 0x0080a00c /* Serial number */
/* AHB-APB Bridge A */
#define SAM_PM_BASE 0x40000000 /* Power Management */
#define SAM_MCLK_BASE 0x40000400 /* Main Clock */
#define SAM_RSTC_BASE 0x40000800 /* Reset controller */
#define SAM_OSCCTRL_BASE 0x40000c00 /* Oscillators Controller */
#define SAM_OSC32KCTRL_BASE 0x40001000 /* 32KHz Oscillators Controller */
#define SAM_SUPC_BASE 0x40001400 /* Supply Controller */
#define SAM_GCLK_BASE 0x40001800 /* Generic Clock Controller */
#define SAM_WDT_BASE 0x40001c00 /* Watchdog Timer */
#define SAM_RTC_BASE 0x40002000 /* Real-Time Counter */
#define SAM_EIC_BASE 0x40002400 /* External Interrupt Controller */
#define SAM_PORT_BASE 0x40002800 /* Ports */
/* AHB-APB Bridge B */
#define SAM_USB_BASE 0x41000000 /* Universal Serial Bus */
#define SAM_DSU_BASE 0x41002000 /* Device Service Unit */
#define SAM_NVMCTRL_BASE 0x41004000 /* Non-Volatile Memory Controller */
#define SAM_MTB_BASE 0x41006000 /* Micro trace buffer */
/* AHB-APB Bridge C */
#define SAM_SERCOM0_BASE 0x42000000 /* Serial Communication Interface 0 */
#define SAM_SERCOM1_BASE 0x42000400 /* Serial Communication Interface 1 */
#define SAM_SERCOM2_BASE 0x42000800 /* Serial Communication Interface 2 */
#define SAM_SERCOM3_BASE 0x42000c00 /* Serial Communication Interface 3 */
#define SAM_SERCOM4_BASE 0x42001000 /* Serial Communication Interface 4 */
#define SAM_TCC0_BASE 0x42001400 /* Timer/Counter Control 0 */
#define SAM_TCC1_BASE 0x42001800 /* Timer/Counter Control 1 */
#define SAM_TCC2_BASE 0x42001c00 /* Timer/Counter Control 2 */
#define SAM_TC0_BASE 0x42002000 /* Timer/Counter 0 */
#define SAM_TC1_BASE 0x42002400 /* Timer/Counter 1 */
#define SAM_TC2_BASE 0x42002800 /* Timer/Counter 2 */
#define SAM_TC3_BASE 0x42002c00 /* Timer/Counter 3 */
#define SAM_DAC_BASE 0x42003000 /* Digital-to-Analog Converter */
#define SAM_AES_BASE 0x42003400 /* Advanced Encryption Standard */
#define SAM_TRNG_BASE 0x42003800 /* True Random Number Generator */
/* AHB-APB Bridge D */
#define SAM_EVSYS_BASE 0x43000000 /* Event system */
#define SAM_SERCOM5_BASE 0x43000400 /* Serial Communication Interface 5 */
#define SAM_TC4_BASE 0x43000800 /* Timer/Counter 4 */
#define SAM_ADC_BASE 0x43000c00 /* Analog-to-Digital Converter */
#define SAM_AC_BASE 0x43001000 /* Analog Comparator */
#define SAM_PTC_BASE 0x43001400 /* Peripheral Touch Controller */
#define SAM_OPAMP_BASE 0x43001800 /* OpAmps */
#define SAM_CCL_BASE 0x43001c00 /* Configurable Custom Logic */
/* AHB-APB Bridge E */
#define SAM_PAC_BASE 0x44000000 /* Peripheral Access Controller */
#define SAM_DMAC_BASE 0x44000400 /* DMA Controller */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML21_MEMORYMAP_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/saml21_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML21_PINMAP_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML21_PINMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* GPIO pin definitions *****************************************************/
/* Alternate Pin Functions.
*
* Alternative pin selections are provided with a numeric suffix like _1, _2,
* etc. Drivers, however, will use the pin selection without the numeric
* suffix. Additional definitions are required in the board.h file. For
* example, if we wanted the SERCOM0 PAD0 on PA8, then the following
* definition should appear in the board.h header file for that board:
*
* #define PORT_SERCOM0_PAD0 PORT_SERCOM0_PAD0_1
*
* The driver will then automatically configure PA8 as the SERCOM0 PAD0
* pin.
*/
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as
* frequency, open-drain/push-pull, and pull-up/down!
* Just the basics are defined for most pins in this file.
*/
/* Analog comparator */
#define PORT_AC_CMP0_1 (PORT_FUNCH | PORTA | PORT_PIN12)
#define PORT_AC_CMP0_2 (PORT_FUNCH | PORTA | PORT_PIN18)
#define PORT_AC_CMP1_1 (PORT_FUNCH | PORTA | PORT_PIN13)
#define PORT_AC_CMP1_2 (PORT_FUNCH | PORTA | PORT_PIN19)
/* ADC voltage references */
#define PORT_ADC_VREFA (PORT_FUNCB | PORTA | PORT_PIN3)
#define PORT_ADC_VREFB (PORT_FUNCB | PORTA | PORT_PIN4)
#define PORT_AIN0_1 (PORT_FUNCB | PORTA | PORT_PIN2)
#define PORT_AIN0_2 (PORT_FUNCB | PORTA | PORT_PIN4)
#define PORT_AIN1_1 (PORT_FUNCB | PORTA | PORT_PIN3)
#define PORT_AIN1_2 (PORT_FUNCB | PORTA | PORT_PIN5)
#define PORT_AIN2_1 (PORT_FUNCB | PORTA | PORT_PIN6)
#define PORT_AIN2_2 (PORT_FUNCB | PORTB | PORT_PIN8)
#define PORT_AIN3_1 (PORT_FUNCB | PORTA | PORT_PIN7)
#define PORT_AIN3_2 (PORT_FUNCB | PORTB | PORT_PIN9)
#define PORT_AIN4 (PORT_FUNCB | PORTA | PORT_PIN4)
#define PORT_AIN5 (PORT_FUNCB | PORTA | PORT_PIN5)
#define PORT_AIN6 (PORT_FUNCB | PORTA | PORT_PIN6)
#define PORT_AIN7 (PORT_FUNCB | PORTA | PORT_PIN7)
#define PORT_AIN8 (PORT_FUNCB | PORTB | PORT_PIN0)
#define PORT_AIN9 (PORT_FUNCB | PORTB | PORT_PIN1)
#define PORT_AIN10 (PORT_FUNCB | PORTB | PORT_PIN2)
#define PORT_AIN11 (PORT_FUNCB | PORTB | PORT_PIN3)
#define PORT_AIN12 (PORT_FUNCB | PORTB | PORT_PIN4)
#define PORT_AIN13 (PORT_FUNCB | PORTB | PORT_PIN5)
#define PORT_AIN14 (PORT_FUNCB | PORTB | PORT_PIN6)
#define PORT_AIN15 (PORT_FUNCB | PORTB | PORT_PIN7)
#define PORT_AIN16 (PORT_FUNCB | PORTA | PORT_PIN8)
#define PORT_AIN17 (PORT_FUNCB | PORTA | PORT_PIN9)
#define PORT_AIN18 (PORT_FUNCB | PORTA | PORT_PIN10)
#define PORT_AIN19 (PORT_FUNCB | PORTA | PORT_PIN11)
/* Configurable Custom Logic */
#define PORT_CCL0_IN0_1 (PORT_FUNCE | PORTA | PORT_PIN4)
#define PORT_CCL0_IN0_2 (PORT_FUNCI | PORTA | PORT_PIN16)
#define PORT_CCL0_IN0_3 (PORT_FUNCI | PORTB | PORT_PIN22)
#define PORT_CCL0_IN1_1 (PORT_FUNCI | PORTA | PORT_PIN17)
#define PORT_CCL0_IN1_2 (PORT_FUNCI | PORTA | PORT_PIN5)
#define PORT_CCL0_IN1_3 (PORT_FUNCI | PORTB | PORT_PIN0)
#define PORT_CCL0_IN2_1 (PORT_FUNCI | PORTA | PORT_PIN18)
#define PORT_CCL0_IN2_2 (PORT_FUNCI | PORTA | PORT_PIN6)
#define PORT_CCL0_IN2_3 (PORT_FUNCI | PORTB | PORT_PIN1)
#define PORT_CCL0_OUT_1 (PORT_FUNCI | PORTA | PORT_PIN7)
#define PORT_CCL0_OUT_2 (PORT_FUNCI | PORTA | PORT_PIN19)
#define PORT_CCL0_OUT_3 (PORT_FUNCI | PORTB | PORT_PIN2)
#define PORT_CCL0_OUT_4 (PORT_FUNCI | PORTB | PORT_PIN23)
#define PORT_CCL1_IN0_1 (PORT_FUNCI | PORTA | PORT_PIN30)
#define PORT_CCL1_IN0_2 (PORT_FUNCI | PORTA | PORT_PIN8)
#define PORT_CCL1_IN0_3 (PORT_FUNCI | PORTB | PORT_PIN6)
#define PORT_CCL1_IN1 (PORT_FUNCI | PORTA | PORT_PIN9)
#define PORT_CCL1_IN2_1 (PORT_FUNCI | PORTA | PORT_PIN10)
#define PORT_CCL1_IN2_2 (PORT_FUNCI | PORTB | PORT_PIN10)
#define PORT_CCL1_OUT_1 (PORT_FUNCI | PORTA | PORT_PIN11)
#define PORT_CCL1_OUT_2 (PORT_FUNCI | PORTA | PORT_PIN31)
#define PORT_CCL1_OUT_3 (PORT_FUNCI | PORTB | PORT_PIN11)
#define PORT_CCL2_IN0 (PORT_FUNCI | PORTA | PORT_PIN22)
#define PORT_CCL2_IN1_1 (PORT_FUNCI | PORTA | PORT_PIN23)
#define PORT_CCL2_IN1_2 (PORT_FUNCI | PORTB | PORT_PIN7)
#define PORT_CCL2_IN1_3 (PORT_FUNCI | PORTB | PORT_PIN8)
#define PORT_CCL2_IN2 (PORT_FUNCI | PORTA | PORT_PIN24)
#define PORT_CCL2_OUT_1 (PORT_FUNCI | PORTA | PORT_PIN25)
#define PORT_CCL2_OUT_2 (PORT_FUNCI | PORTB | PORT_PIN9)
#define PORT_CCL3_IN0 (PORT_FUNCI | PORTB | PORT_PIN14)
#define PORT_CCL3_IN1 (PORT_FUNCI | PORTB | PORT_PIN15)
#define PORT_CCL3_IN2 (PORT_FUNCI | PORTB | PORT_PIN16)
#define PORT_CCL3_OUT (PORT_FUNCI | PORTB | PORT_PIN17)
/* Cortex-M0 */
#define PORT_CORTEX_M0P (PORT_FUNCG | PORTA | PORT_PIN30)
/* DAC */
#define PORT_DAC_VOUT0 (PORT_FUNCB | PORTA | PORT_PIN2)
#define PORT_DAC_VOUT1 (PORT_FUNCB | PORTA | PORT_PIN5)
#define PORT_DAC_VREFP (PORT_FUNCB | PORTA | PORT_PIN3)
/* External interrupts */
#define PORT_EXTINT0_1 (PORT_FUNCA | PORTA | PORT_PIN0)
#define PORT_EXTINT0_2 (PORT_FUNCA | PORTA | PORT_PIN16)
#define PORT_EXTINT0_3 (PORT_FUNCA | PORTB | PORT_PIN0)
#define PORT_EXTINT0_4 (PORT_FUNCA | PORTB | PORT_PIN16)
#define PORT_EXTINT1_1 (PORT_FUNCA | PORTA | PORT_PIN1)
#define PORT_EXTINT1_2 (PORT_FUNCA | PORTA | PORT_PIN17)
#define PORT_EXTINT1_3 (PORT_FUNCA | PORTB | PORT_PIN1)
#define PORT_EXTINT1_4 (PORT_FUNCA | PORTB | PORT_PIN17)
#define PORT_EXTINT2_1 (PORT_FUNCA | PORTA | PORT_PIN2)
#define PORT_EXTINT2_2 (PORT_FUNCA | PORTB | PORT_PIN2)
#define PORT_EXTINT3_1 (PORT_FUNCA | PORTA | PORT_PIN3)
#define PORT_EXTINT3_2 (PORT_FUNCA | PORTB | PORT_PIN3)
#define PORT_EXTINT4_1 (PORT_FUNCA | PORTA | PORT_PIN20)
#define PORT_EXTINT4_2 (PORT_FUNCA | PORTA | PORT_PIN4)
#define PORT_EXTINT4_3 (PORT_FUNCA | PORTB | PORT_PIN4)
#define PORT_EXTINT5_1 (PORT_FUNCA | PORTA | PORT_PIN21)
#define PORT_EXTINT5_2 (PORT_FUNCA | PORTA | PORT_PIN5)
#define PORT_EXTINT5_3 (PORT_FUNCA | PORTB | PORT_PIN5)
#define PORT_EXTINT6_1 (PORT_FUNCA | PORTA | PORT_PIN22)
#define PORT_EXTINT6_2 (PORT_FUNCA | PORTA | PORT_PIN6)
#define PORT_EXTINT6_3 (PORT_FUNCA | PORTB | PORT_PIN22)
#define PORT_EXTINT6_4 (PORT_FUNCA | PORTB | PORT_PIN6)
#define PORT_EXTINT7_1 (PORT_FUNCA | PORTA | PORT_PIN7)
#define PORT_EXTINT7_2 (PORT_FUNCA | PORTA | PORT_PIN23)
#define PORT_EXTINT7_3 (PORT_FUNCA | PORTB | PORT_PIN23)
#define PORT_EXTINT7_4 (PORT_FUNCA | PORTB | PORT_PIN7)
#define PORT_EXTINT8 (PORT_FUNCA | PORTB | PORT_PIN8)
#define PORT_EXTINT9_1 (PORT_FUNCA | PORTA | PORT_PIN9)
#define PORT_EXTINT9_2 (PORT_FUNCA | PORTB | PORT_PIN9)
#define PORT_EXTINT10_1 (PORT_FUNCA | PORTA | PORT_PIN10)
#define PORT_EXTINT10_2 (PORT_FUNCA | PORTA | PORT_PIN30)
#define PORT_EXTINT10_3 (PORT_FUNCA | PORTB | PORT_PIN10)
#define PORT_EXTINT11_1 (PORT_FUNCA | PORTA | PORT_PIN11)
#define PORT_EXTINT11_2 (PORT_FUNCA | PORTA | PORT_PIN31)
#define PORT_EXTINT11_3 (PORT_FUNCA | PORTB | PORT_PIN11)
#define PORT_EXTINT12_1 (PORT_FUNCA | PORTA | PORT_PIN12)
#define PORT_EXTINT12_2 (PORT_FUNCA | PORTA | PORT_PIN18)
#define PORT_EXTINT12_3 (PORT_FUNCA | PORTA | PORT_PIN24)
#define PORT_EXTINT12_4 (PORT_FUNCA | PORTB | PORT_PIN12)
#define PORT_EXTINT13_1 (PORT_FUNCA | PORTA | PORT_PIN13)
#define PORT_EXTINT13_2 (PORT_FUNCA | PORTA | PORT_PIN19)
#define PORT_EXTINT13_3 (PORT_FUNCA | PORTA | PORT_PIN25)
#define PORT_EXTINT13_4 (PORT_FUNCA | PORTB | PORT_PIN13)
#define PORT_EXTINT14_1 (PORT_FUNCA | PORTA | PORT_PIN14)
#define PORT_EXTINT14_2 (PORT_FUNCA | PORTB | PORT_PIN14)
#define PORT_EXTINT14_3 (PORT_FUNCA | PORTB | PORT_PIN30)
#define PORT_EXTINT15_1 (PORT_FUNCA | PORTA | PORT_PIN15)
#define PORT_EXTINT15_2 (PORT_FUNCA | PORTA | PORT_PIN27)
#define PORT_EXTINT15_3 (PORT_FUNCA | PORTB | PORT_PIN15)
#define PORT_EXTINT15_4 (PORT_FUNCA | PORTB | PORT_PIN31)
/* External wake-up for backup mode */
#define PORT_EXTWAKE0 (PORT_FUNCA | PORTA | PORT_PIN0)
#define PORT_EXTWAKE1 (PORT_FUNCA | PORTA | PORT_PIN1)
#define PORT_EXTWAKE2 (PORT_FUNCA | PORTA | PORT_PIN2)
#define PORT_EXTWAKE3 (PORT_FUNCA | PORTA | PORT_PIN3)
#define PORT_EXTWAKE4 (PORT_FUNCA | PORTA | PORT_PIN4)
#define PORT_EXTWAKE5 (PORT_FUNCA | PORTA | PORT_PIN5)
#define PORT_EXTWAKE6 (PORT_FUNCA | PORTA | PORT_PIN6)
#define PORT_EXTWAKE7 (PORT_FUNCA | PORTA | PORT_PIN7)
/* Generic clock controller I/O */
#define PORT_GCLK_IO0_1 (PORT_FUNCH | PORTA | PORT_PIN14)
#define PORT_GCLK_IO0_2 (PORT_FUNCH | PORTA | PORT_PIN27)
#define PORT_GCLK_IO0_3 (PORT_FUNCH | PORTA | PORT_PIN30)
#define PORT_GCLK_IO0_4 (PORT_FUNCH | PORTB | PORT_PIN14)
#define PORT_GCLK_IO0_5 (PORT_FUNCH | PORTB | PORT_PIN22)
#define PORT_GCLK_IO1_1 (PORT_FUNCH | PORTA | PORT_PIN15)
#define PORT_GCLK_IO1_2 (PORT_FUNCH | PORTB | PORT_PIN15)
#define PORT_GCLK_IO1_3 (PORT_FUNCH | PORTB | PORT_PIN23)
#define PORT_GCLK_IO2_1 (PORT_FUNCH | PORTA | PORT_PIN16)
#define PORT_GCLK_IO2_2 (PORT_FUNCH | PORTB | PORT_PIN16)
#define PORT_GCLK_IO3_1 (PORT_FUNCH | PORTA | PORT_PIN17)
#define PORT_GLCK_IO3_2 (PORT_FUNCH | PORTB | PORT_PIN17)
#define PORT_GCLK_IO4_1 (PORT_FUNCH | PORTA | PORT_PIN10)
#define PORT_GCLK_IO4_2 (PORT_FUNCH | PORTA | PORT_PIN20)
#define PORT_GCLK_IO4_3 (PORT_FUNCH | PORTB | PORT_PIN10)
#define PORT_GCLK_IO5_1 (PORT_FUNCH | PORTA | PORT_PIN11)
#define PORT_GCLK_IO5_2 (PORT_FUNCH | PORTA | PORT_PIN21)
#define PORT_GCLK_IO5_3 (PORT_FUNCH | PORTB | PORT_PIN11)
#define PORT_GCLK_IO6_1 (PORT_FUNCH | PORTA | PORT_PIN22)
#define PORT_GCLK_IO6_2 (PORT_FUNCH | PORTB | PORT_PIN12)
#define PORT_GCLK_IO7_1 (PORT_FUNCH | PORTA | PORT_PIN23)
#define PORT_GCLK_IO7_2 (PORT_FUNCH | PORTB | PORT_PIN13)
/* Non maskable interrupt */
#define PORT_NMI (PORT_FUNCA | PORTA | PORT_PIN8)
/* OpAmps */
#define PORT_OA_NEG0 (PORT_FUNCB | PORTA | PORT_PIN2)
#define PORT_0A_NEG1 (PORT_FUNCB | PORTB | PORT_PIN5)
#define PORT_OA_NEG2 (PORT_FUNCB | PORTB | PORT_PIN6)
#define PORT_OA_OUT0 (PORT_FUNCB | PORTA | PORT_PIN7)
#define PORT_OA_OUT1 (PORT_FUNCB | PORTB | PORT_PIN8)
#define PORT_OA_OUT2 (PORT_FUNCB | PORTA | PORT_PIN4)
#define PORT_OA_POS0 (PORT_FUNCB | PORTA | PORT_PIN6)
#define PORT_OA_POS1 (PORT_FUNCB | PORTB | PORT_PIN9)
#define PORT_OA_POS2 (PORT_FUNCB | PORTA | PORT_PIN5)
/* Serial communication interface (SERCOM) */
#define PORT_SERCOM0_PAD0_1 (PORT_FUNCC | PORTA | PORT_PIN8)
#define PORT_SERCOM0_PAD0_2 (PORT_FUNCD | PORTA | PORT_PIN4)
#define PORT_SERCOM0_PAD1_1 (PORT_FUNCC | PORTA | PORT_PIN9)
#define PORT_SERCOM0_PAD1_2 (PORT_FUNCD | PORTA | PORT_PIN5)
#define PORT_SERCOM0_PAD2_1 (PORT_FUNCC | PORTA | PORT_PIN10)
#define PORT_SERCOM0_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN6)
#define PORT_SERCOM0_PAD3_1 (PORT_FUNCC | PORTA | PORT_PIN11)
#define PORT_SERCOM0_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN7)
#define PORT_SERCOM1_PAD0_1 (PORT_FUNCC | PORTA | PORT_PIN16)
#define PORT_SERCOM1_PAD0_2 (PORT_FUNCD | PORTA | PORT_PIN0)
#define PORT_SERCOM1_PAD1_1 (PORT_FUNCC | PORTA | PORT_PIN17)
#define PORT_SERCOM1_PAD1_2 (PORT_FUNCD | PORTA | PORT_PIN1)
#define PORT_SERCOM1_PAD2_1 (PORT_FUNCC | PORTA | PORT_PIN18)
#define PORT_SERCOM1_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN30)
#define PORT_SERCOM1_PAD3_1 (PORT_FUNCC | PORTA | PORT_PIN19)
#define PORT_SERCOM1_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN31)
#define PORT_SERCOM2_PAD0_1 (PORT_FUNCC | PORTA | PORT_PIN12)
#define PORT_SERCOM2_PAD0_2 (PORT_FUNCD | PORTA | PORT_PIN8)
#define PORT_SERCOM2_PAD1_1 (PORT_FUNCC | PORTA | PORT_PIN13)
#define PORT_SERCOM2_PAD1_2 (PORT_FUNCD | PORTA | PORT_PIN8)
#define PORT_SERCOM2_PAD1_3 (PORT_FUNCD | PORTA | PORT_PIN9)
#define PORT_SERCOM2_PAD2_1 (PORT_FUNCC | PORTA | PORT_PIN14)
#define PORT_SERCOM2_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN10)
#define PORT_SERCOM2_PAD3_1 (PORT_FUNCC | PORTA | PORT_PIN15)
#define PORT_SERCOM2_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN11)
#define PORT_SERCOM3_PAD0_1 (PORT_FUNCC | PORTA | PORT_PIN22)
#define PORT_SERCOM3_PAD0_2 (PORT_FUNCD | PORTA | PORT_PIN16)
#define PORT_SERCOM3_PAD1_1 (PORT_FUNCC | PORTA | PORT_PIN23)
#define PORT_SERCOM3_PAD1_2 (PORT_FUNCD | PORTA | PORT_PIN17)
#define PORT_SERCOM3_PAD2_1 (PORT_FUNCC | PORTA | PORT_PIN24)
#define PORT_SERCOM3_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN18)
#define PORT_SERCOM3_PAD3_1 (PORT_FUNCC | PORTA | PORT_PIN25)
#define PORT_SERCOM3_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN19)
#define PORT_SERCOM3_PAD3_3 (PORT_FUNCD | PORTA | PORT_PIN20)
#define PORT_SERCOM3_PAD3_4 (PORT_FUNCD | PORTA | PORT_PIN21)
#define PORT_SERCOM4_PAD0_1 (PORT_FUNCC | PORTB | PORT_PIN12)
#define PORT_SERCOM4_PAD0_2 (PORT_FUNCD | PORTA | PORT_PIN12)
#define PORT_SERCOM4_PAD0_3 (PORT_FUNCD | PORTB | PORT_PIN9)
#define PORT_SERCOM4_PAD1_1 (PORT_FUNCC | PORTB | PORT_PIN13)
#define PORT_SERCOM4_PAD1_2 (PORT_FUNCD | PORTA | PORT_PIN13)
#define PORT_SERCOM4_PAD1_3 (PORT_FUNCD | PORTB | PORT_PIN8)
#define PORT_SERCOM4_PAD2_1 (PORT_FUNCC | PORTB | PORT_PIN14)
#define PORT_SERCOM4_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN14)
#define PORT_SERCOM4_PAD2_3 (PORT_FUNCD | PORTB | PORT_PIN10)
#define PORT_SERCOM4_PAD3_1 (PORT_FUNCC | PORTB | PORT_PIN15)
#define PORT_SERCOM4_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN15)
#define PORT_SERCOM4_PAD3_3 (PORT_FUNCD | PORTB | PORT_PIN11)
#define PORT_SERCOM5_PAD0_1 (PORT_FUNCC | PORTB | PORT_PIN16)
#define PORT_SERCOM5_PAD0_2 (PORT_FUNCD | PORTA | PORT_PIN22)
#define PORT_SERCOM5_PAD0_3 (PORT_FUNCD | PORTB | PORT_PIN2)
#define PORT_SERCOM5_PAD0_4 (PORT_FUNCD | PORTB | PORT_PIN30)
#define PORT_SERCOM5_PAD1_1 (PORT_FUNCC | PORTB | PORT_PIN17)
#define PORT_SERCOM5_PAD1_2 (PORT_FUNCD | PORTA | PORT_PIN23)
#define PORT_SERCOM5_PAD1_3 (PORT_FUNCD | PORTB | PORT_PIN3)
#define PORT_SERCOM5_PAD1_4 (PORT_FUNCD | PORTB | PORT_PIN31)
#define PORT_SERCOM5_PAD2_1 (PORT_FUNCC | PORTA | PORT_PIN20)
#define PORT_SERCOM5_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN24)
#define PORT_SERCOM5_PAD2_3 (PORT_FUNCD | PORTB | PORT_PIN0)
#define PORT_SERCOM5_PAD2_4 (PORT_FUNCD | PORTB | PORT_PIN22)
#define PORT_SERCOM5_PAD3_1 (PORT_FUNCC | PORTA | PORT_PIN21)
#define PORT_SERCOM5_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN25)
#define PORT_SERCOM5_PAD3_3 (PORT_FUNCD | PORTB | PORT_PIN1)
#define PORT_SERCOM5_PAD3_4 (PORT_FUNCD | PORTB | PORT_PIN23)
/* Peripheral touch controller */
#define PORT_PTC_X0 (PORT_FUNCB | PORTA | PORT_PIN8)
#define PORT_PTC_X1 (PORT_FUNCB | PORTA | PORT_PIN9)
#define PORT_PTC_X2 (PORT_FUNCB | PORTA | PORT_PIN10)
#define PORT_PTC_X3 (PORT_FUNCB | PORTA | PORT_PIN11)
#define PORT_PTC_X4 (PORT_FUNCB | PORTA | PORT_PIN16)
#define PORT_PTC_X5 (PORT_FUNCB | PORTA | PORT_PIN17)
#define PORT_PTC_X6 (PORT_FUNCB | PORTA | PORT_PIN18)
#define PORT_PTC_X7 (PORT_FUNCB | PORTA | PORT_PIN19)
#define PORT_PTC_X8 (PORT_FUNCB | PORTA | PORT_PIN20)
#define PORT_PTC_X9 (PORT_FUNCB | PORTA | PORT_PIN21)
#define PORT_PTC_X10 (PORT_FUNCB | PORTA | PORT_PIN22)
#define PORT_PTC_X11 (PORT_FUNCB | PORTA | PORT_PIN23)
#define PORT_PTC_X12 (PORT_FUNCB | PORTB | PORT_PIN12)
#define PORT_PTC_X13 (PORT_FUNCB | PORTB | PORT_PIN13)
#define PORT_PTC_X14 (PORT_FUNCB | PORTB | PORT_PIN14)
#define PORT_PTC_X15 (PORT_FUNCB | PORTB | PORT_PIN15)
#define PORT_PTC_Y0 (PORT_FUNCB | PORTA | PORT_PIN2)
#define PORT_PTC_Y1 (PORT_FUNCB | PORTA | PORT_PIN3)
#define PORT_PTC_Y2 (PORT_FUNCB | PORTB | PORT_PIN10)
#define PORT_PTC_Y3 (PORT_FUNCB | PORTB | PORT_PIN11)
#define PORT_PTC_Y4 (PORT_FUNCB | PORTA | PORT_PIN6)
#define PORT_PTC_Y5 (PORT_FUNCB | PORTB | PORT_PIN12)
#define PORT_PTC_Y6 (PORT_FUNCB | PORTA | PORT_PIN8)
#define PORT_PTC_Y7 (PORT_FUNCB | PORTA | PORT_PIN9)
#define PORT_PTC_Y8 (PORT_FUNCB | PORTA | PORT_PIN10)
#define PORT_PTC_Y9 (PORT_FUNCB | PORTA | PORT_PIN11)
#define PORT_PTC_Y10 (PORT_FUNCB | PORTB | PORT_PIN4)
#define PORT_PTC_Y11 (PORT_FUNCB | PORTB | PORT_PIN5)
#define PORT_PTC_Y12 (PORT_FUNCB | PORTB | PORT_PIN6)
#define PORT_PTC_Y13 (PORT_FUNCB | PORTB | PORT_PIN7)
#define PORT_PTC_Y14 (PORT_FUNCB | PORTB | PORT_PIN13)
#define PORT_PTC_Y15 (PORT_FUNCB | PORTB | PORT_PIN9)
/* Support Controller */
#define PORT_SUPC_OUT0 (PORT_FUNCH | PORTB | PORT_PIN1)
#define PORT_SUPC_OUT1 (PORT_FUNCH | PORTB | PORT_PIN2)
#define PORT_SUPC_PSOK (PORT_FUNCH | PORTB | PORT_PIN0)
#define PORT_SUPC_VBAT (PORT_FUNCH | PORTB | PORT_PIN3)
/* JTAG/SWI */
#define PORT_SWCLK (PORT_FUNCG | PORTA | PORT_PIN30)
#define PORT_SWDIO (PORT_FUNCG | PORTA | PORT_PIN31)
/* Timer/Counters */
#define PORT_TC0_WO0_1 (PORT_FUNCE | PORTA | PORT_PIN22)
#define PORT_TC0_WO0_2 (PORT_FUNCE | PORTB | PORT_PIN12)
#define PORT_TC0_WO0_3 (PORT_FUNCE | PORTB | PORT_PIN8)
#define PORT_TC0_WO1_1 (PORT_FUNCE | PORTA | PORT_PIN23)
#define PORT_TC0_WO1_2 (PORT_FUNCE | PORTB | PORT_PIN13)
#define PORT_TC0_WO1_3 (PORT_FUNCE | PORTB | PORT_PIN9)
#define PORT_TC1_WO0_1 (PORT_FUNCE | PORTA | PORT_PIN24)
#define PORT_TC1_WO0_2 (PORT_FUNCE | PORTB | PORT_PIN10)
#define PORT_TC1_WO0_3 (PORT_FUNCE | PORTB | PORT_PIN14)
#define PORT_TC1_WO1_1 (PORT_FUNCE | PORTA | PORT_PIN25)
#define PORT_TC1_WO1_2 (PORT_FUNCE | PORTB | PORT_PIN11)
#define PORT_TC1_WO1_3 (PORT_FUNCE | PORTB | PORT_PIN15)
#define PORT_TC2_WO0_1 (PORT_FUNCE | PORTB | PORT_PIN16)
#define PORT_TC2_WO0_2 (PORT_FUNCE | PORTB | PORT_PIN2)
#define PORT_TC2_WO1_1 (PORT_FUNCE | PORTB | PORT_PIN17)
#define PORT_TC2_WO1_2 (PORT_FUNCE | PORTB | PORT_PIN3)
#define PORT_TC3_WO0_1 (PORT_FUNCE | PORTA | PORT_PIN14)
#define PORT_TC3_WO0_2 (PORT_FUNCE | PORTA | PORT_PIN18)
#define PORT_TC3_WO0_3 (PORT_FUNCE | PORTA | PORT_PIN20)
#define PORT_TC3_WO0_4 (PORT_FUNCE | PORTB | PORT_PIN0)
#define PORT_TC3_WO0_5 (PORT_FUNCE | PORTB | PORT_PIN22)
#define PORT_TC3_WO1_1 (PORT_FUNCE | PORTA | PORT_PIN15)
#define PORT_TC3_WO1_2 (PORT_FUNCE | PORTA | PORT_PIN19)
#define PORT_TC3_WO1_3 (PORT_FUNCE | PORTA | PORT_PIN21)
#define PORT_TC3_WO1_4 (PORT_FUNCE | PORTB | PORT_PIN1)
#define PORT_TC3_WO1_5 (PORT_FUNCE | PORTB | PORT_PIN23)
/* Timer/Counters Control */
#define PORT_TCC0_WO0_1 (PORT_FUNCE | PORTA | PORT_PIN4)
#define PORT_TCC0_WO0_2 (PORT_FUNCE | PORTA | PORT_PIN8)
#define PORT_TCCO_WO0_3 (PORT_FUNCE | PORTB | PORT_PIN30)
#define PORT_TCC0_WO1_1 (PORT_FUNCE | PORTA | PORT_PIN5)
#define PORT_TCC0_WO1_2 (PORT_FUNCE | PORTA | PORT_PIN9)
#define PORT_TCC0_WO1_3 (PORT_FUNCE | PORTB | PORT_PIN31)
#define PORT_TCC0_WO2_1 (PORT_FUNCF | PORTA | PORT_PIN10)
#define PORT_TCC0_WO2_2 (PORT_FUNCF | PORTA | PORT_PIN18)
#define PORT_TCC0_WO3_1 (PORT_FUNCF | PORTA | PORT_PIN11)
#define PORT_TCC0_WO3_2 (PORT_FUNCF | PORTA | PORT_PIN19)
#define PORT_TCC0_WO4_1 (PORT_FUNCF | PORTA | PORT_PIN14)
#define PORT_TCC0_WO4_2 (PORT_FUNCF | PORTA | PORT_PIN22)
#define PORT_TCC0_WO4_3 (PORT_FUNCF | PORTB | PORT_PIN10)
#define PORT_TCC0_WO4_4 (PORT_FUNCF | PORTB | PORT_PIN16)
#define PORT_TCC0_WO5_1 (PORT_FUNCF | PORTA | PORT_PIN15)
#define PORT_TCC0_WO5_2 (PORT_FUNCF | PORTA | PORT_PIN23)
#define PORT_TCC0_WO5_3 (PORT_FUNCF | PORTB | PORT_PIN11)
#define PORT_TCC0_WO5_4 (PORT_FUNCF | PORTB | PORT_PIN17)
#define PORT_TCC0_WO6_1 (PORT_FUNCF | PORTA | PORT_PIN12)
#define PORT_TCC0_WO6_2 (PORT_FUNCF | PORTA | PORT_PIN16)
#define PORT_TCC0_WO6_3 (PORT_FUNCF | PORTA | PORT_PIN20)
#define PORT_TCC0_WO6_4 (PORT_FUNCF | PORTB | PORT_PIN12)
#define PORT_TCC0_WO7_1 (PORT_FUNCF | PORTA | PORT_PIN13)
#define PORT_TCC0_WO7_2 (PORT_FUNCF | PORTA | PORT_PIN17)
#define PORT_TCC0_WO7_3 (PORT_FUNCF | PORTA | PORT_PIN21)
#define PORT_TCC0_WO7_4 (PORT_FUNCF | PORTB | PORT_PIN13)
#define PORT_TCC1_WO0_1 (PORT_FUNCE | PORTA | PORT_PIN10)
#define PORT_TCC1_WO0_2 (PORT_FUNCE | PORTA | PORT_PIN30)
#define PORT_TCC1_WO1_1 (PORT_FUNCE | PORTA | PORT_PIN11)
#define PORT_TCC1_WO1_2 (PORT_FUNCE | PORTA | PORT_PIN31)
#define PORT_TCC1_WO1_3 (PORT_FUNCE | PORTA | PORT_PIN6)
#define PORT_TCC1_WO1_4 (PORT_FUNCE | PORTA | PORT_PIN7)
#define PORT_TCC1_WO2_1 (PORT_FUNCF | PORTA | PORT_PIN24)
#define PORT_TCC1_WO2_2 (PORT_FUNCF | PORTA | PORT_PIN8)
#define PORT_TCC1_WO2_3 (PORT_FUNCF | PORTB | PORT_PIN30)
#define PORT_TCC1_WO3_1 (PORT_FUNCF | PORTA | PORT_PIN25)
#define PORT_TCC1_WO3_2 (PORT_FUNCF | PORTA | PORT_PIN9)
#define PORT_TCC1_WO3_3 (PORT_FUNCF | PORTB | PORT_PIN31)
#define PORT_TCC2_WO0_1 (PORT_FUNCE | PORTA | PORT_PIN0)
#define PORT_TCC2_WO0_2 (PORT_FUNCE | PORTA | PORT_PIN12)
#define PORT_TCC2_WO0_3 (PORT_FUNCE | PORTA | PORT_PIN16)
#define PORT_TCC2_WO1_1 (PORT_FUNCE | PORTA | PORT_PIN1)
#define PORT_TCC2_WO1_2 (PORT_FUNCE | PORTA | PORT_PIN13)
#define PORT_TCC2_WO1_3 (PORT_FUNCE | PORTA | PORT_PIN17)
/* USB */
#define PORT_USB_DM (PORT_FUNCG | PORTA | PORT_PIN24)
#define PORT_USB_DP (PORT_FUNCG | PORTA | PORT_PIN25)
#define PORT_USB_SOF (PORT_FUNCG | PORTA | PORT_PIN23)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML21_PINMAP_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/saml_adc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Alexander Vasiljev <alexvasiljev@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* References:
* "Microchip SAM L21 Family Datasheet", Rev A - 02/2017
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_ADC_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_ADC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_ARCH_FAMILY_SAML21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* ADC register offsets *****************************************************/
#define SAM_ADC_CTRLA_OFFSET 0x0000 /* Control A Register */
#define SAM_ADC_CTRLB_OFFSET 0x0001 /* Control B Register */
#define SAM_ADC_REFCTL_OFFSET 0x0002 /* Reference Control Register */
#define SAM_ADC_EVCTRL_OFFSET 0x0003 /* Event Control Register */
#define SAM_ADC_INTENCLR_OFFSET 0x0004 /* Interrupt Enable Clear Register */
#define SAM_ADC_INTENSET_OFFSET 0x0005 /* Interrupt Enable Set Register */
#define SAM_ADC_INTFLAG_OFFSET 0x0006 /* Interrupt Flag Status and Clear Register */
#define SAM_ADC_SEQSTATUS_OFFSET 0x0007 /* Sequence Status Register */
#define SAM_ADC_INPUTCTRL_OFFSET 0x0008 /* Input Control Register */
#define SAM_ADC_CTRLC_OFFSET 0x000A /* Control C Register */
#define SAM_ADC_AVGCTRL_OFFSET 0x000C /* Average Control Register */
#define SAM_ADC_SAMPCTRL_OFFSET 0x000D /* Sampling Time Control Register */
#define SAM_ADC_WINLT_OFFSET 0x000E /* Window Monitor Lower Threshold Register */
#define SAM_ADC_WINUT_OFFSET 0x0010 /* Window Monitor Upper Threshold Register */
#define SAM_ADC_GAINCORR_OFFSET 0x0012 /* Gain Correction Register */
#define SAM_ADC_OFFSETCORR_OFFSET 0x0014 /* Offset Correction Register */
#define SAM_ADC_SWTRIG_OFFSET 0x0018 /* Software Trigger Register */
#define SAM_ADC_DBGCTRL_OFFSET 0x001C /* Debug Control Register */
#define SAM_ADC_SYNCBUSY_OFFSET 0x0020 /* Synchronization Busy Register */
#define SAM_ADC_RESULT_OFFSET 0x0024 /* Result Register */
#define SAM_ADC_SEQCTRL_OFFSET 0x0028 /* Sequence Control Register */
#define SAM_ADC_CALIB_OFFSET 0x002C /* Calibration Register */
/* ADC register addresses ***************************************************/
#define SAM_ADC_CTRLA (SAM_ADC_BASE + SAM_ADC_CTRLA_OFFSET)
#define SAM_ADC_CTRLB (SAM_ADC_BASE + SAM_ADC_CTRLB_OFFSET)
#define SAM_ADC_REFCTL (SAM_ADC_BASE + SAM_ADC_REFCTL_OFFSET)
#define SAM_ADC_EVCTRL (SAM_ADC_BASE + SAM_ADC_EVCTRL_OFFSET)
#define SAM_ADC_INTENCLR (SAM_ADC_BASE + SAM_ADC_INTENCLR_OFFSET)
#define SAM_ADC_INTENSET (SAM_ADC_BASE + SAM_ADC_INTENSET_OFFSET)
#define SAM_ADC_INTFLAG (SAM_ADC_BASE + SAM_ADC_INTFLAG_OFFSET)
#define SAM_ADC_SEQSTATUS (SAM_ADC_BASE + SAM_ADC_SEQSTATUS_OFFSET)
#define SAM_ADC_INPUTCTRL (SAM_ADC_BASE + SAM_ADC_INPUTCTRL_OFFSET)
#define SAM_ADC_CTRLC (SAM_ADC_BASE + SAM_ADC_CTRLC_OFFSET)
#define SAM_ADC_AVGCTRL (SAM_ADC_BASE + SAM_ADC_AVGCTRL_OFFSET)
#define SAM_ADC_SAMPCTRL (SAM_ADC_BASE + SAM_ADC_SAMPCTRL_OFFSET)
#define SAM_ADC_WINLT (SAM_ADC_BASE + SAM_ADC_WINLT_OFFSET)
#define SAM_ADC_WINUT (SAM_ADC_BASE + SAM_ADC_WINUT_OFFSET)
#define SAM_ADC_GAINCORR (SAM_ADC_BASE + SAM_ADC_GAINCORR_OFFSET)
#define SAM_ADC_OFFSETCORR (SAM_ADC_BASE + SAM_ADC_OFFSETCORR_OFFSET)
#define SAM_ADC_SWTRIG (SAM_ADC_BASE + SAM_ADC_SWTRIG_OFFSET)
#define SAM_ADC_DBGCTRL (SAM_ADC_BASE + SAM_ADC_DBGCTRL_OFFSET)
#define SAM_ADC_SYNCBUSY (SAM_ADC_BASE + SAM_ADC_SYNCBUSY_OFFSET)
#define SAM_ADC_RESULT (SAM_ADC_BASE + SAM_ADC_RESULT_OFFSET)
#define SAM_ADC_SEQCTRL (SAM_ADC_BASE + SAM_ADC_SEQCTRL_OFFSET)
#define SAM_ADC_CALIB (SAM_ADC_BASE + SAM_ADC_CALIB_OFFSET)
#endif /* CONFIG_ARCH_FAMILY_SAML21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_ADC_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/saml_aes.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_AES_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_AES_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_ARCH_FAMILY_SAML21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* AES register offsets *****************************************************/
#define SAM_AES_CTRLA_OFFSET 0x0000 /* Control A Register */
#define SAM_AES_CTRLB_OFFSET 0x0004 /* Control B Register */
#define SAM_AES_INTENCLR_OFFSET 0x0005 /* Interrupt Enable Clear Register */
#define SAM_AES_INTENSET_OFFSET 0x0006 /* Interrupt Enable Set Register */
#define SAM_AES_INTENFLAG_OFFSET 0x0007 /* Interrupt Flag Status and Clear Register */
#define SAM_AES_DATABUFPTR_OFFSET 0x0008 /* Data Buffer Pointer Register */
#define SAM_AES_DBGCTRL_OFFSET 0x0009 /* Debug Register */
#define SAM_AES_KEYWORD_OFFSET(n) (0x0010 + ((n) << 2))
# define SAM_AES_KEWORD0_OFFSET 0x0010 /* Keyword 0 Register */
# define SAM_AES_KEWORD1_OFFSET 0x0014 /* Keyword 1 Register */
# define SAM_AES_KEWORD2_OFFSET 0x0018 /* Keyword 2 Register */
# define SAM_AES_KEWORD3_OFFSET 0x001c /* Keyword 3 Register */
# define SAM_AES_KEWORD4_OFFSET 0x0020 /* Keyword 4 Register */
# define SAM_AES_KEWORD5_OFFSET 0x0024 /* Keyword 5 Register */
# define SAM_AES_KEWORD6_OFFSET 0x0028 /* Keyword 6 Register */
#define SAM_AES_DATA_OFFSET 0x0038 /* Data Register */
#define SAM_AES_INTVECT_OFFSET(n) (0x003c + ((n) << 2))
# define SAM_AES_INTVECT0_OFFSET 0x003c /* Initialization Vector 0 Register */
# define SAM_AES_INTVECT1_OFFSET 0x0040 /* Initialization Vector 1 Register */
# define SAM_AES_INTVECT2_OFFSET 0x0044 /* Initialization Vector 2 Register */
# define SAM_AES_INTVECT3_OFFSET 0x0048 /* Initialization Vector 3 Register */
#define SAM_AES_HASHKEY_OFFSET(n) (0x004c + ((n) << 2))
# define SAM_AES_HASHKEY0_OFFSET 0x004c /* Hash Key 0 Register */
# define SAM_AES_HASHKEY1_OFFSET 0x0050 /* Hash Key 1 Register */
# define SAM_AES_HASHKEY2_OFFSET 0x0054 /* Hash Key 2 Register */
# define SAM_AES_HASHKEY3_OFFSET 0x0058 /* Hash Key 3 Register */
#define SAM_AES_GHASH_OFFSET(n) (0x005c + ((n) << 2))
# define SAM_AES_GHASH0_OFFSET 0x005c /* Galois Hash 0 Register */
# define SAM_AES_GHASH1_OFFSET 0x0060 /* Galois Hash 1 Register */
# define SAM_AES_GHASH2_OFFSET 0x0064 /* Galois Hash 2 Register */
# define SAM_AES_GHASH3_OFFSET 0x0068 /* Galois Hash 3 Register */
#define SAM_AES_CIPLEN_OFFSET 0x0070 /* Cipher Length Register */
#define SAM_AES_RANDSEED_OFFSET 0x0074 /* Random Seed Register */
/* AES register addresses ***************************************************/
#define SAM_AES_CTRLA (SAM_AES_BASE+SAM_AES_CTRLA_OFFSET)
#define SAM_AES_CTRLB (SAM_AES_BASE+SAM_AES_CTRLB_OFFSET)
#define SAM_AES_INTENCLR (SAM_AES_BASE+SAM_AES_INTENCLR_OFFSET)
#define SAM_AES_INTENSET (SAM_AES_BASE+SAM_AES_INTENSET_OFFSET)
#define SAM_AES_INTENFLAG (SAM_AES_BASE+SAM_AES_INTENFLAG_OFFSET)
#define SAM_AES_DATABUFPTR (SAM_AES_BASE+SAM_AES_DATABUFPTR_OFFSET)
#define SAM_AES_DBGCTRL (SAM_AES_BASE+SAM_AES_DBGCTRL_OFFSET)
#define SAM_AES_KEYWORD(n) (SAM_AES_BASE+SAM_AES_KEYWORD_OFFSET(n))
# define SAM_AES_KEWORD0 (SAM_AES_BASE+SAM_AES_KEWORD0_OFFSET)
# define SAM_AES_KEWORD1 (SAM_AES_BASE+SAM_AES_KEWORD1_OFFSET)
# define SAM_AES_KEWORD2 (SAM_AES_BASE+SAM_AES_KEWORD2_OFFSET)
# define SAM_AES_KEWORD3 (SAM_AES_BASE+SAM_AES_KEWORD3_OFFSET)
# define SAM_AES_KEWORD4 (SAM_AES_BASE+SAM_AES_KEWORD4_OFFSET)
# define SAM_AES_KEWORD5 (SAM_AES_BASE+SAM_AES_KEWORD5_OFFSET)
# define SAM_AES_KEWORD6 (SAM_AES_BASE+SAM_AES_KEWORD6_OFFSET)
#define SAM_AES_DATA (SAM_AES_BASE+SAM_AES_DATA_OFFSET)
#define SAM_AES_INTVECT(n) (SAM_AES_BASE+SAM_AES_INTVECT_OFFSET(n))
# define SAM_AES_INTVECT0 (SAM_AES_BASE+SAM_AES_INTVECT0_OFFSET)
# define SAM_AES_INTVECT1 (SAM_AES_BASE+SAM_AES_INTVECT1_OFFSET)
# define SAM_AES_INTVECT2 (SAM_AES_BASE+SAM_AES_INTVECT2_OFFSET)
# define SAM_AES_INTVECT3 (SAM_AES_BASE+SAM_AES_INTVECT3_OFFSET)
#define SAM_AES_HASHKEY(n) (SAM_AES_BASE+SAM_AES_HASHKEY_OFFSET(n))
# define SAM_AES_HASHKEY0 (SAM_AES_BASE+SAM_AES_HASHKEY0_OFFSET)
# define SAM_AES_HASHKEY1 (SAM_AES_BASE+SAM_AES_HASHKEY1_OFFSET)
# define SAM_AES_HASHKEY2 (SAM_AES_BASE+SAM_AES_HASHKEY2_OFFSET)
# define SAM_AES_HASHKEY3 (SAM_AES_BASE+SAM_AES_HASHKEY3_OFFSET)
#define SAM_AES_GHASH(n) (SAM_AES_BASE+SAM_AES_GHASH_OFFSET(n))
# define SAM_AES_GHASH0 (SAM_AES_BASE+SAM_AES_GHASH0_OFFSET)
# define SAM_AES_GHASH1 (SAM_AES_BASE+SAM_AES_GHASH1_OFFSET)
# define SAM_AES_GHASH2 (SAM_AES_BASE+SAM_AES_GHASH2_OFFSET)
# define SAM_AES_GHASH3 (SAM_AES_BASE+SAM_AES_GHASH3_OFFSET)
#define SAM_AES_CIPLEN (SAM_AES_BASE+SAM_AES_CIPLEN_OFFSET)
#define SAM_AES_RANDSEED (SAM_AES_BASE+SAM_AES_RANDSEED_OFFSET)
/* AES register bit definitions *********************************************/
/* Control A Register */
#define AES_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
#define AES_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
#define AES_CTRLA_AESMODE_SHIFT (2) /* Bits 2-4: AES mode of operation */
#define AES_CTRLA_AESMODE_MASK (7 << AES_CTRLA_AESMODE_SHIFT)
# define AES_CTRLA_AESMODE_ECB (0 << AES_CTRLA_AESMODE_SHIFT) /* Electronic code book mode */
# define AES_CTRLA_AESMODE_CBC (1 << AES_CTRLA_AESMODE_SHIFT) /* Cipher block chaining mode */
# define AES_CTRLA_AESMODE_OFB (2 << AES_CTRLA_AESMODE_SHIFT) /* Output feedback mode */
# define AES_CTRLA_AESMODE_CFB (3 << AES_CTRLA_AESMODE_SHIFT) /* Cipher feedback mode */
# define AES_CTRLA_AESMODE_CNTR (4 << AES_CTRLA_AESMODE_SHIFT) /* Counter mode */
# define AES_CTRLA_AESMODE_CCM (5 << AES_CTRLA_AESMODE_SHIFT) /* CCM mode */
# define AES_CTRLA_AESMODE_GCM (6 << AES_CTRLA_AESMODE_SHIFT) /* Galois counter mode */
#define AES_CTRLA_CFBS_SHIFT (5) /* Bits 5-7: Cipher feedback block size */
#define AES_CTRLA_CFBS_MASK (7 << AES_CTRLA_CFBS_SHIFT)
# define AES_CTRLA_CFBS_128 (0 << AES_CTRLA_CFBS_SHIFT) /* 128-bit data block */
# define AES_CTRLA_CFBS_64 (1 << AES_CTRLA_CFBS_SHIFT) /* 64-bit data block */
# define AES_CTRLA_CFBS_32 (2 << AES_CTRLA_CFBS_SHIFT) /* 32-bit data block */
# define AES_CTRLA_CFBS_16 (3 << AES_CTRLA_CFBS_SHIFT) /* 16-bit data block */
# define AES_CTRLA_CFBS_8 (4 << AES_CTRLA_CFBS_SHIFT) /* 8-bit data block */
#define AES_CTRLA_KEYSIZE_SHIFT (8) /* Bits 8-9: Encryption key size */
#define AES_CTRLA_KEYSIZE_MASK (3 << AES_CTRLA_KEYSIZE_SHIFT)
# define AES_CTRLA_KEYSIZE_128 (0 << AES_CTRLA_KEYSIZE_SHIFT) /* 128-bit key */
# define AES_CTRLA_KEYSIZE_192 (1 << AES_CTRLA_KEYSIZE_SHIFT) /* 192-bit key */
# define AES_CTRLA_KEYSIZE_256 (2 << AES_CTRLA_KEYSIZE_SHIFT) /* 256-bit key */
#define AES_CTRLA_CIPHER (1 << 10) /* Bit 10: Cipher */
#define AES_CTRLA_STARTMODE (1 << 11) /* Bit 11: Start mode select */
#define AES_CTRLA_LOD (1 << 12) /* Bit 12: Last output data mode */
#define AES_CTRLA_KEYGEN (1 << 13) /* Bit 13: Key generation */
#define AES_CTRLA_XORKEY (1 << 14) /* Bit 14: XOR key */
#define AES_CTRLA_CTYPE_SHIFT (16) /* Bits 16-19: Countermeasure type */
#define AES_CTRLA_CTYPE_MASK (15 << AES_CTRLA_CTYPE_SHIFT)
# define AES_CTRLA_CTYPE_CTYPE1 (1 << AES_CTRLA_CTYPE_SHIFT) /* Countermeasure 1 enabled */
# define AES_CTRLA_CTYPE_CTYPE2 (2 << AES_CTRLA_CTYPE_SHIFT) /* Countermeasure 2 enabled */
# define AES_CTRLA_CTYPE_CTYPE3 (4 << AES_CTRLA_CTYPE_SHIFT) /* Countermeasure 3 enabled */
# define AES_CTRLA_CTYPE_CTYPE4 (8 << AES_CTRLA_CTYPE_SHIFT) /* Countermeasure 4 enabled */
/* Control B Register */
#define AES_CTRLB_START (1 << 0) /* Bit 0: Start encryption/decryption */
#define AES_CTRLB_NEWMSG (1 << 1) /* Bit 1: New message */
#define AES_CTRLB_EOM (1 << 2) /* Bit 2: End of message */
#define AES_CTRLB_GFMUL (1 << 3) /* Bit 3: GF multiplication */
/* Common Bit Definitions for the Interrupt Enable Clear Register, Interrupt
* Enable Set Register, and Interrupt Flag Status and Clear Register
*/
#define AES_INT_ENCCMP (1 << 0) /* Bit 0: Encryption complete interrupt */
#define AES_INT_GFMCMP (1 << 1) /* Bit 1: GF multiplication complete interrupt */
#define AES_INT_ALL 0x03
/* Data Buffer Pointer Register */
#define AES_DATABUFPTR_MASK 0x03 /* Bits 0-1: Data pointer */
/* Debug Register */
#define AES_DBGCTRL_DBGRUN (1 << 0) /* Bit 0: Debug run */
/* Keyword n Register, n = 0-7 (32-value) */
/* Data Register (32-bit value) */
/* Initialization Vector n Register, n=0-3 (32-bit value) */
/* Hash Key n Register, n=0-3 (32-bit value) */
/* Galois Hash n Register, n=0-3 (32-bit value) */
/* Cipher Length Register (32-bit vaoue) */
/* Random Seed Register (32-bit value) */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAML21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_AES_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/saml_dac.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_DAC_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_DAC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_ARCH_FAMILY_SAML21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* DAC register offsets *****************************************************/
#define SAM_DAC_CTRLA_OFFSET 0x0000 /* Control A Register */
#define SAM_DAC_CTRLB_OFFSET 0x0001 /* Control B Register */
#define SAM_DAC_EVCTRL_OFFSET 0x0002 /* Event Control Register */
#define SAM_DAC_INTENCLR_OFFSET 0x0004 /* Interrupt Enable Clear Register */
#define SAM_DAC_INTENSET_OFFSET 0x0005 /* Interrupt Enable Set Register */
#define SAM_DAC_INTFLAG_OFFSET 0x0006 /* Interrupt Flag Status and Clear Register */
#define SAM_DAC_STATUS_OFFSET 0x0007 /* Status Register */
#define SAM_DAC_SYNCBUSY_OFFSET 0x0008 /* Synchronization Busy Register */
#define SAM_DAC_DACCTRL0_OFFSET 0x000c /* DAC0 Control Register */
#define SAM_DAC_DACCTRL1_OFFSET 0x000e /* DAC1 Control Register */
#define SAM_DAC_DATA0_OFFSET 0x0010 /* Data DAC0 Register */
#define SAM_DAC_DATA1_OFFSET 0x0012 /* Data DAC1 Register */
#define SAM_DAC_DATABUF0_OFFSET 0x0014 /* Data Buffer DAC0 Register */
#define SAM_DAC_DATABUF1_OFFSET 0x0016 /* Data Buffer DAC1 Register */
#define SAM_DAC_DBCTRL_OFFSET 0x0017 /* Debug Control Register */
/* DAC register addresses ***************************************************/
#define SAM_DAC_CTRLA (SAM_DAC_BASE+SAM_DAC_CTRLA_OFFSET)
#define SAM_DAC_CTRLB (SAM_DAC_BASE+SAM_DAC_CTRLB_OFFSET)
#define SAM_DAC_EVCTRL (SAM_DAC_BASE+SAM_DAC_EVCTRL_OFFSET)
#define SAM_DAC_INTENCLR (SAM_DAC_BASE+SAM_DAC_INTENCLR_OFFSET)
#define SAM_DAC_INTENSET (SAM_DAC_BASE+SAM_DAC_INTENSET_OFFSET)
#define SAM_DAC_INTFLAG (SAM_DAC_BASE+SAM_DAC_INTFLAG_OFFSET)
#define SAM_DAC_STATUS (SAM_DAC_BASE+SAM_DAC_STATUS_OFFSET)
#define SAM_DAC_SYNCBUSY (SAM_DAC_BASE+SAM_DAC_SYNCBUSY_OFFSET)
#define SAM_DAC_DACCTRL0 (SAM_DAC_BASE+SAM_DAC_DACCTRL0_OFFSET)
#define SAM_DAC_DACCTRL1 (SAM_DAC_BASE+SAM_DAC_DACCTRL1_OFFSET)
#define SAM_DAC_DATA0 (SAM_DAC_BASE+SAM_DAC_DATA0_OFFSET)
#define SAM_DAC_DATA1 (SAM_DAC_BASE+SAM_DAC_DATA1_OFFSET)
#define SAM_DAC_DATABUF0 (SAM_DAC_BASE+SAM_DAC_DATABUF0_OFFSET)
#define SAM_DAC_DATABUF1 (SAM_DAC_BASE+SAM_DAC_DATABUF1_OFFSET)
#define SAM_DAC_DBCTRL (SAM_DAC_BASE+SAM_DAC_DBCTRL_OFFSET)
/* DAC register bit definitions *********************************************/
/* Control A Register */
#define DAC_CTRLA_SWRTS (1 << 0) /* Bit 0: Software reset */
#define DAC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable DAC controller */
/* Control B Register */
#define DAC_CTRLB_DIFF (1 << 0) /* Bit 0: Differential mode enable */
#define DAC_CTRLB_REFSEL_SHIFT (1) /* Bit 1-2: Reference selection */
#define DAC_CTRLB_REFSEL_MASK (3 << DAC_CTRLB_REFSEL_SHIFT)
# define DAC_CTRLB_REFSEL_VREFAU (0 << DAC_CTRLB_REFSEL_SHIFT) /* Unbuffered external voltage reference */
# define DAC_CTRLB_REFSEL_VDDANA (1 << DAC_CTRLB_REFSEL_SHIFT) /* Voltage supply */
# define DAC_CTRLB_REFSEL_VREFAB (2 << DAC_CTRLB_REFSEL_SHIFT) /* Buffered external voltage reference */
# define DAC_CTRLB_REFSEL_INTREF (3 << DAC_CTRLB_REFSEL_SHIFT) /* Internal bandgap reference */
/* Event Control Register */
#define DAC_EVCTRL_STARTEI0 (1 << 0) /* Bit 0: Start conversion event input DAC0 */
#define DAC_EVCTRL_STARTEI1 (1 << 1) /* Bit 1: Start conversion event input DAC1 */
#define DAC_EVCTRL_EMTPYEO0 (1 << 2) /* Bit 2: Data buffer empty event output DAC0 */
#define DAC_EVCTRL_EMTPYEO1 (1 << 3) /* Bit 3: Data buffer empty event output DAC1 */
#define DAC_EVCTRL_INVEI0 (1 << 4) /* Bit 4: Enable inversion of DAC0 input event */
#define DAC_EVCTRL_INVEI1 (1 << 5) /* Bit 5: Enable inversion of DAC1 input event */
/* Common bit definitions for Interrupt Enable Clear Register,
* Interrupt Enable Set Register,
* and Interrupt Flag Status and Clear Register
*/
#define DAC_INT_UNDERRUN0 (1 << 0) /* Bit 0: Underrun interrupt for DAC2 */
#define DAC_INT_UNDERRUN1 (1 << 1) /* Bit 1: Underrun interrupt for DAC1 */
#define DAC_INT_EMPTY0 (1 << 2) /* Bit 2: Data buffer 0 empty interrupt */
#define DAC_INT_EMPTY1 (1 << 3) /* Bit 3: Data buffer 1 empty interrupt */
#define DAC_INT_ALL 0x0f
/* Status Register */
#define DAC_STATUS_READY0 (1 << 0) /* Bit 0: DAC0 startup ready */
#define DAC_STATUS_READY1 (1 << 1) /* Bit 1: DAC1 startup ready */
#define DAC_STATUS_EOC0 (1 << 2) /* Bit 2: DAC0 end of conversion */
#define DAC_STATUS_EOC1 (1 << 3) /* Bit 3: DAC1 end of conversion */
/* Synchronization Busy Register */
#define DAC_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset */
#define DAC_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: DAC enable status */
#define DAC_SYNCBUSY_DATA0 (1 << 2) /* Bit 2: Data DAC0 */
#define DAC_SYNCBUSY_DATA1 (1 << 3) /* Bit 3: Data DAC1 */
#define DAC_SYNCBUSY_DATABUF0 (1 << 4) /* Bit 4: Data buffer DAC0 */
#define DAC_SYNCBUSY_DATABUF1 (1 << 5) /* Bit 5: Data buffer DAC1 */
/* DAC0/1 Control Register */
#define DAC_DACCTRL_LEFTADJ (1 << 0) /* Bit 0: Left adjusted data */
#define DAC_DACCTRL_ENABLE (1 << 1) /* Bit 1: Enable DAC */
#define DAC_DACCTRL_CCTRL_SHIFT (2) /* Bit 2-3: Current control */
#define DAC_DACCTRL_CCTRL_MASK (3 << DAC_DACCTRL_CCTRL_SHIFT)
# define DAC_DACCTRL_CCTRL_CC100K (0 << DAC_DACCTRL_CCTRL_SHIFT) /* GCLK_DAC <= 1.2MHz */
# define DAC_DACCTRL_CCTRL_CC1M (1 << DAC_DACCTRL_CCTRL_SHIFT) /* 1.2MHz < GCLK_DAC <= 6MHz */
# define DAC_DACCTRL_CCTRL_CC2M (2 << DAC_DACCTRL_CCTRL_SHIFT) /* 6MHz < GCLK_DAC <= 12MHz */
#define DAC_DACCTRL_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
#define DAC_DACCTRL_DITHER (1 << 7) /* Bit 7: Dithering mode */
#define DAC_DACCTRL_REFRESH_SHIFT (8) /* Bit 8-11: Refresh period */
#define DAC_DACCTRL_REFRESH_MASK (15 << DAC_DACCTRL_REFRESH_SHIFT)
# define DAC_DACCTRL_REFRESH(n) ((uin16_t)(n) << DAC_DACCTRL_REFRESH_SHIFT)
/* Data DAC0/1 Register (16-bit data) */
/* Data Buffer DAC0/1 Register (16-bit data) */
/* Debug Control Register */
#define DAC_DBCTRL_DBGRUN (1 << 0) /* Bit 0: Debug run */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAML21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_DAC_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/saml_dmac.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_DMAC_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_DMAC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_ARCH_FAMILY_SAML21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* DMAC register offsets ****************************************************/
#define SAM_DMAC_CTRL_OFFSET 0x0000 /* Control Register */
#define SAM_DMAC_CRCCTRL_OFFSET 0x0002 /* CRC Control Register */
#define SAM_DMAC_CRCDATAIN_OFFSET 0x0004 /* CRC Data Input Register */
#define SAM_DMAC_CRCCHKSUM_OFFSET 0x0008 /* CRC Checksum Register */
#define SAM_DMAC_CRCSTATUS_OFFSET 0x000c /* CRC Status Register */
#define SAM_DMAC_DBGCTRL_OFFSET 0x000d /* Debug Control Register */
#define SAM_DMAC_QOSCTRL_OFFSET 0x000e /* Quality of Service Control Register */
#define SAM_DMAC_SWTRIGCTRL_OFFSET 0x0010 /* Software Trigger Control Register */
#define SAM_DMAC_PRICTRL0_OFFSET 0x0014 /* Priority Control 0 Register */
#define SAM_DMAC_INTPEND_OFFSET 0x0020 /* Interrupt Pending Register */
#define SAM_DMAC_INTSTATUS_OFFSET 0x0024 /* Interrupt Status Register */
#define SAM_DMAC_BUSYCH_OFFSET 0x0028 /* Busy Channels Register */
#define SAM_DMAC_PENDCH_OFFSET 0x002c /* Pending Channels Register */
#define SAM_DMAC_ACTIVE_OFFSET 0x0030 /* Active Channels and Levels Register */
#define SAM_DMAC_BASEADDR_OFFSET 0x0034 /* Descriptor Memory Section Base Address Register */
#define SAM_DMAC_WRBADDR_OFFSET 0x0038 /* Write-Back Memory Section Base Address Register */
#define SAM_DMAC_CHID_OFFSET 0x003f /* Channel ID Register */
#define SAM_DMAC_CHCTRLA_OFFSET 0x0040 /* Channel Control A Register */
#define SAM_DMAC_CHCTRLB_OFFSET 0x0044 /* Channel Control B Register */
#define SAM_DMAC_CHINTENCLR_OFFSET 0x004c /* Channel Interrupt Enable Clear Register */
#define SAM_DMAC_CHINTENSET_OFFSET 0x004d /* Channel Interrupt Enable Set Register */
#define SAM_DMAC_CHINTFLAG_OFFSET 0x004e /* Channel Interrupt Flag Status and Clear Register */
#define SAM_DMAC_CHSTATUS_OFFSET 0x004f /* Channel Status Register */
/* LPSRAM Registers Relative to BASEADDR or WRBADDR */
#define SAM_LPSRAM_BTCTRL_OFFSET 0x0000 /* Block Transfer Control Register */
#define SAM_LPSRAM_BTCNT_OFFSET 0x0002 /* Block Transfer Count Register */
#define SAM_LPSRAM_SRCADDR_OFFSET 0x0004 /* Block Transfer Source Address Register */
#define SAM_LPSRAM_DSTADDR_OFFSET 0x0008 /* Block Transfer Destination Address Register */
#define SAM_LPSRAM_DESCADDR_OFFSET 0x000c /* Next Address Descriptor Register */
/* DMAC register addresses **************************************************/
#define SAM_DMAC_CTRL (SAM_DMAC_BASE+SAM_DMAC_CTRL_OFFSET)
#define SAM_DMAC_CRCCTRL (SAM_DMAC_BASE+SAM_DMAC_CRCCTRL_OFFSET)
#define SAM_DMAC_CRCDATAIN (SAM_DMAC_BASE+SAM_DMAC_CRCDATAIN_OFFSET)
#define SAM_DMAC_CRCCHKSUM (SAM_DMAC_BASE+SAM_DMAC_CRCCHKSUM_OFFSET)
#define SAM_DMAC_CRCSTATUS (SAM_DMAC_BASE+SAM_DMAC_CRCSTATUS_OFFSET)
#define SAM_DMAC_DBGCTRL (SAM_DMAC_BASE+SAM_DMAC_DBGCTRL_OFFSET)
#define SAM_DMAC_QOSCTRL (SAM_DMAC_BASE+SAM_DMAC_QOSCTRL_OFFSET)
#define SAM_DMAC_SWTRIGCTRL (SAM_DMAC_BASE+SAM_DMAC_SWTRIGCTRL_OFFSET)
#define SAM_DMAC_PRICTRL0 (SAM_DMAC_BASE+SAM_DMAC_PRICTRL0_OFFSET)
#define SAM_DMAC_INTPEND (SAM_DMAC_BASE+SAM_DMAC_INTPEND_OFFSET)
#define SAM_DMAC_INTSTATUS (SAM_DMAC_BASE+SAM_DMAC_INTSTATUS_OFFSET)
#define SAM_DMAC_BUSYCH (SAM_DMAC_BASE+SAM_DMAC_BUSYCH_OFFSET)
#define SAM_DMAC_PENDCH (SAM_DMAC_BASE+SAM_DMAC_PENDCH_OFFSET)
#define SAM_DMAC_ACTIVE (SAM_DMAC_BASE+SAM_DMAC_ACTIVE_OFFSET)
#define SAM_DMAC_BASEADDR (SAM_DMAC_BASE+SAM_DMAC_BASEADDR_OFFSET)
#define SAM_DMAC_WRBADDR (SAM_DMAC_BASE+SAM_DMAC_WRBADDR_OFFSET)
#define SAM_DMAC_CHID (SAM_DMAC_BASE+SAM_DMAC_CHID_OFFSET)
#define SAM_DMAC_CHCTRLA (SAM_DMAC_BASE+SAM_DMAC_CHCTRLA_OFFSET)
#define SAM_DMAC_CHCTRLB (SAM_DMAC_BASE+SAM_DMAC_CHCTRLB_OFFSET)
#define SAM_DMAC_CHINTENCLR (SAM_DMAC_BASE+SAM_DMAC_CHINTENCLR_OFFSET)
#define SAM_DMAC_CHINTENSET (SAM_DMAC_BASE+SAM_DMAC_CHINTENSET_OFFSET)
#define SAM_DMAC_CHINTFLAG (SAM_DMAC_BASE+SAM_DMAC_CHINTFLAG_OFFSET)
#define SAM_DMAC_CHSTATUS (SAM_DMAC_BASE+SAM_DMAC_CHSTATUS_OFFSET)
/* DMAC register bit definitions ********************************************/
/* Control Register */
#define DMAC_CTRL_SWRST (1 << 0) /* Bit 0: Software Reset */
#define DMAC_CTRL_DMAENABLE (1 << 1) /* Bit 1: DMA Enable */
#define DMAC_CTRL_CRCENABLE (1 << 2) /* Bit 2: CRC Enable */
#define DMAC_CTRL_LVLEN0 (1 << 8) /* Bit 8: Priority level 0 Enable */
#define DMAC_CTRL_LVLEN1 (1 << 9) /* Bit 9: Priority level 1 Enable */
#define DMAC_CTRL_LVLEN2 (1 << 10) /* Bit 10: Priority level 2 Enable */
/* CRC Control Register */
#define DMAC_CRCCTRL_CRCBEATSIZE_SHIFT (0) /* Bits 0-1: CRC beat size */
#define DMAC_CRCCTRL_CRCBEATSIZE_MASK (3 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT)
# define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (0 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 8-bit bus transfer */
# define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (1 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 16-bit bus transfer */
# define DMAC_CRCCTRL_CRCBEATSIZE_WORD (2 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 32-bit bus transfer */
#define DMAC_CRCCTRL_CRCPOLY_SHIFT (2) /* Bits 2-3: CRC polynomial type */
#define DMAC_CRCCTRL_CRCPOLY_MASK (3 < DMAC_CRCCTRL_CRCPOLY_SHIFT)
# define DMAC_CRCCTRL_CRCPOLY_CRC16 (0 < DMAC_CRCCTRL_CRCPOLY_SHIFT) /* CRC-16 (CRC-CCITT) */
# define DMAC_CRCCTRL_CRCPOLY_CRC32 (1 < DMAC_CRCCTRL_CRCPOLY_SHIFT) /* CRC32 (IEEE 802.3) */
#define DMAC_CRCCTRL_CRCSRC_SHIFT (8) /* Bits 8-13: CRC Input Source */
#define DMAC_CRCCTRL_CRCSRC_MASK (0x3f < DMAC_CRCCTRL_CRCSRC_SHIFT)
# define DMAC_CRCCTRL_CRCSRC_NOACTION (0 < DMAC_CRCCTRL_CRCSRC_SHIFT) /* No action */
# define DMAC_CRCCTRL_CRCSRC_IO (1 < DMAC_CRCCTRL_CRCSRC_SHIFT) /* I/O interface */
# define DMAC_CRCCTRL_CRCSRC_CHAN(n) (((uint32_t)(n) + 0x20) < DMAC_CRCCTRL_CRCSRC_SHIFT)
/* CRC Data Input Register (32-bit value) */
/* CRC Checksum Register (32-bit value) */
/* CRC Status Register */
#define DMAC_CRCSTATUS_CRCBUSY (1 << 0) /* Bit 0: CRC module busy */
#define DMAC_CRCSTATUS_CRCZERO (1 << 1) /* Bit 1: CRC zero */
/* Debug Control Register */
#define DMAC_DBGCTRL_DBGRUN (1 << 0) /* Bit 0: Debug run */
/* Quality of Service Control Register */
#define DMAC_QOSCTRL_WRBQOS_SHIFT (0) /* Bits 0-1: Write back quality of service */
#define DMAC_QOSCTRL_WRBQOS_MASK (3 << DMAC_QOSCTRL_WRBQOS_SHIFT)
# define DMAC_QOSCTRL_WRBQOS_DISABLE (0 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Background */
# define DMAC_QOSCTRL_WRBQOS_LOW (1 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Sensitive bandwidth */
# define DMAC_QOSCTRL_WRBQOS_MEDIUM (2 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Sensitive latency */
# define DMAC_QOSCTRL_WRBQOS_HIGH (3 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Critical latency */
#define DMAC_QOSCTRL_FQOS_SHIFT (2) /* Bits 2-3: Fetch quality of service */
#define DMAC_QOSCTRL_FQOS_MASK (3 << DMAC_QOSCTRL_FQOS_SHIFT)
# define DMAC_QOSCTRL_FQOS_DISABLE (0 << DMAC_QOSCTRL_FQOS_SHIFT) /* Background */
# define DMAC_QOSCTRL_FQOS_LOW (1 << DMAC_QOSCTRL_FQOS_SHIFT) /* Sensitive bandwidth */
# define DMAC_QOSCTRL_FQOS_MEDIUM (2 << DMAC_QOSCTRL_FQOS_SHIFT) /* Sensitive latency */
# define DMAC_QOSCTRL_FQOS_HIGH (3 << DMAC_QOSCTRL_FQOS_SHIFT) /* Critical latency */
#define DMAC_QOSCTRL_DQOS_SHIFT (4) /* Bits 4-5: Data transfer quality of service */
#define DMAC_QOSCTRL_DQOS_MASK (3 << DMAC_QOSCTRL_DQOS_SHIFT)
# define DMAC_QOSCTRL_DQOS_DISABLE (0 << DMAC_QOSCTRL_DQOS_SHIFT) /* Background */
# define DMAC_QOSCTRL_DQOS_LOW (1 << DMAC_QOSCTRL_DQOS_SHIFT) /* Sensitive bandwidth */
# define DMAC_QOSCTRL_DQOS_MEDIUM (2 << DMAC_QOSCTRL_DQOS_SHIFT) /* Sensitive latency */
# define DMAC_QOSCTRL_DQOS_HIGH (3 << DMAC_QOSCTRL_DQOS_SHIFT) /* Critical latency */
/* Common bit definitions for: Software Trigger Control Register,
* Interrupt Status Register, Busy Channels Register, and Pending Channels
* Register
*/
#define DMAC_CHAN(n) (1 << (n)) /* DMAC Channel n, n=0-15 */
/* Priority Control 0 Register */
#define DMAC_PRICTRL0_LVLPRI0_SHIFT (0) /* Bits 0-3: Level 0 channel priority number */
#define DMAC_PRICTRL0_LVLPRI0_MASK (15 << DMAC_PRICTRL0_LVLPRI0_SHIFT)
# define DMAC_PRICTRL0_LVLPRI0(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI0_SHIFT)
#define DMAC_PRICTRL0_RRLVLEN0 (1 << 7) /* Bit 7: Level 0 round-robin arbitrarion enable */
#define DMAC_PRICTRL0_LVLPRI1_SHIFT (8) /* Bits 8-11: Level 1 channel priority number */
#define DMAC_PRICTRL0_LVLPRI1_MASK (15 << DMAC_PRICTRL0_LVLPRI1_SHIFT)
# define DMAC_PRICTRL0_LVLPRI1(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI1_SHIFT)
#define DMAC_PRICTRL0_RRLVLEN1 (1 << 15) /* Bit 15: Level 1 round-robin arbitrarion enable */
#define DMAC_PRICTRL0_LVLPRI2_SHIFT (16) /* Bits 16-18: Level 2 channel priority number */
#define DMAC_PRICTRL0_LVLPRI2_MASK (7 << DMAC_PRICTRL0_LVLPRI2_SHIFT)
# define DMAC_PRICTRL0_LVLPRI2(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI2_SHIFT)
#define DMAC_PRICTRL0_RRLVLEN2 (1 << 23) /* Bit 23: Level 2 round-robin arbitrarion enable */
/* Interrupt Pending Register */
#define DMAC_INTPEND_ID_SHIFT (0) /* Bit 0-3: Channel ID */
#define DMAC_INTPEND_ID_MASK (15 << DMAC_INTPEND_ID_SHIFT)
#define DMAC_INTPEND_TERR (1 << 8) /* Bit 8: Transfer error */
#define DMAC_INTPEND_TCMPL (1 << 9) /* Bit 9: Transfer complete */
#define DMAC_INTPEND_SUSP (1 << 10) /* Bit 10: Channel suspend */
#define DMAC_INTPEND_FERR (1 << 13) /* Bit 13: Fetch error */
#define DMAC_INTPEND_BUSY (1 << 14) /* Bit 14: Busy */
#define DMAC_INTPEND_PEND (1 << 15) /* Bit 15: Pending */
/* Active Channels and Levels Register */
#define DMAC_ACTIVE_LVLEX0 (1 << 0) /* Bit 0: Level 0 channel trigger request executing */
#define DMAC_ACTIVE_LVLEX1 (1 << 1) /* Bit 1: Level 1 channel trigger request executing */
#define DMAC_ACTIVE_LVLEX2 (1 << 2) /* Bit 2: Level 2 channel trigger request executing */
#define DMAC_ACTIVE_ID_SHIFT (8) /* Bits 8-11: Active channel ID */
#define DMAC_ACTIVE_ID_MASK (15 << DMAC_ACTIVE_ID_SHIFT)
#define DMAC_ACTIVE_ABUSY (1 << 15) /* Bit 15: Active channel busy */
#define DMAC_ACTIVE_BTCNT_SHIFT (16) /* Bit 16-31: Active channel block transfer count */
#define DMAC_ACTIVE_BTCNT_MASK (0xffff << DMAC_ACTIVE_BTCNT_SHIFT)
/* Descriptor Memory Section Base Address Register (32-bit address) */
/* Write-Back Memory Section Base Address Register (31-bit address) */
/* Channel ID Register */
#define DMAC_CHID_MASK 0x0f /* Bits 0-3: Channel ID */
/* Channel Control A Register */
#define DMAC_CHCTRLA_SWRST (1 << 0) /* Bit 0: Channel software reset */
#define DMAC_CHCTRLA_ENABLE (1 << 1) /* Bit 1: Channel enable */
#define DMAC_CHCTRLA_RUNSTDBY (1 << 6) /* Bit 6: Channel run in standby */
/* Channel Control B Register */
#define DMAC_CHCTRLB_EVACT_SHIFT (0) /* Bits 0-2: Event input action */
#define DMAC_CHCTRLB_EVACT_MASK (7 << DMAC_CHCTRLB_EVACT_SHIFT)
# define DMAC_CHCTRLB_EVACT_NOACT (0 << DMAC_CHCTRLB_EVACT_SHIFT) /* No action */
# define DMAC_CHCTRLB_EVACT_TRIG (1 << DMAC_CHCTRLB_EVACT_SHIFT) /* Normal Transfer and Conditional Transfer on Strobe
* trigger */
# define DMAC_CHCTRLB_EVACT_CTRIG (2 << DMAC_CHCTRLB_EVACT_SHIFT) /* Conditional transfer trigger */
# define DMAC_CHCTRLB_EVACT_CBLOCK (3 << DMAC_CHCTRLB_EVACT_SHIFT) /* Conditional block transfer */
# define DMAC_CHCTRLB_EVACT_SUSPEND (4 << DMAC_CHCTRLB_EVACT_SHIFT) /* Channel suspend operation */
# define DMAC_CHCTRLB_EVACT_RESUME (5 << DMAC_CHCTRLB_EVACT_SHIFT) /* Channel resume operation */
# define DMAC_CHCTRLB_EVACT_SSKIP (6 << DMAC_CHCTRLB_EVACT_SHIFT) /* Skip next block suspend action */
#define DMAC_CHCTRLB_EVIE (1 << 3) /* Bit 3: Channel event input enable */
#define DMAC_CHCTRLB_EVOE (1 << 4) /* Bit 4: Channel event output enable */
#define DMAC_CHCTRLB_LVL_SHIFT (5) /* Bits 5-6: Channel arbitration level */
#define DMAC_CHCTRLB_LVL_MASK (3 << DMAC_CHCTRLB_LVL_SHIFT)
# define DMAC_CHCTRLB_LVL(n) ((uint32_t)(n) << DMAC_CHCTRLB_LVL_SHIFT)
# define DMAC_CHCTRLB_LVL_LVL0 (0 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 0 */
# define DMAC_CHCTRLB_LVL_LVL1 (1 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 1 */
# define DMAC_CHCTRLB_LVL_LVL2 (2 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 2 */
# define DMAC_CHCTRLB_LVL_LVL3 (3 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 3 */
#define DMAC_CHCTRLB_TRIGSRC_SHIFT (8) /* Bits 8-13: Trigger source */
#define DMAC_CHCTRLB_TRIGSRC_MASK (0x3f << DMAC_CHCTRLB_TRIGSRC_SHIFT)
# define DMAC_CHCTRLB_TRIGSRC(n) ((uint32_t)(n) << DMAC_CHCTRLB_TRIGSRC_SHIFT)
#define DMAC_CHCTRLB_TRIGACT_SHIFT (22) /* Bits 22-23: Trigger action */
#define DMAC_CHCTRLB_TRIGACT_MASK (3 << DMAC_CHCTRLB_TRIGACT_SHIFT)
# define DMAC_CHCTRLB_TRIGACT_BLOCK (0 << DMAC_CHCTRLB_TRIGACT_SHIFT) /* One trigger required for each action */
# define DMAC_CHCTRLB_TRIGACT_BEAT (2 << DMAC_CHCTRLB_TRIGACT_SHIFT) /* One trigger required for beat transfer */
# define DMAC_CHCTRLB_TRIGACT_TRANSACT (3 << DMAC_CHCTRLB_TRIGACT_SHIFT) /* One trigger required for each transaction */
#define DMAC_CHCTRLB_CMD_SHIFT (24) /* Bits 24-25: Software command */
#define DMAC_CHCTRLB_CMD_MASK (3 << DMAC_CHCTRLB_CMD_SHIFT)
# define DMAC_CHCTRLB_CMD_NOACTION (0 << DMAC_CHCTRLB_CMD_SHIFT) /* No action */
# define DMAC_CHCTRLB_CMD_SUSPEND (1 << DMAC_CHCTRLB_CMD_SHIFT) /* Channel suspend operation */
# define DMAC_CHCTRLB_CMD_RESUME (2 << DMAC_CHCTRLB_CMD_SHIFT) /* Channel resume operation */
/* Values for use with the DMAC_CHCTRLB_TRIGSRC(n) macro: */
#define DMAC_TRIGSRC_DISABLE (0) /* Only software/event triggers */
#define DMAC_TRIGSRC_SERCOM0_RX (1) /* SERCOM0 RX Trigger */
#define DMAC_TRIGSRC_SERCOM0_TX (2) /* SERCOM0 TX Trigger */
#define DMAC_TRIGSRC_SERCOM1_RX (3) /* SERCOM1 RX Trigger */
#define DMAC_TRIGSRC_SERCOM1_TX (4) /* SERCOM1 TX Trigger */
#define DMAC_TRIGSRC_SERCOM2_RX (5) /* SERCOM2 RX Trigger */
#define DMAC_TRIGSRC_SERCOM2_TX (6) /* SERCOM2 TX Trigger */
#define DMAC_TRIGSRC_SERCOM3_RX (7) /* SERCOM3 RX Trigger */
#define DMAC_TRIGSRC_SERCOM3_TX (8) /* SERCOM3 TX Trigger */
#define DMAC_TRIGSRC_SERCOM4_RX (9) /* SERCOM4 RX Trigger */
#define DMAC_TRIGSRC_SERCOM4_TX (10) /* SERCOM4 TX Trigger */
#define DMAC_TRIGSRC_TCC0_OVF (11) /* TCC0 Overflow Trigger */
#define DMAC_TRIGSRC_TCC0_MC0 (12) /* TCC0 Match/Compare 0 Trigger */
#define DMAC_TRIGSRC_TCC0_MC1 (13) /* TCC0 Match/Compare 1 Trigger */
#define DMAC_TRIGSRC_TCC0_MC2 (14) /* TCC0 Match/Compare 2 Trigger */
#define DMAC_TRIGSRC_TCC0_MC3 (15) /* TCC0 Match/Compare 3 Trigger */
#define DMAC_TRIGSRC_TCC1_OVF (16) /* TCC1 Overflow Trigger */
#define DMAC_TRIGSRC_TCC1_MC0 (17) /* TCC1 Match/Compare 0 Trigger */
#define DMAC_TRIGSRC_TCC1_MC1 (18) /* TCC1 Match/Compare 1 Trigger */
#define DMAC_TRIGSRC_TCC2_OVF (19) /* TCC2 Overflow Trigger */
#define DMAC_TRIGSRC_TCC2_MC0 (20) /* TCC2 Match/Compare 0 Trigger */
#define DMAC_TRIGSRC_TCC2_MC1 (21) /* TCC2 Match/Compare 1 Trigger */
#define DMAC_TRIGSRC_TC0_OVF (22) /* TC0 Overflow Trigger */
#define DMAC_TRIGSRC_TC0_MC0 (23) /* TC0 Match/Compare 0 Trigger */
#define DMAC_TRIGSRC_TC0 MC1 (24) /* TC0 Match/Compare 1 Trigger */
#define DMAC_TRIGSRC_TC1_OVF (25) /* TC1 Overflow Trigger */
#define DMAC_TRIGSRC_TC1_MC0 (26) /* TC1 Match/Compare 0 Trigger */
#define DMAC_TRIGSRC_TC1_MC1 (27) /* TC1 Match/Compare 1 Trigger */
#define DMAC_TRIGSRC_TC2_OVF (28) /* TC2 Overflow Trigger */
#define DMAC_TRIGSRC_TC2_MC0 (29) /* TC2 Match/Compare 0 Trigger */
#define DMAC_TRIGSRC_TC2_MC1 (30) /* TC2 Match/Compare 1 Trigger */
#define DMAC_TRIGSRC_TC3_OVF (31) /* TC3 Overflow Trigger */
#define DMAC_TRIGSRC_TC3_MC0 (32) /* TC3 Match/Compare 0 Trigger */
#define DMAC_TRIGSRC_TC3_MC1 (33) /* TC3 Match/Compare 1 Trigger */
#define DMAC_TRIGSRC_TC4_OVF (34) /* TC4 Overflow Trigger */
#define DMAC_TRIGSRC_TC4_MC0 (35) /* TC4 Match/Compare 0 Trigger */
#define DMAC_TRIGSRC_TC4_MC1 (36) /* TC4 Match/Compare 1 Trigger */
#define DMAC_TRIGSRC_ADC_RESRDY (37) /* ADC Result Ready Trigger */
#define DMAC_TRIGSRC_DAC0_EMPTY (38) /* DAC0 Empty Trigger */
#define DMAC_TRIGSRC_DAC1_EMPTY (39) /* DAC1 Empty Trigger */
#define DMAC_TRIGSRC_AES_WR (44) /* AES Write Trigger */
#define DMAC_TRIGSRC_AES_RD (45) /* AES Read Trigger */
/* Common register bit definitions: Channel Interrupt Enable Clear Register,
* Channel Interrupt Enable Set Register, and Channel Interrupt Flag
* Status and Clear Register
*/
#define DMAC_INT_TERR (1 << 0) /* Bit 0: Transfer error interrupt */
#define DMAC_INT_TCMPL (1 << 1) /* Bit 1: Channel transfer complete interrupt */
#define DMAC_INT_SUSP (1 << 2) /* Bit 2: Channel suspend interrupt */
#define DMAC_INT_ALL (0x07)
/* Channel Status Register */
#define DMAC_CHSTATUS_PEND (1 << 0) /* Bit 0: Channel pending */
#define DMAC_CHSTATUS_BUSY (1 << 1) /* Bit 1: Channel busy */
#define DMAC_CHSTATUS_FERR (1 << 2) /* Bit 2: Channel fetch error */
/* Block Transfer Control Register */
#define LPSRAM_BTCTRL_VALID (1 << 0) /* Bit 0: Descriptor valid */
#define LPSRAM_BTCTRL_EVOSEL_SHIFT (1) /* Bits 1-2: Event output selection */
#define LPSRAM_BTCTRL_EVOSEL_MASK (3 << LPSRAM_BTCTRL_EVOSEL_SHIFT)
# define LPSRAM_BTCTRL_EVOSEL_DISABLE (0 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event generation disabled */
# define LPSRAM_BTCTRL_EVOSEL_BLOCK (1 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event strobe when block transfer complete */
# define LPSRAM_BTCTRL_EVOSEL_BEAT (3 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event strobe when beat transfer complete */
#define LPSRAM_BTCTRL_BLOCKACT_SHIFT (3) /* Bits 3-4: Block action */
#define LPSRAM_BTCTRL_BLOCKACT_MASK (3 << LPSRAM_BTCTRL_BLOCKACT_SHIFT)
# define LPSRAM_BTCTRL_BLOCKACT_NOACT (0 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel disabled if last block transfer */
# define LPSRAM_BTCTRL_BLOCKACT_INT (1 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel disabled if last block transfer + block int */
# define LPSRAM_BTCTRL_BLOCKACT_SUSPEND (2 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel suspend operation is completed */
# define LPSRAM_BTCTRL_BLOCKACT_BOTH (3 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Both channel suspend operation + block int */
#define LPSRAM_BTCTRL_BEATSIZE_SHIFT (8) /* Bits 8-9: Beat size */
#define LPSRAM_BTCTRL_BEATSIZE_MASK (3 << LPSRAM_BTCTRL_BEATSIZE_SHIFT)
# define LPSRAM_BTCTRL_BEATSIZE_BYTE (0 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 8-bit bus transfer */
# define LPSRAM_BTCTRL_BEATSIZE_HWORD (1 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 16-bit bus transfer */
# define LPSRAM_BTCTRL_BEATSIZE_WORD (2 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 32-bit bus transfer */
#define LPSRAM_BTCTRL_SRCINC (1 << 10) /* Bit 10: Source address increment enable */
#define LPSRAM_BTCTRL_DSTINC (1 << 11) /* Bit 11: Destination address increment enable */
#define LPSRAM_BTCTRL_STEPSEL (1 << 12) /* Bit 12: Step selection */
#define LPSRAM_BTCTRL_STEPSIZE_SHIFT (13) /* Bits 13-15: Address increment step */
#define LPSRAM_BTCTRL_STEPSIZE_MASK (7 << LPSRAM_BTCTRL_STEPSIZE_SHIFT)
# define LPSRAM_BTCTRL_STEPSIZE_X1 (0 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 1 */
# define LPSRAM_BTCTRL_STEPSIZE_X2 (1 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 2 */
# define LPSRAM_BTCTRL_STEPSIZE_X4 (2 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 4 */
# define LPSRAM_BTCTRL_STEPSIZE_X8 (3 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 8 */
# define LPSRAM_BTCTRL_STEPSIZE_X16 (4 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 16 */
# define LPSRAM_BTCTRL_STEPSIZE_X32 (5 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 32 */
# define LPSRAM_BTCTRL_STEPSIZE_X64 (6 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 64 */
# define LPSRAM_BTCTRL_STEPSIZE_X128 (7 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 128 */
/* Block Transfer Count Register (16-bit count) */
/* Block Transfer Source Address Register (32-bit address) */
/* Block Transfer Destination Address Register (32-bit address) */
/* Next Address Descriptor Register (32-bit address) */
/****************************************************************************
* Public Types
****************************************************************************/
/* DMA descriptor */
struct dma_desc_s
{
uint16_t btctrl; /* Block Transfer Control Register */
uint16_t btcnt; /* Block Transfer Count Register */
uint32_t srcaddr; /* Block Transfer Source Address Register */
uint32_t dstaddr; /* Block Transfer Destination Address Register */
uint32_t descaddr; /* Next Address Descriptor Register */
};
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAML21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_DMAC_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/saml_eic.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_EIC_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_EIC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_ARCH_FAMILY_SAML21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* EIC register offsets *****************************************************/
#define SAM_EIC_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_EIC_NVMICTRL_OFFSET 0x0001 /* Non-maskable interrupt control register */
#define SAM_EIC_NMIFLAG_OFFSET 0x0002 /* Non-maskable interrupt flasg status and clear register */
#define SAM_EIC_SYNCBUSY_OFFSET 0x0004 /* Synchronization busy register */
#define SAM_EIC_EVCTRL_OFFSET 0x0008 /* Event control register */
#define SAM_EIC_INTENCLR_OFFSET 0x000c /* Interrupt enable clear register */
#define SAM_EIC_INTENSET_OFFSET 0x0010 /* Interrupt enable set register */
#define SAM_EIC_INTFLAG_OFFSET 0x0014 /* Interrupt flag and status clear register */
#define SAM_EIC_ASYNCH_OFFSET 0x0018 /* External interrupt asynchronous mode register */
#define SAM_EIC_CONFIG0_OFFSET 0x001c /* Configuration 0 register */
#define SAM_EIC_CONFIG1_OFFSET 0x0020 /* Configuration 1 register */
#define SAM_EIC_CONFIG2_OFFSET 0x0024 /* Configuration 2 register */
#define SAM_EIC_CONFIG3_OFFSET 0x0028 /* Configuration 3 register */
/* EIC register addresses ***************************************************/
#define SAM_EIC_CTRLA (SAM_EIC_BASE+SAM_EIC_CTRLA_OFFSET)
#define SAM_EIC_NVMICTRL (SAM_EIC_BASE+SAM_EIC_NVMICTRL_OFFSET)
#define SAM_EIC_NMIFLAG (SAM_EIC_BASE+SAM_EIC_NMIFLAG_OFFSET)
#define SAM_EIC_SYNCBUSY (SAM_EIC_BASE+SAM_EIC_SYNCBUSY_OFFSET)
#define SAM_EIC_EVCTRL (SAM_EIC_BASE+SAM_EIC_EVCTRL_OFFSET)
#define SAM_EIC_INTENCLR (SAM_EIC_BASE+SAM_EIC_INTENCLR_OFFSET)
#define SAM_EIC_INTENSET (SAM_EIC_BASE+SAM_EIC_INTENSET_OFFSET)
#define SAM_EIC_INTFLAG (SAM_EIC_BASE+SAM_EIC_INTFLAG_OFFSET)
#define SAM_EIC_ASYNCH (SAM_EIC_BASE+SAM_EIC_ASYNCH_OFFSET)
#define SAM_EIC_CONFIG0 (SAM_EIC_BASE+SAM_EIC_CONFIG0_OFFSET)
#define SAM_EIC_CONFIG1 (SAM_EIC_BASE+SAM_EIC_CONFIG1_OFFSET)
#define SAM_EIC_CONFIG2 (SAM_EIC_BASE+SAM_EIC_CONFIG2_OFFSET)
#define SAM_EIC_CONFIG3 (SAM_EIC_BASE+SAM_EIC_CONFIG3_OFFSET)
/* EIC register bit definitions *********************************************/
/* Control A register */
#define EIC_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
#define EIC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
#define EIC_CTRLA_CKSEL (1 << 2) /* Bit 2: Clock selection */
# define EIC_CTRLA_CKSEL_GCLK_EIC (0) /* 0=EIC clocked by GCLK_EIC */
# define EIC_CTRLA_CKSEL_CLK_ULP32K EIC_CTRLA_CKSEL /* 1=EIC clocked by CLK_ULP32K */
/* Non-maskable interrupt control register */
#define EIC_NVMICTRL_NMISENSE_SHIFT (0) /* Bits 0-2: Non-maskable interrupt sense */
#define EIC_NVMICTRL_NMISENSE_MASK (7 << EIC_NVMICTRL_NMISENSE_SHIFT)
# define EIC_NVMICTRL_NMISENSE_NONE (0 << EIC_NVMICTRL_NMISENSE_SHIFT) /* No detection */
# define EIC_NVMICTRL_NMISENSE_RISE (1 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Rising edge detection */
# define EIC_NVMICTRL_NMISENSE_FALL (2 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Falling edge detection */
# define EIC_NVMICTRL_NMISENSE_BOTH (3 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Both edge detection */
# define EIC_NVMICTRL_NMISENSE_HIGH (4 << EIC_NVMICTRL_NMISENSE_SHIFT) /* High level detection */
# define EIC_NVMICTRL_NMISENSE_LOW (5 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Low level detection */
#define EIC_NVMICTRL_NMIFLTEN (1 << 3) /* Bit 3: Non-maskable interrupt filter enable */
#define EIC_NVMICTRL_ASYNC (1 << 4) /* Bit 4: Asynchronous edge detection mode */
/* Non-maskable interrupt flas status and clear register */
#define EIC_NMIFLAG_NMI (1 << 0) /* Non-maskable interrupt */
/* Synchronization busy register */
#define EIC_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset syncrhonization busy */
#define EIC_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: Enable syncrhonization busy */
/* Event control, Interrupt enable clear, interrupt enable set register,
* interrupt flag status and clear, and External interrupt asynchronous
* mode registers.
*/
#define EIC_EXTINT_SHIFT (0) /* Bits 0-15: External interrupt n */
#define EIC_EXTINT_MASK (0xffff << EIC_EXTINT_SHIFT)
# define EIC_EXTINT(n) (1 << (n))
# define EIC_EXTINT_0 (1 << 0) /* Bit 0: External interrupt 0 */
# define EIC_EXTINT_1 (1 << 1) /* Bit 1: External interrupt 1 */
# define EIC_EXTINT_2 (1 << 2) /* Bit 2: External interrupt 2 */
# define EIC_EXTINT_3 (1 << 3) /* Bit 3: External interrupt 3 */
# define EIC_EXTINT_4 (1 << 4) /* Bit 4: External interrupt 4 */
# define EIC_EXTINT_5 (1 << 5) /* Bit 5: External interrupt 5 */
# define EIC_EXTINT_6 (1 << 6) /* Bit 6: External interrupt 6 */
# define EIC_EXTINT_7 (1 << 7) /* Bit 7: External interrupt 7 */
# define EIC_EXTINT_8 (1 << 8) /* Bit 8: External interrupt 8 */
# define EIC_EXTINT_9 (1 << 9) /* Bit 9: External interrupt 9 */
# define EIC_EXTINT_10 (1 << 10) /* Bit 10: External interrupt 10 */
# define EIC_EXTINT_11 (1 << 11) /* Bit 11: External interrupt 11 */
# define EIC_EXTINT_12 (1 << 12) /* Bit 12: External interrupt 12 */
# define EIC_EXTINT_13 (1 << 13) /* Bit 13: External interrupt 13 */
# define EIC_EXTINT_14 (1 << 14) /* Bit 14: External interrupt 14 */
# define EIC_EXTINT_15 (1 << 15) /* Bit 15: External interrupt 15 */
#define EIC_EXTINT_ALL EIC_EXTINT_MASK
/* Configuration 0 register */
#define EIC_CONFIG0_FILTEN(n) (3 + ((n) << 2)) /* Filter n enable, n=0-7 */
#define EIC_CONFIG0_SENSE_SHIFT(n) ((n) << 2) /* Filter n input sense, n=0-7 */
#define EIC_CONFIG0_SENSE_MASK(n) (7 << EIC_CONFIG0_SENSE_SHIFT(n))
# define EIC_CONFIG0_SENSE_NONE (0 << EIC_CONFIG0_SENSE_SHIFT(n)) /* No detection */
# define EIC_CONFIG0_SENSE_RISE (1 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Rising edge detection */
# define EIC_CONFIG0_SENSE_FALL (2 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Falling edge detection */
# define EIC_CONFIG0_SENSE_BOTH (3 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Both edge detection */
# define EIC_CONFIG0_SENSE_HIGH (4 << EIC_CONFIG0_SENSE_SHIFT(n)) /* High level detection */
# define EIC_CONFIG0_SENSE_LOW (5 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Low level detection */
/* Configuration 1 register */
#define EIC_CONFIG1_FILTEN(n) (3 + (((n) - 8) << 2)) /* Filter n enable, n=8-15 */
#define EIC_CONFIG1_SENSE_SHIFT(n) (((n) - 8) << 2) /* Filter n input sense, n=8-17 */
#define EIC_CONFIG1_SENSE_MASK(n) (7 << EIC_CONFIG1_SENSE_SHIFT(n))
# define EIC_CONFIG1_SENSE_NONE (0 << EIC_CONFIG1_SENSE_SHIFT(n)) /* No detection */
# define EIC_CONFIG1_SENSE_RISE (1 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Rising edge detection */
# define EIC_CONFIG1_SENSE_FALL (2 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Falling edge detection */
# define EIC_CONFIG1_SENSE_BOTH (3 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Both edge detection */
# define EIC_CONFIG1_SENSE_HIGH (4 << EIC_CONFIG1_SENSE_SHIFT(n)) /* High level detection */
# define EIC_CONFIG1_SENSE_LOW (5 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Low level detection */
/* Configuration 2 register */
#define EIC_CONFIG2_FILTEN(n) (3 + (((n) - 16) << 2)) /* Filter n enable, n=16-23 */
#define EIC_CONFIG2_SENSE_SHIFT(n) (((n) - 16) << 2) /* Filter n input sense, n=16-23 */
#define EIC_CONFIG2_SENSE_MASK(n) (7 << EIC_CONFIG2_SENSE_SHIFT(n))
# define EIC_CONFIG2_SENSE_NONE (0 << EIC_CONFIG2_SENSE_SHIFT(n)) /* No detection */
# define EIC_CONFIG2_SENSE_RISE (1 << EIC_CONFIG2_SENSE_SHIFT(n)) /* Rising edge detection */
# define EIC_CONFIG2_SENSE_FALL (2 << EIC_CONFIG2_SENSE_SHIFT(n)) /* Falling edge detection */
# define EIC_CONFIG2_SENSE_BOTH (3 << EIC_CONFIG2_SENSE_SHIFT(n)) /* Both edge detection */
# define EIC_CONFIG2_SENSE_HIGH (4 << EIC_CONFIG2_SENSE_SHIFT(n)) /* High level detection */
# define EIC_CONFIG2_SENSE_LOW (5 << EIC_CONFIG2_SENSE_SHIFT(n)) /* Low level detection */
/* Configuration 3 register */
#define EIC_CONFIG3_FILTEN(n) (3 + (((n) - 24) << 2)) /* Filter n enable, n=24-31 */
#define EIC_CONFIG3_SENSE_SHIFT(n) (((n) - 24) << 2) /* Filter n input sense, n=24-31 */
#define EIC_CONFIG3_SENSE_MASK(n) (7 << EIC_CONFIG3_SENSE_SHIFT(n))
# define EIC_CONFIG3_SENSE_NONE (0 << EIC_CONFIG3_SENSE_SHIFT(n)) /* No detection */
# define EIC_CONFIG3_SENSE_RISE (1 << EIC_CONFIG3_SENSE_SHIFT(n)) /* Rising edge detection */
# define EIC_CONFIG3_SENSE_FALL (2 << EIC_CONFIG3_SENSE_SHIFT(n)) /* Falling edge detection */
# define EIC_CONFIG3_SENSE_BOTH (3 << EIC_CONFIG3_SENSE_SHIFT(n)) /* Both edge detection */
# define EIC_CONFIG3_SENSE_HIGH (4 << EIC_CONFIG3_SENSE_SHIFT(n)) /* High level detection */
# define EIC_CONFIG3_SENSE_LOW (5 << EIC_CONFIG3_SENSE_SHIFT(n)) /* Low level detection */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAML21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_EIC_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/saml_evsys.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_EVSYS_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_EVSYS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_ARCH_FAMILY_SAML21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* EVSYS register offsets ***************************************************/
#define SAM_EVSYS_CTRLA_OFFSET 0x0000 /* Control register */
#define SAM_EVSYS_CHSTATUS_OFFSET 0x000c /* Channel status register */
#define SAM_EVSYS_INTENCLR_OFFSET 0x0010 /* Interrupt enable clear register */
#define SAM_EVSYS_INTENSET_OFFSET 0x0014 /* Interrupt enable set register */
#define SAM_EVSYS_INTFLAG_OFFSET 0x0018 /* Interrupt flag status and clear register */
#define SAM_EVSYS_SWEVT_OFFSET 0x001c /* Event user */
#define SAM_EVSYS_CHANNEL_OFFSET(n) (0x0020 + ((n) << 2)) /* Channel registers */
#define SAM_EVSYS_USER_OFFSET(n) (0x0080 + ((m) << 2)) /* User registers */
/* EVSYS register addresses *************************************************/
#define SAM_EVSYS_CTRLA (SAM_EVSYS_BASE+SAM_EVSYS_CTRLA_OFFSET)
#define SAM_EVSYS_CHSTATUS (SAM_EVSYS_BASE+SAM_EVSYS_CHSTATUS_OFFSET
#define SAM_EVSYS_INTENCLR (SAM_EVSYS_BASE+SAM_EVSYS_INTENCLR_OFFSET
#define SAM_EVSYS_INTENSET (SAM_EVSYS_BASE+SAM_EVSYS_INTENSET_OFFSET
#define SAM_EVSYS_INTFLAG (SAM_EVSYS_BASE+SAM_EVSYS_INTFLAG_OFFSET)
#define SAM_EVSYS_SWEVT (SAM_EVSYS_BASE+SAM_EVSYS_SWEVT_OFFSET)
#define SAM_EVSYS_CHANNEL_BASE(n) (SAM_EVSYS_BASE+SAM_EVSYS_CHANNEL_OFFSET(n))
#define SAM_EVSYS_USER_BASE(n) (SAM_EVSYS_BASE+SAM_EVSYS_USER_OFFSET(n))
/* EVSYS register bit definitions *******************************************/
/* Control register */
#define EVSYS_CTRLA_SWRST (1 << 0) /* Bit 0: Software Reset */
/* Channel status register */
#define EVSYS_CHSTATUS_USRRDY_SHIFT (0) /* Bits 0-7: User Ready for Channel n, n=0-11 */
#define EVSYS_CHSTATUS_USRRDY_MASK (0xfff << EVSYS_CHSTATUS_USRRDY_SHIFT)
# define EVSYS_CHSTATUS_USRRDY(n) ((uint32_t)(n) << EVSYS_CHSTATUS_USRRDY_SHIFT)
#define EVSYS_CHSTATUS_CHBUSY_SHIFT (8) /* Bits 8-15: Channel Busy n, n=0-11 */
#define EVSYS_CHSTATUS_CHBUSY_MASK (0xfff << EVSYS_CHSTATUS_CHBUSY_SHIFT)
# define EVSYS_CHSTATUS_CHBUSY(n) ((uint32_t)(n) << EVSYS_CHSTATUS_CHBUSY_SHIFT)
/* Interrupt enable clear, interrupt enable set,
* and interrupt flag status and clear registers
*/
#define EVSYS_INT_OVR_SHIFT (0) /* Bits 0-7: Overrun channel n interrupt, n= 0-11 */
#define EVSYS_INT_OVR_MASK (0xfff << EVSYS_INT_OVR_SHIFT)
# define EVSYS_INT_OVR(n) (1 << (n))
#define EVSYS_INT_EVD_SHIFT (8) /* Bits 8-15: Event detected channel n interrupt */
#define EVSYS_INT_EVD_MASK (0xff << EVSYS_INT_EVD_SHIFT)
# define EVSYS_INT_EVD(n) (1 << ((n)+8))
/* Event user register */
#define EVSYS_SWEVT_CHANNEL_SHIFT (0)) /* Bits 0-11: Channel n software selection, n=0-11 */
#define EVSYS_SWEVT_CHANNEL_MASK (0xfff << EVSYS_SWEVT_CHANNEL_SHIFT)
# define EVSYS_SWEVT_CHANNEL(n) (1 << (n))
/* Channel registers */
#define EVSYS_CHANNEL_EVGEN_SHIFT (0) /* Bits 0-6: Event generator */
#define EVSYS_CHANNEL_EVGEN_MASK (0x7f << EVSYS_CHANNEL_EVGEN_SHIFT)
# define EVSYS_CHANNEL_EVGEN_NONE (0x00 << EVSYS_CHANNEL_EVGEN_SHIFT) /* No event generator selected */
# define EVSYS_CHANNEL_EVGEN_RTC_CMP0 (0x01 << EVSYS_CHANNEL_EVGEN_SHIFT) /* Compare 0 or alarm 0 */
# define EVSYS_CHANNEL_EVGEN_RTC_CMP1 (0x02 << EVSYS_CHANNEL_EVGEN_SHIFT) /* Compare 1 */
# define EVSYS_CHANNEL_EVGEN_RTC_OVF (0x03 << EVSYS_CHANNEL_EVGEN_SHIFT) /* Overflow */
# define EVSYS_CHANNEL_EVGEN_RTC_PER0 (0x04 << EVSYS_CHANNEL_EVGEN_SHIFT) /* Period 0 */
# define EVSYS_CHANNEL_EVGEN_RTC_PER1 (0x05 << EVSYS_CHANNEL_EVGEN_SHIFT) /* Period 1 */
# define EVSYS_CHANNEL_EVGEN_RTC_PER2 (0x06 << EVSYS_CHANNEL_EVGEN_SHIFT) /* Period 2 */
# define EVSYS_CHANNEL_EVGEN_RTC_PER3 (0x07 << EVSYS_CHANNEL_EVGEN_SHIFT) /* Period 3 */
# define EVSYS_CHANNEL_EVGEN_RTC_PER4 (0x08 << EVSYS_CHANNEL_EVGEN_SHIFT) /* Period 4 */
# define EVSYS_CHANNEL_EVGEN_RTC_PER5 (0x09 << EVSYS_CHANNEL_EVGEN_SHIFT) /* Period 5 */
# define EVSYS_CHANNEL_EVGEN_RTC_PER6 (0x0a << EVSYS_CHANNEL_EVGEN_SHIFT) /* Period 6 */
# define EVSYS_CHANNEL_EVGEN_RTC_PER7 (0x0b << EVSYS_CHANNEL_EVGEN_SHIFT) /* Period 7 */
# define EVSYS_CHANNEL_EVGEN_EIC_EXTINT0 (0x0c << EVSYS_CHANNEL_EVGEN_SHIFT) /* External interrupt 0 */
# define EVSYS_CHANNEL_EVGEN_EIC_EXTINT1 (0x0d << EVSYS_CHANNEL_EVGEN_SHIFT) /* External interrupt 1 */
# define EVSYS_CHANNEL_EVGEN_EIC_EXTINT2 (0x0e << EVSYS_CHANNEL_EVGEN_SHIFT) /* External interrupt 2 */
# define EVSYS_CHANNEL_EVGEN_EIC_EXTINT3 (0x0f << EVSYS_CHANNEL_EVGEN_SHIFT) /* External interrupt 3 */
# define EVSYS_CHANNEL_EVGEN_EIC_EXTINT4 (0x10 << EVSYS_CHANNEL_EVGEN_SHIFT) /* External interrupt 4 */
# define EVSYS_CHANNEL_EVGEN_EIC_EXTINT5 (0x11 << EVSYS_CHANNEL_EVGEN_SHIFT) /* External interrupt 5 */
# define EVSYS_CHANNEL_EVGEN_EIC_EXTINT6 (0x12 << EVSYS_CHANNEL_EVGEN_SHIFT) /* External interrupt 6 */
# define EVSYS_CHANNEL_EVGEN_EIC_EXTINT7 (0x13 << EVSYS_CHANNEL_EVGEN_SHIFT) /* External interrupt 7 */
# define EVSYS_CHANNEL_EVGEN_EIC_EXTINT8 (0x14 << EVSYS_CHANNEL_EVGEN_SHIFT) /* External interrupt 8 */
# define EVSYS_CHANNEL_EVGEN_EIC_EXTINT9 (0x15 << EVSYS_CHANNEL_EVGEN_SHIFT) /* External interrupt 9 */
# define EVSYS_CHANNEL_EVGEN_EIC_EXTINT10 (0x16 << EVSYS_CHANNEL_EVGEN_SHIFT) /* External interrupt 10 */
# define EVSYS_CHANNEL_EVGEN_EIC_EXTINT11 (0x17 << EVSYS_CHANNEL_EVGEN_SHIFT) /* External interrupt 11 */
# define EVSYS_CHANNEL_EVGEN_EIC_EXTINT12 (0x18 << EVSYS_CHANNEL_EVGEN_SHIFT) /* External interrupt 12 */
# define EVSYS_CHANNEL_EVGEN_EIC_EXTINT13 (0x19 << EVSYS_CHANNEL_EVGEN_SHIFT) /* External interrupt 13 */
# define EVSYS_CHANNEL_EVGEN_EIC_EXTINT14 (0x1a << EVSYS_CHANNEL_EVGEN_SHIFT) /* External interrupt 14 */
# define EVSYS_CHANNEL_EVGEN_EIC_EXTINT15 (0x1b << EVSYS_CHANNEL_EVGEN_SHIFT) /* External interrupt 15 */
# define EVSYS_CHANNEL_EVGEN_DMAC_CH0 (0x1c << EVSYS_CHANNEL_EVGEN_SHIFT) /* DMA channel 0 */
# define EVSYS_CHANNEL_EVGEN_DMAC_CH1 (0x1d << EVSYS_CHANNEL_EVGEN_SHIFT) /* DMA channel 1 */
# define EVSYS_CHANNEL_EVGEN_DMAC_CH2 (0x1e << EVSYS_CHANNEL_EVGEN_SHIFT) /* DMA channel 2 */
# define EVSYS_CHANNEL_EVGEN_DMAC_CH3 (0x1f << EVSYS_CHANNEL_EVGEN_SHIFT) /* DMA channel 3 */
# define EVSYS_CHANNEL_EVGEN_DMAC_CH4 (0x20 << EVSYS_CHANNEL_EVGEN_SHIFT) /* DMA channel 4 */
# define EVSYS_CHANNEL_EVGEN_DMAC_CH5 (0x21 << EVSYS_CHANNEL_EVGEN_SHIFT) /* DMA channel 5 */
# define EVSYS_CHANNEL_EVGEN_DMAC_CH6 (0x22 << EVSYS_CHANNEL_EVGEN_SHIFT) /* DMA channel 6 */
# define EVSYS_CHANNEL_EVGEN_DMAC_CH7 (0x23 << EVSYS_CHANNEL_EVGEN_SHIFT) /* DMA channel 7 */
# define EVSYS_CHANNEL_EVGEN_TCCO_OVF (0x24 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC0 overflow */
# define EVSYS_CHANNEL_EVGEN_TCCO_TRG (0x25 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC0 trigger */
# define EVSYS_CHANNEL_EVGEN_TCCO_CNT (0x26 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC0 counter */
# define EVSYS_CHANNEL_EVGEN_TCCO_MCX0 (0x27 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC0 match/capture 0 */
# define EVSYS_CHANNEL_EVGEN_TCCO_MCX1 (0x28 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC0 match/capture 1 */
# define EVSYS_CHANNEL_EVGEN_TCCO_MCX2 (0x29 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC0 match/capture 2 */
# define EVSYS_CHANNEL_EVGEN_TCCO_MCX3 (0x2a << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC0 match/capture 2 */
# define EVSYS_CHANNEL_EVGEN_TCC1_OVF (0x2b << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC1 overflow */
# define EVSYS_CHANNEL_EVGEN_TCC1_TRG (0x2c << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC1 trigger */
# define EVSYS_CHANNEL_EVGEN_TCC1_CNT (0x2d << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC1 counter */
# define EVSYS_CHANNEL_EVGEN_TCC1_MCX0 (0x2e << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC01match/capture 0 */
# define EVSYS_CHANNEL_EVGEN_TCC1_MCX1 (0x2f << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC1 match/capture 1 */
# define EVSYS_CHANNEL_EVGEN_TCC2_OVF (0x30 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC2 overflow */
# define EVSYS_CHANNEL_EVGEN_TCC2_TRG (0x31 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC2 trigger */
# define EVSYS_CHANNEL_EVGEN_TCC2_CNT (0x32 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC2 counter */
# define EVSYS_CHANNEL_EVGEN_TCC2_MCX0 (0x33 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC2 match/capture 0 */
# define EVSYS_CHANNEL_EVGEN_TCC2_MCX1 (0x34 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCC2 match/capture 1 */
# define EVSYS_CHANNEL_EVGEN_TC0_OVF (0x35 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TCO Overflow */
# define EVSYS_CHANNEL_EVGEN_TC0_MC0 (0x36 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC0 match/capture 0 */
# define EVSYS_CHANNEL_EVGEN_TC0_MC1 (0x37 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC0 match/capture 1 */
# define EVSYS_CHANNEL_EVGEN_TC1_OVF (0x38 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC1 Overflow */
# define EVSYS_CHANNEL_EVGEN_TC1_MC0 (0x39 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC1 match/capture 0 */
# define EVSYS_CHANNEL_EVGEN_TC1_MC1 (0x3a << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC1 match/capture 1 */
# define EVSYS_CHANNEL_EVGEN_TC2_OVF (0x3b << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC2 Overflow */
# define EVSYS_CHANNEL_EVGEN_TC2_MC0 (0x3c << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC2 match/captue 0 */
# define EVSYS_CHANNEL_EVGEN_TC2_MC1 (0x3d << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC2 match/capture 1 */
# define EVSYS_CHANNEL_EVGEN_TC3_OVF (0x3e << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC3 Overflow */
# define EVSYS_CHANNEL_EVGEN_TC3_MC0 (0x3f << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC3 match/capture 0 */
# define EVSYS_CHANNEL_EVGEN_TC3_MC1 (0x40 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC3 match/capture 1 */
# define EVSYS_CHANNEL_EVGEN_TC4_OVF (0x41 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC4 Overflow */
# define EVSYS_CHANNEL_EVGEN_TC4_MC0 (0x42 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC4 match/capture 0 */
# define EVSYS_CHANNEL_EVGEN_TC4_MC1 (0x43 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC4 match/capture 1 */
# define EVSYS_CHANNEL_EVGEN_ADC_RESRDY (0x44 << EVSYS_CHANNEL_EVGEN_SHIFT) /* ADC result ready */
# define EVSYS_CHANNEL_EVGEN_ADC_WINMON (0x45 << EVSYS_CHANNEL_EVGEN_SHIFT) /* ADC window monitor */
# define EVSYS_CHANNEL_EVGEN_AC_COMP0 (0x46 << EVSYS_CHANNEL_EVGEN_SHIFT) /* Analog comparator 0 */
# define EVSYS_CHANNEL_EVGEN_AC_COMP1 (0x47 << EVSYS_CHANNEL_EVGEN_SHIFT) /* Analog comparator 1 */
# define EVSYS_CHANNEL_EVGEN_AC_WIN0 (0x48 << EVSYS_CHANNEL_EVGEN_SHIFT) /* Analog window comparator */
# define EVSYS_CHANNEL_EVGEN_DAC_EMPTY0 (0x49 << EVSYS_CHANNEL_EVGEN_SHIFT) /* DAC data buffer 0 empty */
# define EVSYS_CHANNEL_EVGEN_DAC_EMPTY1 (0x4a << EVSYS_CHANNEL_EVGEN_SHIFT) /* DAC data buffer 1 empty */
# define EVSYS_CHANNEL_EVGEN_PTC_EOC (0x4b << EVSYS_CHANNEL_EVGEN_SHIFT) /* PTC end of conversion */
# define EVSYS_CHANNEL_EVGEN_PTC_WCOMPT (0x4c << EVSYS_CHANNEL_EVGEN_SHIFT) /* PTC window comparator */
# define EVSYS_CHANNEL_EVGEN_TRNG_READY (0x4d << EVSYS_CHANNEL_EVGEN_SHIFT) /* TRNG data ready */
# define EVSYS_CHANNEL_EVGEN_CCL_LUTOUT0 (0x4e << EVSYS_CHANNEL_EVGEN_SHIFT) /* CCL output 0 */
# define EVSYS_CHANNEL_EVGEN_CCL_LUTOUT1 (0x4f << EVSYS_CHANNEL_EVGEN_SHIFT) /* CCL output 1 */
# define EVSYS_CHANNEL_EVGEN_CCL_LUTOUT2 (0x50 << EVSYS_CHANNEL_EVGEN_SHIFT) /* CCL output 2 */
# define EVSYS_CHANNEL_EVGEN_CCL_LUTOUT3 (0x51 << EVSYS_CHANNEL_EVGEN_SHIFT) /* CCL output 3 */
# define EVSYS_CHANNEL_EVGEN_PAC_ACCERR (0x52 << EVSYS_CHANNEL_EVGEN_SHIFT) /* PAC access error */
#define EVSYS_CHANNEL_PATH_SHIFT (8) /* Bits 8-9: Path selection */
#define EVSYS_CHANNEL_PATH_MASK (3 << EVSYS_CHANNEL_PATH_SHIFT)
# define EVSYS_CHANNEL_PATH_SYNCH (0 << EVSYS_CHANNEL_PATH_SHIFT) /* Synchronized path */
# define EVSYS_CHANNEL_PATH_RESYNCH (1 << EVSYS_CHANNEL_PATH_SHIFT) /* Resynchronized path */
# define EVSYS_CHANNEL_PATH_ASYNCH (2 << EVSYS_CHANNEL_PATH_SHIFT) /* Asynchronous path */
#define EVSYS_CHANNEL_EDGESEL_SHIFT (10) /* Bits 10-11: Edge dection selection */
#define EVSYS_CHANNEL_EDGESEL_MASK (3 << EVSYS_CHANNEL_EDGESEL_SHIFT)
# define EVSYS_CHANNEL_EDGESEL_NONE (0 << EVSYS_CHANNEL_EDGESEL_SHIFT) /* No event output */
# define EVSYS_CHANNEL_EDGESEL_RISING (1 << EVSYS_CHANNEL_EDGESEL_SHIFT) /* Detect on rising edge */
# define EVSYS_CHANNEL_EDGESEL_FALLING (2 << EVSYS_CHANNEL_EDGESEL_SHIFT) /* Detect on falling edge */
# define EVSYS_CHANNEL_EDGESEL_BOTH (3 << EVSYS_CHANNEL_EDGESEL_SHIFT) /* Detect on both edges */
#define EVSYS_CHANNEL_RUNSTDBY (1 << 14) /* Bit 14: Run in standby */
#define EVSYS_CHANNEL_ONDEMAND (1 << 15) /* Bit 15: Generic clock on-demand */
/* User registers */
#define EVSYS_USER_CHANNEL_SHIFT (0) /* Bits 0-5: Channel number */
#define EVSYS_USER_CHANNEL_MASK (63 << EVSYS_USER_CHANNEL_SHIFT)
# define EVSYS_USER_CHANNEL_NONE (0 << EVSYS_USER_CHANNEL_SHIFT) /* No channel output selected */
# define EVSYS_USER_CHANNEL(n) ((uint32_t)((n)+1) << EVSYS_USER_CHANNEL_SHIFT) /* Channel n */
/* User multiplexer numbers ************************************************/
#define EVSYS_USER_PORT_EV0 0 /* Event 0 */
#define EVSYS_USER_PORT_EV1 1 /* Event 1 */
#define EVSYS_USER_PORT_EV2 2 /* Event 2 */
#define EVSYS_USER_PORT_EV3 3 /* Event 3 */
#define EVSYS_USER_DMAC_CH0 4 /* DMAC Channel 0 */
#define EVSYS_USER_DMAC_CH1 5 /* DMAC Channel 1 */
#define EVSYS_USER_DMAC_CH2 6 /* DMAC Channel 2 */
#define EVSYS_USER_DMAC_CH3 7 /* DMAC Channel 3 */
#define EVSYS_USER_DMAC_CH4 8 /* DMAC Channel 4 */
#define EVSYS_USER_DMAC_CH5 9 /* DMAC Channel 5 */
#define EVSYS_USER_DMAC_CH6 10 /* DMAC Channel 6 */
#define EVSYS_USER_DMAC_CH7 11 /* DMAC Channel 7 */
#define EVSYS_USER_TCC0_EV0 12 /* TCC0 Event 0 */
#define EVSYS_USER_TCC0_EV1 13 /* TCC0 Event 1 */
#define EVSYS_USER_TCC0_MC0 14 /* TCC0 Match/Capture 0 */
#define EVSYS_USER_TCC0_MC1 15 /* TCC0 Match/Capture 1 */
#define EVSYS_USER_TCC0_MC2 16 /* TCC0 Match/Capture 2 */
#define EVSYS_USER_TCC0_MC3 17 /* TCC0 Match/Capture 3 */
#define EVSYS_USER_TCC1_EV0 18 /* TCC1 Event 0 */
#define EVSYS_USER_TCC1_EV1 19 /* TCC1 Event 1 */
#define EVSYS_USER_TCC1_MC0 20 /* TCC1 Match/Capture 0 */
#define EVSYS_USER_TCC1_MC1 21 /* TCC1 Match/Capture 1 */
#define EVSYS_USER_TCC2_EV0 22 /* TCC2 Event 0 */
#define EVSYS_USER_TCC2_EV1 23 /* TCC2 Event 1 */
#define EVSYS_USER_TCC2_MC0 24 /* TCC2 Match/Capture 0 */
#define EVSYS_USER_TCC2_MC1 25 /* TCC2 Match/Capture 1 */
#define EVSYS_USER_TC0 26 /* TC0 */
#define EVSYS_USER_TC1 27 /* TC1 */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAML21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_EVSYS_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/saml_fuses.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_FUSES_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_FUSES_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_ARCH_FAMILY_SAML21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* NVM Fuse addresses *******************************************************/
/* NVM user row bits */
#define SAM_NVMUSER_ROW0 (SAM_NVMUSER_ROW + 0x0000) /* Bits 0-31 */
#define SAM_NVMUSER_ROW1 (SAM_NVMUSER_ROW + 0x0004) /* Bits 32-63 */
/* NVM Software Calibration Area */
#define SAM_NVMCALIB_AREA0 (SAM_NVMCALIB_AREA + 0x0000) /* Bits 0-31 */
#define SAM_NVMCALIB_AREA1 (SAM_NVMCALIB_AREA + 0x0000) /* Bits 32-63 */
#define SAM_NVMCALIB_AREA2 (SAM_NVMCALIB_AREA + 0x0000) /* Bits 64-95 */
#define SAM_NVMCALIB_AREA3 (SAM_NVMCALIB_AREA + 0x0000) /* Bits 96-127 */
/* Fuse bit-field definitions ***********************************************/
/* NVM user row bits 0-31 */
#define SAM_FUSES_BOOTPROT_ADDR SAM_NVMUSER_ROW0
#define SAM_FUSES_BOOTPROT_SHIFT (0) /* Bits 0-2: Bootloader Size */
#define SAM_FUSES_BOOTPROT_MASK (7 << SAM_FUSES_BOOTPROT_SHIFT)
# define SAM_FUSES_BOOTPROT(n) ((uint32_t)(n) << SAM_FUSES_BOOTPROT_SHIFT)
#define SAM_FUSES_EEPROM_SIZE_ADDR SAM_NVMUSER_ROW0
#define SAM_FUSES_EEPROM_SIZE_SHIFT (4) /* Bits 4-6: EEPROM Size */
#define SAM_FUSES_EEPROM_SIZE_MASK (7 << SAM_FUSES_EEPROM_SIZE_SHIFT)
# define SAM_FUSES_EEPROM_SIZE(n) ((uint32_t)(n) << SAM_FUSES_EEPROM_SIZE_SHIFT)
#define SAM_FUSES_BOD33LEVEL_ADDR SAM_NVMUSER_ROW0
#define SAM_FUSES_BOD33LEVEL_SHIFT (8) /* Bits 8-13: BOD33 Level */
#define SAM_FUSES_BOD33LEVEL_MASK (0x3f << SAM_FUSES_BOD33LEVEL_SHIFT)
# define SAM_FUSES_BOD33LEVEL(n) (((uint32_t)n) << SAM_FUSES_BOD33LEVEL_SHIFT)
#define SAM_FUSES_BOD33_DIS_ADDR SAM_NVMUSER_ROW0
#define SAM_FUSES_BOD33_DIS_SHIFT (14) /* Bit 14: BOD33 Disable */
#define SAM_FUSES_BOD33_DIS_MASK (1 << SAM_FUSES_BOD33_DIS_SHIFT)
#define SAM_FUSES_BOD33_ACTION_ADDR SAM_NVMUSER_ROW0
#define SAM_FUSES_BOD33_ACTION_SHIFT (15) /* Bits 15-16: BOD33 Action */
#define SAM_FUSES_BOD33_ACTION_MASK (3 << SAM_FUSES_BOD33_ACTION_SHIFT)
# define SAM_FUSES_BOD33_ACTION(n) (((uint32_t)n) << SAM_FUSES_BOD33_ACTION_SHIFT)
#define SAM_FUSES_BOD12LEVEL_ADDR SAM_NVMUSER_ROW0
#define SAM_FUSES_BOD12LEVEL_SHIFT (17) /* Bits 17-22: BOD12 Level */
#define SAM_FUSES_BOD12LEVEL_MASK (0x1f << SAM_FUSES_BOD12LEVEL_SHIFT)
# define SAM_FUSES_BOD12LEVEL(n) ((uint32_t)(n) << SAM_FUSES_BOD12LEVEL_SHIFT)
#define SAM_FUSES_BOD12_DIS_ADDR SAM_NVMUSER_ROW0
#define SAM_FUSES_BOD12_DIS_SHIFT (23) /* Bit 23: BOD12 Disable */
#define SAM_FUSES_BOD12_DIS_MASK (1 << SAM_FUSES_BOD12_DIS_SHIFT)
#define SAM_FUSES_BOD12_ACTION_ADDR SAM_NVMUSER_ROW0
#define SAM_FUSES_BOD12_ACTION_SHIFT (24) /* Bits 24-25: BOD12 Action */
#define SAM_FUSES_BOD12_ACTION_MASK (3 << SAM_FUSES_BOD12_ACTION_SHIFT)
# define SAM_FUSES_BOD12_ACTION(n) ((uint32_t)(n) << SAM_FUSES_BOD12_ACTION_SHIFT)
#define SAM_FUSES_WDT_ENA_ADDR SAM_NVMUSER_ROW0
#define SAM_FUSES_WDT_ENA_SHIFT (26) /* Bit 26: WDT Enable */
#define SAM_FUSES_WDT_ENA_MASK (1 << SAM_FUSES_WDT_ENA_SHIFT)
#define SAM_FUSES_WDT_ALWAYSON_ADDR SAM_NVMUSER_ROW0
#define SAM_FUSES_WDT_ALWAYSON_SHIFT (27) /* Bit 27: WDT Always On */
#define SAM_FUSES_WDT_ALWAYSON_MASK (1 << SAM_FUSES_WDT_ALWAYSON_SHIFT)
#define SAM_FUSES_WDT_PER_ADDR SAM_NVMUSER_ROW0
#define SAM_FUSES_WDT_PER_SHIFT (28) /* Bits 28-31: WDT Period */
#define SAM_FUSES_WDT_PER_MASK (15 << SAM_FUSES_WDT_PER_SHIFT)
# define SAM_FUSES_WDT_PER(n) ((uint32_t)(n) << SAM_FUSES_WDT_PER_SHIFT)
/* NVM user row bits 32-64 */
#define SAM_FUSES_WDT_WINDOW_ADDR SAM_NVMUSER_ROW1
#define SAM_FUSES_WDT_WINDOW_SHIFT (0) /* Bits 32-35: WDT Window */
#define SAM_FUSES_WDT_WINDOW_MASK (15 << SAM_FUSES_WDT_WINDOW_SHIFT)
#define SAM_FUSES_WDT_EWOFFSET_ADDR SAM_NVMUSER_ROW1
#define SAM_FUSES_WDT_EWOFFSET_SHIFT (4) /* Bits 36-39: WDT Early Warning Offset */
#define SAM_FUSES_WDT_EWOFFSET_MASK (15 << SAM_FUSES_WDT_EWOFFSET_SHIFT)
# define SAM_FUSES_WDT_EWOFFSET(n) ((uint32_t)(n) << SAM_FUSES_WDT_EWOFFSET_SHIFT)
#define SAM_FUSES_WDT_WEN_ADDR SAM_NVMUSER_ROW1
#define SAM_FUSES_WDT_WEN_SHIFT (8) /* Bit 40: WDT Window Mode Enable */
#define SAM_FUSES_WDT_WEN_MASK (1 << SAM_FUSES_WDT_WEN_SHIFT)
#define SAM_FUSES_BOD33_HYST_ADDR SAM_NVMUSER_ROW1
#define SAM_FUSES_BOD33_HYST_SHIFT (9) /* Bit 41: BOD33 Hysteresis */
#define SAM_FUSES_BOD33_HYST_MASK (1 << SAM_FUSES_BOD33_HYST_SHIFT)
#define SAM_FUSES_BOD12_HYST_ADDR SAM_NVMUSER_ROW1
#define SAM_FUSES_BOD12_HYST_SHIFT (10) /* Bit 42: BOD12 Hysteresis */
#define SAM_FUSES_BOD12_HYST_MASK (1 << SAM_FUSES_BOD12_HYST_SHIFT)
#define SAM_FUSES_LOCK_ADDR SAM_NVMUSER_ROW1
#define SAM_FUSES_LOCK_SHIFT (16) /* Bits 48-63: NVM Region Lock bits */
#define SAM_FUSES_LOCK_MASK (0xffff << SAM_FUSES_LOCK_SHIFT)
# define SAM_FUSES_LOCK(n) ((uint32_t)(n) << SAM_FUSES_LOCK_SHIFT)
/* NVM Software Calibration Area bits 0-31 */
#define SAM_FUSES_ADC_LINEARITY_ADDR SAM_NVMCALIB_AREA0
#define SAM_FUSES_ADC_LINEARITY_SHIFT (0) /* Bits 0-2: ADC Linearity bits */
#define SAM_FUSES_ADC_LINEARITY_MASK (7 << SAM_FUSES_ADC_LINEARITY_SHIFT)
# define SAM_FUSES_ADC_LINEARITY(n) ((uint32_t)(n) << SAM_FUSES_ADC_LINEARITY_SHIFT)
#define SAM_FUSES_ADC_BIASCAL_ADDR SAM_NVMCALIB_AREA0
#define SAM_FUSES_ADC_BIASCAL_SHIFT (3) /* Bits 3-5: ADC Bias Calibration */
#define SAM_FUSES_ADC_BIASCAL_MASK (7 << SAM_FUSES_ADC_BIASCAL_SHIFT)
# define SAM_FUSES_ADC_BIASCAL(n) ((uint32_t)(n) << SAM_FUSES_ADC_BIASCAL_SHIFT)
#define SAM_FUSES_OSC32KCAL_ADDR SAM_NVMCALIB_AREA0
#define SAM_FUSES_OSC32KCAL_SHIFT (6) /* Bits 6-12: OSC32K Calibration */
#define SAM_FUSES_OSC32KCAL_MASK (0x7f << SAM_FUSES_OSC32KCAL_SHIFT)
# define SAM_FUSES_OSC32KCAL(n) ((uint32_t)(n) << SAM_FUSES_OSC32KCAL_SHIFT)
#define SAM_FUSES_USBTRANSN_ADDR SAM_NVMCALIB_AREA0
#define SAM_FUSES_USBTRANSN_SHIFT (13) /* Bits 13-17: USB TRNSN Calibration */
#define SAM_FUSES_USBTRANSN_MASK (31 << SAM_FUSES_USBTRANSN_SHIFT)
# define SAM_FUSES_USBTRANSN(n) ((uint32_t)(n) << SAM_FUSES_USBTRANSN_SHIFT)
#define SAM_FUSES_USBTRANSP_ADDR SAM_NVMCALIB_AREA0
#define SAM_FUSES_USBTRANSP_SHIFT (6) /* Bits 18-22: USB TRNSP Calibration */
#define SAM_FUSES_USBTRANSP_MASK (31 << SAM_FUSES_USBTRANSP_SHIFT)
# define SAM_FUSES_USBTRANSP(n) ((uint32_t)(n) << SAM_FUSES_USBTRANSP_SHIFT)
#define SAM_FUSES_USBTRIM_ADDR SAM_NVMCALIB_AREA0
#define SAM_FUSES_USBTRIM_SHIFT (23) /* Bits 23-25: USB TRIM Calibration */
#define SAM_FUSES_USBTRIM_MASK (7 << SAM_FUSES_USBTRIM_SHIFT)
# define SAM_FUSES_USBTRIM(n) ((uint32_t)(n) << SAM_FUSES_USBTRIM_SHIFT)
#define SAM_FUSES_DFLL48MCC_ADDR SAM_NVMCALIB_AREA0
#define SAM_FUSES_DFLL48MCC_SHIFT (26) /* Bits 26-31: DFLL48M Coarse Calibration */
#define SAM_FUSES_DFLL48MCC_MASK (0x3f << SAM_FUSES_DFLL48MCC_SHIFT)
# define SAM_FUSES_DFLL48MCC(n) ((uint32_t)(n) << SAM_FUSES_DFLL48MCC_SHIFT)
/* NVM Software Calibration Area bits 32-63 - Reserved */
/* NVM Software Calibration Area bits 64-95 - Reserved */
/* NVM Software Calibration Area bits 96-127 - Reserved */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAML21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_FUSES_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/saml_gclk.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_GCLK_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_GCLK_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_ARCH_FAMILY_SAML21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* GCLK register offsets ****************************************************/
#define SAM_GCLK_CTRLA_OFFSET 0x0000 /* Control register */
#define SAM_GCLK_SYNCHBUSY_OFFSET 0x0004 /* Status register */
#define SAM_GCLK_GENCTRL_OFFSET(n) (0x0020 + ((n) << 2)) /* General clock generator n */
#define SAM_GCLK_PCHCTRL_OFFSET(m) (0x0080 + ((m) << 2)) /* Peripheral channel control m */
/* GCLK register addresses **************************************************/
#define SAM_GCLK_CTRLA (SAM_GCLK_BASE+SAM_GCLK_CTRLA_OFFSET)
#define SAM_GCLK_SYNCHBUSY (SAM_GCLK_BASE+SAM_GCLK_SYNCHBUSY_OFFSET)
#define SAM_GCLK_GENCTRL(n) (SAM_GCLK_BASE+SAM_GCLK_GENCTRL_OFFSET(n))
#define SAM_GCLK_PCHCTRL(m) (SAM_GCLK_BASE+SAM_GCLK_PCHCTRL_OFFSET(m))
/* GCLK register bit definitions ********************************************/
/* Control register */
#define GCLK_CTRLA_SWRST (1 << 0) /* Bit 0: Software Reset */
/* Status register */
#define GCLK_SYNCHBUSY_SWRST (1 << 0) /* Bit 0: SWRST synchronization busy */
#define GCLK_SYNCHBUSY_GENCTRL(n) (1 << ((n) + 2)) /* Bit n+2: Generator control n busy */
# define GCLK_SYNCHBUSY_GENCTRL0 (1 << 2) /* Bit 2: Generator control 0 busy */
# define GCLK_SYNCHBUSY_GENCTRL1 (1 << 3) /* Bit 3: Generator control 1 busy */
# define GCLK_SYNCHBUSY_GENCTRL2 (1 << 4) /* Bit 4: Generator control 2 busy */
# define GCLK_SYNCHBUSY_GENCTRL3 (1 << 5) /* Bit 5: Generator control 3 busy */
# define GCLK_SYNCHBUSY_GENCTRL4 (1 << 6) /* Bit 6: Generator control 4 busy */
# define GCLK_SYNCHBUSY_GENCTRL5 (1 << 7) /* Bit 7: Generator control 5 busy */
# define GCLK_SYNCHBUSY_GENCTRL6 (1 << 8) /* Bit 8: Generator control 6 busy */
# define GCLK_SYNCHBUSY_GENCTRL7 (1 << 9) /* Bit 9: Generator control 7 busy */
# define GCLK_SYNCHBUSY_GENCTRL8 (1 << 10) /* Bit 10: Generator control 8 busy */
/* General clock generator n */
#define GCLK_GENCTRL_SRC_SHIFT (0) /* Bits 0-4: Generator source selection */
#define GCLK_GENCTRL_SRC_MASK (31 << GCLK_GENCTRL_SRC_SHIFT)
# define GCLK_GENCTRL_SRC_XOSC (0 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC oscillator inpupt */
# define GCLK_GENCTRL_SRC_GCLK_IN (1 << GCLK_GENCTRL_SRC_SHIFT) /* Generator input pad */
# define GCLK_GENCTRL_SRC_GLCK_GEN1 (2 << GCLK_GENCTRL_SRC_SHIFT) /* Generic clock generator 1 output */
# define GCLK_GENCTRL_SRC_OSCULP32K (3 << GCLK_GENCTRL_SRC_SHIFT) /* OSCULP32K oscillator output */
# define GCLK_GENCTRL_SRC_OSC32K (4 << GCLK_GENCTRL_SRC_SHIFT) /* OSC32K osccillator output */
# define GCLK_GENCTRL_SRC_XOSC32K (5 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC32K oscillator output */
# define GCLK_GENCTRL_SRC_OSC16M (6 << GCLK_GENCTRL_SRC_SHIFT) /* OSC16M oscillator output */
# define GCLK_GENCTRL_SRC_DFLL48M (7 << GCLK_GENCTRL_SRC_SHIFT) /* DFLL48M output */
# define GCLK_GENCTRL_SRC_DPLL96M (8 << GCLK_GENCTRL_SRC_SHIFT) /* DPLL96M output */
#define GCLK_GENCTRL_GENEN (1 << 8) /* Bit 8: Generator enable */
#define GCLK_GENCTRL_IDC (1 << 9) /* Bit 9: Improve duty cycle */
#define GCLK_GENCTRL_OOV (1 << 10) /* Bit 10: Clock output selection */
#define GCLK_GENCTRL_OE (1 << 11) /* Bit 11: Clock output enable */
#define GCLK_GENCTRL_DIVSEL (1 << 12) /* Bit 12: Clock source divider */
#define GCLK_GENCTRL_RUNSTDBY (1 << 13) /* Bit 13: Run in standby */
#define GCLK_GENCTRL_DIV_SHIFT (16) /* Bits 16-31: Generator 0,2-8 Division factor */
#define GCLK_GENCTRL_DIV_MASK (0xff << GCLK_GENCTRL_DIV_SHIFT)
# define GCLK_GENCTRL_DIV(n) ((uint32_t)(n) << GCLK_GENCTRL_DIV_SHIFT)
#define GCLK_GENCTRL1_DIV_SHIFT (16) /* Bits 16-23: Generator 1 Division factor **/
#define GCLK_GENCTRL1_DIV_MASK (0xffff << GCLK_GENCTRL1_DIV_SHIFT)
# define GCLK_GENCTRL1_DIV(n) ((uint32_t)(n) << GCLK_GENCTRL1_DIV_SHIFT)
/* Peripheral channel control m */
#define GCLK_PCHCTRL_GEN_SHIFT (0) /* Bits 0-3: Generator selection */
#define GCLK_PCHCTRL_GEN_MASK (15 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN(n) ((uint32_t)(n) << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN0 (0 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN1 (1 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN2 (2 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN3 (3 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN4 (4 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN5 (5 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN6 (6 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN7 (7 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN8 (8 << GCLK_PCHCTRL_GEN_SHIFT)
#define GCLK_PCHCTRL_CHEN (1 << 6) /* Bit 6: Channel enable */
#define GCLK_PCHCTRL_WRTLOCK (1 << 7) /* Bit 7: Write lock */
/* PCHCTRL channel mapping **************************************************/
#define GCLK_CHAN_DFLL48M_REF 0 /* DFLL48M Reference */
#define GCLK_CHAN_DPLL 1 /* FDPLL96M input clock source for reference */
#define GCLK_CHAN_DPLL_32K 2 /* FDPLL96M 32kHz clock for FDPLL96M internal lock timer */
#define GCLK_CHAN_EIC 3 /* EIC */
#define GCLK_CHAN_USB 4 /* USB */
#define GCLK_CHAN_EVSYS_CH0 5 /* EVSYS_CHANNEL_0 */
#define GCLK_CHAN_EVSYS_CH1 6 /* EVSYS_CHANNEL_1 */
#define GCLK_CHAN_EVSYS_CH2 7 /* EVSYS_CHANNEL_2 */
#define GCLK_CHAN_EVSYS_CH3 8 /* EVSYS_CHANNEL_3 */
#define GCLK_CHAN_EVSYS_CH4 9 /* EVSYS_CHANNEL_4 */
#define GCLK_CHAN_EVSYS_CH5 10 /* EVSYS_CHANNEL_5 */
#define GCLK_CHAN_EVSYS_CH6 11 /* EVSYS_CHANNEL_6 */
#define GCLK_CHAN_EVSYS_CH7 12 /* EVSYS_CHANNEL_7 */
#define GCLK_CHAN_EVSYS_CH8 13 /* EVSYS_CHANNEL_8 */
#define GCLK_CHAN_EVSYS_CH9 14 /* EVSYS_CHANNEL_9 */
#define GCLK_CHAN_EVSYS_CH10 15 /* EVSYS_CHANNEL_10 */
#define GCLK_CHAN_EVSYS_CH11 16 /* EVSYS_CHANNEL_11 */
#define GCLK_CHAN_SERCOM0_SLOW 17 /* SERCOM0_SLOW */
#define GCLK_CHAN_SERCOM1_SLOW 17 /* SERCOM1_SLOW */
#define GCLK_CHAN_SERCOM2_SLOW 17 /* SERCOM2_SLOW */
#define GCLK_CHAN_SERCOM3_SLOW 17 /* SERCOM3_SLOW */
#define GCLK_CHAN_SERCOM4_SLOW 17 /* SERCOM4_SLOW */
#define GCLK_CHAN_SERCOM0_CORE 18 /* SERCOM0_CORE */
#define GCLK_CHAN_SERCOM1_CORE 19 /* SERCOM1_CORE */
#define GCLK_CHAN_SERCOM2_CORE 20 /* SERCOM2_CORE */
#define GCLK_CHAN_SERCOM3_CORE 21 /* SERCOM3_CORE */
#define GCLK_CHAN_SERCOM4_CORE 22 /* SERCOM4_CORE */
#define GCLK_CHAN_SERCOM5_SLOW 23 /* SERCOM5_SLOW */
#define GCLK_CHAN_SERCOM5_CORE 24 /* SERCOM5_CORE */
#define GCLK_CHAN_TCC0 25 /* TCC0 */
#define GCLK_CHAN_TCC1 25 /* TCC1 */
#define GCLK_CHAN_TCC2 26 /* TCC2 */
#define GCLK_CHAN_TC3_1 26 /* TC3 */
#define GCLK_CHAN_TC0 27 /* TC0 */
#define GCLK_CHAN_TC1 27 /* TC1 */
#define GCLK_CHAN_TC2 28 /* TC2 */
#define GCLK_CHAN_TC3_2 28 /* TC3 */
#define GCLK_CHAN_TC4 29 /* TC4 */
#define GCLK_CHAN_ADC 30 /* ADC */
#define GCLK_CHAN_AC 31 /* AC */
#define GCLK_CHAN_DAC 32 /* DAC */
#define GCLK_CHAN_PTC 33 /* PTC */
#define GCLK_CHAN_CCL 34 /* CCL */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAML21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_GCLK_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/saml_i2c_master.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_I2C_MASTER_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_I2C_MASTER_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/saml_sercom.h"
#ifdef CONFIG_ARCH_FAMILY_SAML21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* I2C register offsets *****************************************************/
#define SAM_I2C_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_I2C_CTRLB_OFFSET 0x0004 /* Control B register */
#define SAM_I2C_BAUD_OFFSET 0x000c /* Baud register */
#define SAM_I2C_INTENCLR_OFFSET 0x0014 /* Interrupt enable clear register */
#define SAM_I2C_INTENSET_OFFSET 0x0016 /* Interrupt enable set register */
#define SAM_I2C_INTFLAG_OFFSET 0x0018 /* Interrupt flag and status clear register */
#define SAM_I2C_STATUS_OFFSET 0x001a /* Status register */
#define SAM_I2C_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */
#define SAM_I2C_ADDR_OFFSET 0x0024 /* Address register */
#define SAM_I2C_DATA_OFFSET 0x0028 /* Data register */
#define SAM_I2C_DBGCTRL_OFFSET 0x0030 /* Debug control register */
/* I2C register addresses ***************************************************/
#define SAM_I2C0_CTRLA (SAM_SERCOM0_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C0_CTRLB (SAM_SERCOM0_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C0_BAUD (SAM_SERCOM0_BASE+SAM_I2C_BAUD_OFFSET)
#define SAM_I2C0_INTENCLR (SAM_SERCOM0_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C0_INTENSET (SAM_SERCOM0_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C0_INTFLAG (SAM_SERCOM0_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C0_STATUS (SAM_SERCOM0_BASE+SAM_I2C_STATUS_OFFSET)
#define SAM_I2C0_SYNCBUSY (SAM_SERCOM0_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C0_ADDR (SAM_SERCOM0_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C0_DATA (SAM_SERCOM0_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C0_DBGCTRL (SAM_SERCOM0_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C1_CTRLA (SAM_SERCOM1_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C1_CTRLB (SAM_SERCOM1_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C1_BAUD (SAM_SERCOM1_BASE+SAM_I2C_BAUD_OFFSET)
#define SAM_I2C1_INTENCLR (SAM_SERCOM1_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C1_INTENSET (SAM_SERCOM1_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C1_INTFLAG (SAM_SERCOM1_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C1_STATUS (SAM_SERCOM1_BASE+SAM_I2C_STATUS_OFFSET)
#define SAM_I2C1_SYNCBUSY (SAM_SERCOM1_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C1_ADDR (SAM_SERCOM1_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C1_DATA (SAM_SERCOM1_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C1_DBGCTRL (SAM_SERCOM1_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C2_CTRLA (SAM_SERCOM2_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C2_CTRLB (SAM_SERCOM2_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C2_BAUD (SAM_SERCOM2_BASE+SAM_I2C_BAUD_OFFSET)
#define SAM_I2C2_INTENCLR (SAM_SERCOM2_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C2_INTENSET (SAM_SERCOM2_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C2_INTFLAG (SAM_SERCOM2_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C2_STATUS (SAM_SERCOM2_BASE+SAM_I2C_STATUS_OFFSET)
#define SAM_I2C2_SYNCBUSY (SAM_SERCOM2_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C2_ADDR (SAM_SERCOM2_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C2_DATA (SAM_SERCOM2_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C2_DBGCTRL (SAM_SERCOM2_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C3_CTRLA (SAM_SERCOM3_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C3_CTRLB (SAM_SERCOM3_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C3_BAUD (SAM_SERCOM3_BASE+SAM_I2C_BAUD_OFFSET)
#define SAM_I2C3_INTENCLR (SAM_SERCOM3_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C3_INTENSET (SAM_SERCOM3_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C3_INTFLAG (SAM_SERCOM3_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C3_STATUS (SAM_SERCOM3_BASE+SAM_I2C_STATUS_OFFSET)
#define SAM_I2C3_SYNCBUSY (SAM_SERCOM3_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C3_ADDR (SAM_SERCOM3_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C3_DATA (SAM_SERCOM3_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C3_DBGCTRL (SAM_SERCOM3_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C4_CTRLA (SAM_SERCOM4_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C4_CTRLB (SAM_SERCOM4_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C4_BAUD (SAM_SERCOM4_BASE+SAM_I2C_BAUD_OFFSET)
#define SAM_I2C4_INTENCLR (SAM_SERCOM4_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C4_INTENSET (SAM_SERCOM4_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C4_INTFLAG (SAM_SERCOM4_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C4_STATUS (SAM_SERCOM4_BASE+SAM_I2C_STATUS_OFFSET)
#define SAM_I2C4_SYNCBUSY (SAM_SERCOM4_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C4_ADDR (SAM_SERCOM4_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C4_DATA (SAM_SERCOM4_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C4_DBGCTRL (SAM_SERCOM4_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C5_CTRLA (SAM_SERCOM5_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C5_CTRLB (SAM_SERCOM5_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C5_BAUD (SAM_SERCOM5_BASE+SAM_I2C_BAUD_OFFSET)
#define SAM_I2C5_INTENCLR (SAM_SERCOM5_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C5_INTENSET (SAM_SERCOM5_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C5_INTFLAG (SAM_SERCOM5_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C5_STATUS (SAM_SERCOM5_BASE+SAM_I2C_STATUS_OFFSET)
#define SAM_I2C5_SYNCBUSY (SAM_SERCOM5_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C5_ADDR (SAM_SERCOM5_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C5_DATA (SAM_SERCOM5_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C5_DBGCTRL (SAM_SERCOM5_BASE+SAM_I2C_DBGCTRL_OFFSET)
/* I2C register bit definitions *********************************************/
/* Control A register */
#define I2C_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
#define I2C_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
#define I2C_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */
#define I2C_CTRLA_MODE_MASK (7 << I2C_CTRLA_MODE_SHIFT)
# define I2C_CTRLA_MODE_MASTER (5 << I2C_CTRLA_MODE_SHIFT) /* I2C master mode */
#define I2C_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */
#define I2C_CTRLA_PINOUT (1 << 16) /* Bit 16: Transmit data pinout */
# define I2C_CTRLA_1WIRE (0) /* 4-wire operation disable */
# define I2C_CTRLA_4WIRE I2C_CTRLA_PINOUT /* 4-wire operation enable */
#define I2C_CTRLA_SDAHOLD_SHIFT (20) /* Bits 20-21: SDA Hold Time */
#define I2C_CTRLA_SDAHOLD_MASK (3 << I2C_CTRLA_SDAHOLD_SHIFT)
# define I2C_CTRLA_SDAHOLD_DIS (0 << I2C_CTRLA_SDAHOLD_SHIFT) /* Disabled */
# define I2C_CTRLA_SDAHOLD_75NS (1 << I2C_CTRLA_SDAHOLD_SHIFT) /* 50-100ns hold time */
# define I2C_CTRLA_SDAHOLD_450NS (2 << I2C_CTRLA_SDAHOLD_SHIFT) /* 300-600ns hold time */
# define I2C_CTRLA_SDAHOLD_600NS (3 << I2C_CTRLA_SDAHOLD_SHIFT) /* 400-800ns hold time */
#define I2C_CTRLA_MEXTTOEN (1 << 22) /* Bit 22: Master SCL low extend time-out */
#define I2C_CTRLA_SEXTTOEN (1 << 23) /* Bit 23: Slave SCL low extend time-out */
#define I2C_CTRLA_SPEED_SHIFT (24) /* Bits 24-25: Transfer speed */
#define I2C_CTRLA_SPEED_MASK (3 << I2C_CTRLA_SPEED_SHIFT)
# define I2C_CTRLA_SPEED_STD (0 << I2C_CTRLA_SPEED_SHIFT) /* Standard (<=100KHz) and fast (<=400KHz) */
# define I2C_CTRLA_SPEED_FAST (1 << I2C_CTRLA_SPEED_SHIFT) /* Fast-mode plus (<=1MHz) */
# define I2C_CTRLA_SPEED_HIGH (2 << I2C_CTRLA_SPEED_SHIFT) /* High speed mode (<=3.4Mhz */
#define I2C_CTRLA_SCLAM (1 << 27) /* Bit 27: CSL clock stretch mode */
#define I2C_CTRLA_INACTOUT_SHIFT (28) /* Bits 28-29: Inactive Time-Out */
#define I2C_CTRLA_INACTOUT_MASK (7 << I2C_CTRLA_INACTOUT_SHIFT)
# define I2C_CTRLA_INACTOUT_DIS (0 << I2C_CTRLA_INACTOUT_SHIFT) /* Disabled */
# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60µs) */
# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110µs) */
# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210µs) */
#define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */
/* Control B register */
#define I2C_CTRLB_SMEN (1 << 8) /* Bit 8: Smart Mode Enable */
#define I2C_CTRLB_QCEN (1 << 9) /* Bit 9: Quick Command Enable */
#define I2C_CTRLB_CMD_SHIFT (16) /* Bits 16-17: Command */
#define I2C_CTRLB_CMD_MASK (3 << I2C_CTRLB_CMD_SHIFT)
# define I2C_CTRLB_CMD_NOACTION (0 << I2C_CTRLB_CMD_SHIFT) /* No action */
# define I2C_CTRLB_CMD_ACKREP (1 << I2C_CTRLB_CMD_SHIFT) /* ACK followed by repeated START */
# define I2C_CTRLB_CMD_ACKREAD (2 << I2C_CTRLB_CMD_SHIFT) /* ACK followed by read operation */
# define I2C_CTRLB_CMD_ACKSTOP (3 << I2C_CTRLB_CMD_SHIFT) /* ACK followed by STOP */
#define I2C_CTRLB_ACKACT (1 << 18) /* Bit 18: Acknowledge Action */
# define I2C_CTRLB_ACK (0) /* Send ACK */
# define I2C_CTRLB_NACK I2C_CTRLB_ACKACT /* Send NACK */
/* Baud register (16-bit baud value) */
#define I2C_BAUD_SHIFT (0) /* Bits 0-7: Master Baud Rate */
#define I2C_BAUD_MASK (0xff << I2C_BAUD_SHIFT)
# define I2C_BAUD(n) ((uint16)(n) << I2C_BAUD_SHIFT)
#define I2C_BAUDLOW_SHIFT (8) /* Bits 8-15: Master Baud Rate Low */
#define I2C_BAUDLOW_MASK (0xff << I2C_BAUDLOW_SHIFT)
# define I2C_BAUDLOW(n) (uint16)(n) << I2C_BAUDLOW_SHIFT)
#define I2C_HSBAUD_SHIFT (16) /* Bits 16-23: High speed master Baud Rate */
#define I2C_HSBAUD_MASK (0xff << I2C_HSBAUD_SHIFT)
# define I2C_HSBAUD(n) ((uint16)(n) << I2C_HSBAUD_SHIFT)
#define I2C_HSBAUDLOW_SHIFT (24) /* Bits 24-31: High speed master Baud Rate Low */
#define I2C_HSBAUDLOW_MASK (0xff << I2C_HSBAUDLOW_SHIFT)
# define I2C_HSBAUDLOW(n) (uint16)(n) << I2C_HSBAUDLOW_SHIFT)
/* Interrupt enable clear, interrupt enable set, interrupt enable set,
* interrupt flag and status clear registers.
*/
#define I2C_INT_MB (1 << 0) /* Bit 0: Master on bus interrupt */
#define I2C_INT_SB (1 << 1) /* Bit 1: Slave on bus interrupt */
#define I2C_INT_ERR (1 << 7) /* Bit 7: Bus Error */
#define I2C_INT_ALL (0x03)
/* Status register */
#define I2C_STATUS_BUSERR (1 << 0) /* Bit 0: Bus Error */
#define I2C_STATUS_ARBLOST (1 << 1) /* Bit 1: Arbitration Lost */
#define I2C_STATUS_RXNACK (1 << 2) /* Bit 2: Received Not Acknowledge */
#define I2C_STATUS_BUSSTATE_SHIFT (4) /* Bits 4-5: Bus State */
#define I2C_STATUS_BUSSTATE_MASK (3 << I2C_STATUS_BUSSTATE_SHIFT)
# define I2C_STATUS_BUSSTATE_UNKNOWN (0 << I2C_STATUS_BUSSTATE_SHIFT) /* Unknown to master */
# define I2C_STATUS_BUSSTATE_IDLE (1 << I2C_STATUS_BUSSTATE_SHIFT) /* Waiting for transaction */
# define I2C_STATUS_BUSSTATE_OWNER (2 << I2C_STATUS_BUSSTATE_SHIFT) /* Master of bus owner */
# define I2C_STATUS_BUSSTATE_BUSY (3 << I2C_STATUS_BUSSTATE_SHIFT) /* Other master owns */
#define I2C_STATUS_LOWTOUT (1 << 6) /* Bit 6: SCL Low Time-Out */
#define I2C_STATUS_CLKHOLD (1 << 7) /* Bit 7: Clock Hold */
#define I2C_STATUS_MEXTTOUT (1 << 8) /* Bit 8: Master SCL low extend time-out */
#define I2C_STATUS_SEXTTOUT (1 << 9) /* Bit 9: Slave SCL low extend time-out */
#define I2C_STATUS_LENERR (1 << 10) /* Bit 10: Transaction length error */
/* Synchronization busy register */
#define I2C_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset synchronization busy */
#define I2C_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: SERCOM enable synchronization busy */
#define I2C_SYNCBUSY_SYSOP (1 << 2) /* Bit 2: System operation synchronization busy */
/* Address register */
#define I2C_ADDR_SHIFT (0) /* Bits 0-10: Address */
#define I2C_ADDR_MASK (0x3ff << I2C_ADDR_SHIFT)
# define I2C_ADDR(n) ((uint32-_t(n) << I2C_ADDR_SHIFT)
#define I2C_ADDR_LENEN (1 << 13) /* Bit 13: Transfer length enable */
#define I2C_ADDR_HS (1 << 14) /* Bit 14: High speed */
#define I2C_ADDR_TENBITEN (1 << 15) /* Bit 15: Ten bit addressing enable */
#define I2C_ADDR_LEN_SHIFT (16) /* Bits 16-23: Transaction length */
#define I2C_ADDR_LEN_MASK (0xff << I2C_ADDR_LEN_SHIFT)
# define I2C_ADDR_LEN(n) ((uint32_t)(n) << I2C_ADDR_LEN_SHIFT)
/* Data register */
#define I2C_DATA_MASK (0xff) /* Bits 0-7: Data */
/* Debug control register */
#define I2C_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAML21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_I2C_MASTER_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/saml_i2c_slave.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_I2C_SLAVE_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_I2C_SLAVE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/saml_sercom.h"
#ifdef CONFIG_ARCH_FAMILY_SAML21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* I2C register offsets *****************************************************/
#define SAM_I2C_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_I2C_CTRLB_OFFSET 0x0004 /* Control B register */
#define SAM_I2C_INTENCLR_OFFSET 0x0014 /* Interrupt enable clear register */
#define SAM_I2C_INTENSET_OFFSET 0x0016 /* Interrupt enable set register */
#define SAM_I2C_INTFLAG_OFFSET 0x0018 /* Interrupt flag and status clear register */
#define SAM_I2C_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */
#define SAM_I2C_ADDR_OFFSET 0x0024 /* Address register */
#define SAM_I2C_DATA_OFFSET 0x0028 /* Data register */
/* I2C register addresses ***************************************************/
#define SAM_I2C0_CTRLA (SAM_SERCOM0_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C0_CTRLB (SAM_SERCOM0_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C0_INTENCLR (SAM_SERCOM0_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C0_INTENSET (SAM_SERCOM0_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C0_INTFLAG (SAM_SERCOM0_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C0_SYNCBUSY (SAM_SERCOM0_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C0_ADDR (SAM_SERCOM0_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C0_DATA (SAM_SERCOM0_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C1_CTRLA (SAM_SERCOM1_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C1_CTRLB (SAM_SERCOM1_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C1_INTENCLR (SAM_SERCOM1_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C1_INTENSET (SAM_SERCOM1_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C1_INTFLAG (SAM_SERCOM1_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C1_SYNCBUSY (SAM_SERCOM1_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C1_ADDR (SAM_SERCOM1_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C1_DATA (SAM_SERCOM1_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C2_CTRLA (SAM_SERCOM2_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C2_CTRLB (SAM_SERCOM2_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C2_INTENCLR (SAM_SERCOM2_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C2_INTENSET (SAM_SERCOM2_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C2_INTFLAG (SAM_SERCOM2_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C2_SYNCBUSY (SAM_SERCOM2_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C2_ADDR (SAM_SERCOM2_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C2_DATA (SAM_SERCOM2_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C3_CTRLA (SAM_SERCOM3_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C3_CTRLB (SAM_SERCOM3_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C3_INTENCLR (SAM_SERCOM3_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C3_INTENSET (SAM_SERCOM3_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C3_INTFLAG (SAM_SERCOM3_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C3_SYNCBUSY (SAM_SERCOM3_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C3_ADDR (SAM_SERCOM3_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C3_DATA (SAM_SERCOM3_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C4_CTRLA (SAM_SERCOM4_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C4_CTRLB (SAM_SERCOM4_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C4_INTENCLR (SAM_SERCOM4_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C4_INTENSET (SAM_SERCOM4_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C4_INTFLAG (SAM_SERCOM4_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C4_SYNCBUSY (SAM_SERCOM4_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C4_ADDR (SAM_SERCOM4_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C4_DATA (SAM_SERCOM4_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C5_CTRLA (SAM_SERCOM5_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C5_CTRLB (SAM_SERCOM5_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C5_INTENCLR (SAM_SERCOM5_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C5_INTENSET (SAM_SERCOM5_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C5_INTFLAG (SAM_SERCOM5_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C5_SYNCBUSY (SAM_SERCOM5_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C5_ADDR (SAM_SERCOM5_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C5_DATA (SAM_SERCOM5_BASE+SAM_I2C_DATA_OFFSET)
/* I2C register bit definitions *********************************************/
/* Control A register */
#define I2C_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
#define I2C_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
#define I2C_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */
#define I2C_CTRLA_MODE_MASK (7 << I2C_CTRLA_MODE_SHIFT)
# define I2C_CTRLA_MODE_SLAVE (4 << I2C_CTRLA_MODE_SHIFT) /* I2C slave mode */
#define I2C_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */
#define I2C_CTRLA_PINOUT (1 << 16) /* Bit 16: Pin usage */
# define I2C_CTRLA_1WIRE (0) /* 4-wire operation disabled */
# define I2C_CTRLA_4WIRE I2C_CTRLA_PINOUT /* 4-wire operation enabled */
#define I2C_CTRLA_SDAHOLD_SHIFT (20) /* Bits 20-21: SDA Hold Time */
#define I2C_CTRLA_SDAHOLD_MASK (3 << I2C_CTRLA_SDAHOLD_SHIFT)
# define I2C_CTRLA_SDAHOLD_DIS (0 << I2C_CTRLA_SDAHOLD_SHIFT) /* Disabled */
# define I2C_CTRLA_SDAHOLD_75NS (1 << I2C_CTRLA_SDAHOLD_SHIFT) /* 50-100ns hold time */
# define I2C_CTRLA_SDAHOLD_450NS (2 << I2C_CTRLA_SDAHOLD_SHIFT) /* 300-600ns hold time */
# define I2C_CTRLA_SDAHOLD_600NS (3 << I2C_CTRLA_SDAHOLD_SHIFT) /* 400-800ns hold time */
#define I2C_CTRLA_SEXTTOEN (1 << 23) /* Bit 23: Slave SCL low extend time-out */
#define I2C_CTRLA_SPEED_SHIFT (24) /* Bits 24-25: Trnasfer speed */
#define I2C_CTRLA_SPEED_MASK (3 << I2C_CTRLA_SPEED_SHIFT)
# define I2C_CTRLA_SPEED_STD (0 << I2C_CTRLA_SPEED_SHIFT) /* Standard (<=100KHz) fast <=400KHz */
# define I2C_CTRLA_SPEED_FAST (1 << I2C_CTRLA_SPEED_SHIFT) /* Fast-mode please (<=1MHz) */
# define I2C_CTRLA_SPEED_HIGH (2 << I2C_CTRLA_SPEED_SHIFT) /* High-speed mode (<=3.4Mhz */
#define I2C_CTRLA_SCLSM (1 << 27) /* Bit 27: SCL clock stretch mode */
#define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */
/* Control B register */
#define I2C_CTRLB_SMEN (1 << 8) /* Bit 8: Smart Mode Enable */
#define I2C_CTRLB_GCMD (1 << 9) /* Bit 9: PMBus group command */
#define I2C_CTRLB_AACKEN (1 << 10) /* Bit 10: Automatic acknowledge enable */
#define I2C_CRLB_AMODE_SHIFT (14) /* Bits 14-15: Address Mode */
#define I2C_CRLB_AMODE_MASK (3 << I2C_CRLB_AMODE_SHIFT)
# define I2C_CRLB_AMODE_MASK (0 << I2C_CRLB_AMODE_SHIFT) /* ADDRMASK used to mask ADDR */
# define I2C_CRLB_AMODE_2ADDRS (1 << I2C_CRLB_AMODE_SHIFT) /* Slave 2 addresses: ADDR & ADDRMASK */
# define I2C_CRLB_AMODE_RANGE (2 << I2C_CRLB_AMODE_SHIFT) /* Slave range of addresses: ADDRMASK-ADDR */
#define I2C_CTRLB_CMD_SHIFT (16) /* Bits 16-17: Command */
#define I2C_CTRLB_CMD_MASK (3 << I2C_CTRLB_CMD_SHIFT)
# define I2C_CTRLB_CMD_NOACTION (0 << I2C_CTRLB_CMD_SHIFT) /* No action */
# define I2C_CTRLB_CMD_WAITSTART (2 << I2C_CTRLB_CMD_SHIFT) /* ACK (write) wait for START */
# define I2C_CTRLB_CMD_ACKREAD (3 << I2C_CTRLB_CMD_SHIFT) /* ACK with read (context dependent) */
#define I2C_CTRLB_ACKACT (1 << 18) /* Bit 18: Acknowledge Action */
# define I2C_CTRLB_ACK (0) /* Send ACK */
# define I2C_CTRLB_NCK I2C_CTRLB_ACKACT /* Send NACK */
/* Interrupt enable clear, interrupt enable set, interrupt enable set,
* interrupt flag and status clear registers.
*/
#define I2C_INT_PREC (1 << 0) /* Bit 0: Stop received interrupt */
#define I2C_INT_AMATCH (1 << 1) /* Bit 1: Address match interrupt */
#define I2C_INT_DRDY (1 << 2) /* Bit 2: Data ready interrupt */
#define I2C_INT_ERROR (1 << 7) /* Bit 7: Error interrupt */
#define I2C_INT_ALL (0x87)
/* Synchronization busy register */
#define I2C_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset synchronization busy */
#define I2C_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: SERCOM enable synchronization busy */
/* Address register */
#define I2C_ADDR_GENCEN (1 << 0) /* Bit 0: General Call Address Enable */
#define I2C_ADDR_SHIFT (1) /* Bits 1-10: Address */
#define I2C_ADDR_MASK (0x3ff << I2C_ADDR_SHIFT)
# define I2C_ADDR(n) ((uint32_t)(n) << I2C_ADDR_SHIFT)
#define I2C_ADDR_TENBITEN (1 << 15) /* Bit 15: */
#define I2C_ADDRMASK_SHIFT (17) /* Bits 17-26: Address Mask */
#define I2C_ADDRMASK_MASK (0x3ff << I2C_ADDRMASK_SHIFT)
# define I2C_ADDRMASK(n) ((uint32_t)(n) << I2C_ADDRMASK_SHIFT)
/* Data register */
#define I2C_DATA_MASK (0xff) /* Bits 0-7: Data */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAML21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_I2C_SLAVE_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/saml_mclk.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_MCLK_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_MCLK_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_ARCH_FAMILY_SAML21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* MCLK register offsets ****************************************************/
#define SAM_MCLK_CTRLA_OFFSET 0x0000 /* CTRLA register */
#define SAM_MCLK_INTENCLR_OFFSET 0x0001 /* Interrupt enable clear */
#define SAM_MCLK_INTENSET_OFFSET 0x0002 /* Interrupt enable set */
#define SAM_MCLK_INTFLAG_OFFSET 0x0003 /* Interrupt flag status and clear */
#define SAM_MCLK_CPUDIV_OFFSET 0x0004 /* CPU clock division */
#define SAM_MCLK_LPDIV_OFFSET 0x0005 /* Low-power clock division */
#define SAM_MCLK_BUPDIV_OFFSET 0x0006 /* Backup clock division */
/* 0x0007-0x000f: Reserved */
#define SAM_MCLK_AHBMASK_OFFSET 0x0010 /* AHB mask */
#define SAM_MCLK_APBAMASK_OFFSET 0x0014 /* APBA mask */
#define SAM_MCLK_APBBMASK_OFFSET 0x0018 /* APBB mask */
#define SAM_MCLK_APBCMASK_OFFSET 0x001c /* APBC mask */
#define SAM_MCLK_APBDMASK_OFFSET 0x0020 /* APBD mask */
#define SAM_MCLK_APBEMASK_OFFSET 0x0024 /* APBE mask */
/* MCLK register addresses **************************************************/
#define SAM_MCLK_CTRLA (SAM_MCLK_BASE+SAM_MCLK_CTRLA_OFFSET)
#define SAM_MCLK_INTENCLR (SAM_MCLK_BASE+SAM_MCLK_INTENCLR_OFFSET)
#define SAM_MCLK_INTENSET (SAM_MCLK_BASE+SAM_MCLK_INTENSET_OFFSET)
#define SAM_MCLK_INTFLAG (SAM_MCLK_BASE+SAM_MCLK_INTFLAG_OFFSET)
#define SAM_MCLK_CPUDIV (SAM_MCLK_BASE+SAM_MCLK_CPUDIV_OFFSET)
#define SAM_MCLK_LPDIV (SAM_MCLK_BASE+SAM_MCLK_LPDIV_OFFSET)
#define SAM_MCLK_BUPDIV (SAM_MCLK_BASE+SAM_MCLK_BUPDIV_OFFSET)
#define SAM_MCLK_AHBMASK (SAM_MCLK_BASE+SAM_MCLK_AHBMASK_OFFSET)
#define SAM_MCLK_APBAMASK (SAM_MCLK_BASE+SAM_MCLK_APBAMASK_OFFSET)
#define SAM_MCLK_APBBMASK (SAM_MCLK_BASE+SAM_MCLK_APBBMASK_OFFSET)
#define SAM_MCLK_APBCMASK (SAM_MCLK_BASE+SAM_MCLK_APBCMASK_OFFSET)
#define SAM_MCLK_APBDMASK (SAM_MCLK_BASE+SAM_MCLK_APBDMASK_OFFSET)
#define SAM_MCLK_APBEMASK (SAM_MCLK_BASE+SAM_MCLK_APBEMASK_OFFSET)
/* MCLK register bit definitions ********************************************/
/* CTRLA register */
#define MCLK_CTRLA_CFDEN (1 << 2) /* Bit 2: Clock Failure Detector Enable */
#define MCLK_CTRLA_EMCLK (1 << 4) /* Bit 4: Emergency Clock Select */
/* Interrupt enable clear, Interrupt enable set,
* and Interrupt flag status and clear.
*/
#define MCLK_INT_CKRDY (1 << 0) /* Bit 0: Clock ready */
/* CPU clock division (8-bit divider) */
#define MCLK_CPUDIV_DIV1 0x01
#define MCLK_CPUDIV_DIV2 0x02
#define MCLK_CPUDIV_DIV4 0x04
#define MCLK_CPUDIV_DIV8 0x08
#define MCLK_CPUDIV_DIV16 0x10
#define MCLK_CPUDIV_DIV32 0x20
#define MCLK_CPUDIV_DIV64 0x40
#define MCLK_CPUDIV_DIV128 0x80
/* Low-power clock division (8-bit divider) */
#define MCLK_LPDIV_DIV1 0x01
#define MCLK_LPDIV_DIV2 0x02
#define MCLK_LPDIV_DIV4 0x04
#define MCLK_LPDIV_DIV8 0x08
#define MCLK_LPDIV_DIV16 0x10
#define MCLK_LPDIV_DIV32 0x20
#define MCLK_LPDIV_DIV64 0x40
#define MCLK_LPDIV_DIV128 0x80
/* Backup clock division (8-bit divider) */
#define MCLK_BUPDIV_DIV1 0x01
#define MCLK_BUPDIV_DIV2 0x02
#define MCLK_BUPDIV_DIV4 0x04
#define MCLK_BUPDIV_DIV8 0x08
#define MCLK_BUPDIV_DIV16 0x10
#define MCLK_BUPDIV_DIV32 0x20
#define MCLK_BUPDIV_DIV64 0x40
#define MCLK_BUPDIV_DIV128 0x80
/* AHB mask */
#define MCLK_AHBMASK_APBA (1 << 0) /* Bit 0: APBA AHB clock enable */
#define MCLK_AHBMASK_APBB (1 << 1) /* Bit 1: APBB AHB clock enable */
#define MCLK_AHBMASK_APBC (1 << 2) /* Bit 2: APBC AHB clock enable */
#define MCLK_AHBMASK_APBD (1 << 3) /* Bit 3: APBD AHB clock enable */
#define MCLK_AHBMASK_APBE (1 << 4) /* Bit 4: APBE AHB clock enable */
#define MCLK_AHBMASK_DSU (1 << 5) /* Bit 5: DSU AHB clock enable */
#define MCLK_AHBMASK_NVMCTRL (1 << 8) /* Bit 8: NVMCTRL AHB clock enable */
#define MCLK_AHBMASK_DMAC (1 << 11) /* Bit 11: DMAC AHB clock enable */
#define MCLK_AHBMASK_USB (1 << 12) /* Bit 12: USB AHB clock enable */
#define MCLK_AHBMASK_PAC (1 << 14) /* Bit 14: PAC AHB clock enable */
/* APBA mask */
#define MCLK_APBAMASK_PM (1 << 0) /* Bit 0: PM APBA clock enable */
#define MCLK_APBAMASK_MCLK (1 << 1) /* Bit 1: MCLK APBA clock enable */
#define MCLK_APBAMASK_RSTC (1 << 2) /* Bit 2: RSTC APBA clock enable */
#define MCLK_APBAMASK_OSCCTRL (1 << 3) /* Bit 3: OSCCTRL APBA clock enable */
#define MCLK_APBAMASK_OSC32KCTRL (1 << 4) /* Bit 4: OSC32KCTRL APBA clock enable */
#define MCLK_APBAMASK_SUPC (1 << 5) /* Bit 5: SUPC APBA clock enable */
#define MCLK_APBAMASK_GCLK (1 << 6) /* Bit 6: GCLK APBA clock enable */
#define MCLK_APBAMASK_WDT (1 << 7) /* Bit 7: WDT APBA clock enable */
#define MCLK_APBAMASK_RTC (1 << 8) /* Bit 8: RTC APBA clock enable */
#define MCLK_APBAMASK_EIC (1 << 9) /* Bit 9: EIC APBA clock enable */
#define MCLK_APBAMASK_PORT (1 << 10) /* Bit 10: PORT APBA clock enable */
/* APBB mask */
#define MCLK_APBBMASK_USB (1 << 0) /* Bit 0: USB APBB clock enable */
#define MCLK_APBBMASK_DSU (1 << 1) /* Bit 1: DSU APBB clock enable */
#define MCLK_APBBMASK_NVMCTRL (1 << 2) /* Bit 2: NVMCTRL APBB clock enable */
/* APBC mask */
#define MCLK_APBCMASK_SERCOM(n) (1 << (n)) /* Bit n: SERCOMn APBC clock enable, n=0-4 */
# define MCLK_APBCMASK_SERCOM0 (1 << 0) /* Bit 0: SERCOM0 APBC clock enable */
# define MCLK_APBCMASK_SERCOM1 (1 << 1) /* Bit 1: SERCOM1 APBC clock enable */
# define MCLK_APBCMASK_SERCOM2 (1 << 2) /* Bit 2: SERCOM2 APBC clock enable */
# define MCLK_APBCMASK_SERCOM3 (1 << 3) /* Bit 3: SERCOM3 APBC clock enable */
# define MCLK_APBCMASK_SERCOM4 (1 << 4) /* Bit 4: SERCOM4 APBC clock enable */
#define MCLK_APBCMASK_TCC0 (1 << 5) /* Bit 5: TCC0 APBC clock enable */
#define MCLK_APBCMASK_TCC1 (1 << 6) /* Bit 6: TCC1 APBC clock enable */
#define MCLK_APBCMASK_TCC2 (1 << 7) /* Bit 7: TCC2 APBC clock enable */
#define MCLK_APBCMASK_TC0 (1 << 8) /* Bit 8: TC0 APBC clock enable */
#define MCLK_APBCMASK_TC1 (1 << 9) /* Bit 9: TC1 APBC clock enable */
#define MCLK_APBCMASK_TC2 (1 << 10) /* Bit 10: TC2 APBC clock enable */
#define MCLK_APBCMASK_TC3 (1 << 11) /* Bit 11: TC3 APBC clock enable */
#define MCLK_APBCMASK_DAC (1 << 12) /* Bit 12: DAC APBC clock enable */
#define MCLK_APBCMASK_AES (1 << 13) /* Bit 13: AES APBC clock enable */
#define MCLK_APBCMASK_TRNG (1 << 14) /* Bit 14: TRNG APBC clock enable */
/* APBD mask */
#define MCLK_APBDMASK_EVSYS (1 << 0) /* Bit 0: EVSYS APBD clock enable */
#define MCLK_APBDMASK_SERCOM5 (1 << 1) /* Bit 1: SERCOM5 APBD clock enable */
#define MCLK_APBDMASK_TC4 (1 << 2) /* Bit 2: TC4 APBD clock enable */
#define MCLK_APBDMASK_ADC (1 << 3) /* Bit 3: ADC APBD clock enable */
#define MCLK_APBDMASK_AC (1 << 4) /* Bit 4: AC APBD clock enable */
#define MCLK_APBDMASK_PTC (1 << 5) /* Bit 5: PTC APBD clock enable */
#define MCLK_APBDMASK_OPAMP (1 << 6) /* Bit 6: OpAmp APBD clock enable */
#define MCLK_APBDMASK_CCL (1 << 7) /* Bit 7: CCL APBD clock enable */
/* APBE mask */
#define MCLK_APBEMASK_PAC (1 << 0) /* Bit 0: PAC APBE clock enable */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAML21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_MCLK_H */

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/****************************************************************************
* arch/arm/src/samd2l2/hardware/saml_nvmctrl.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* References:
* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_NVMCTRL_H
#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_NVMCTRL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_ARCH_FAMILY_SAML21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* NVMCTRL register offsets *************************************************/
#define SAM_NVMCTRL_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_NVMCTRL_CTRLB_OFFSET 0x0004 /* Control B register */
#define SAM_NVMCTRL_PARAM_OFFSET 0x0008 /* NVM parameter register */
#define SAM_NVMCTRL_INTENCLR_OFFSET 0x000c /* Interrupt clear register */
#define SAM_NVMCTRL_INTENSET_OFFSET 0x0010 /* Interrupt set register */
#define SAM_NVMCTRL_INTFLAG_OFFSET 0x0014 /* Interface flags status and clear register */
#define SAM_NVMCTRL_STATUS_OFFSET 0x0018 /* Status register */
#define SAM_NVMCTRL_ADDR_OFFSET 0x001c /* Address register */
#define SAM_NVMCTRL_LOCK_OFFSET 0x0020 /* Lock section register */
/* NVMCTRL register addresses ***********************************************/
#define SAM_NVMCTRL_CTRLA (SAM_NVMCTRL_BASE+SAM_NVMCTRL_CTRLA_OFFSET)
#define SAM_NVMCTRL_CTRLB (SAM_NVMCTRL_BASE+SAM_NVMCTRL_CTRLB_OFFSET)
#define SAM_NVMCTRL_INTENCLR (SAM_NVMCTRL_BASE+SAM_NVMCTRL_INTENCLR_OFFSET)
#define SAM_NVMCTRL_INTENSET (SAM_NVMCTRL_BASE+SAM_NVMCTRL_INTENSET_OFFSET)
#define SAM_NVMCTRL_INTFLAG (SAM_NVMCTRL_BASE+SAM_NVMCTRL_INTFLAG_OFFSET)
#define SAM_NVMCTRL_STATUS (SAM_NVMCTRL_BASE+SAM_NVMCTRL_STATUS_OFFSET)
#define SAM_NVMCTRL_ADDR (SAM_NVMCTRL_BASE+SAM_NVMCTRL_ADDR_OFFSET)
#define SAM_NVMCTRL_LOCK (SAM_NVMCTRL_BASE+SAM_NVMCTRL_LOCK_OFFSET)
/* NVMCTRL register bit definitions *****************************************/
/* Control A register */
#define NVMCTRL_CTRLA_CMD_SHIFT (0) /* Bits 0-6: Command */
#define NVMCTRL_CTRLA_CMD_MASK (0x7f << NVMCTRL_CTRLA_CMD_SHIFT)
# define NVMCTRL_CTRLA_CMD_ER (0x02 << NVMCTRL_CTRLA_CMD_SHIFT) /* Erase Row */
# define NVMCTRL_CTRLA_CMD_WP (0x04 << NVMCTRL_CTRLA_CMD_SHIFT) /* Write Page */
# define NVMCTRL_CTRLA_CMD_EAR (0x05 << NVMCTRL_CTRLA_CMD_SHIFT) /* Erase Auxiliary Row */
# define NVMCTRL_CTRLA_CMD_WAP (0x06 << NVMCTRL_CTRLA_CMD_SHIFT) /* Write Auxiliary Page */
# define NVMCTRL_CTRLA_CMD_RWWEEER (0x1a << NVMCTRL_CTRLA_CMD_SHIFT) /* RWWEE Erase Row */
# define NVMCTRL_CTRLA_CMD_RWWEEWP (0x1a << NVMCTRL_CTRLA_CMD_SHIFT) /* RWWEE Write page */
# define NVMCTRL_CTRLA_CMD_LR (0x40 << NVMCTRL_CTRLA_CMD_SHIFT) /* Lock Region */
# define NVMCTRL_CTRLA_CMD_UR (0x41 << NVMCTRL_CTRLA_CMD_SHIFT) /* Unlock Region */
# define NVMCTRL_CTRLA_CMD_SPRM (0x42 << NVMCTRL_CTRLA_CMD_SHIFT) /* Set power reduction mode */
# define NVMCTRL_CTRLA_CMD_CPRM (0x43 << NVMCTRL_CTRLA_CMD_SHIFT) /* Clear power reduction mode */
# define NVMCTRL_CTRLA_CMD_PBC (0x44 << NVMCTRL_CTRLA_CMD_SHIFT) /* Page Buffer Clear */
# define NVMCTRL_CTRLA_CMD_SSB (0x45 << NVMCTRL_CTRLA_CMD_SHIFT) /* Set Security Bit */
# define NVMCTRL_CTRLA_CMD_INVALL (0x46 << NVMCTRL_CTRLA_CMD_SHIFT) /* Invalidate all cache lines */
#define NVMCTRL_CTRLA_CMDEX_SHIFT (8) /* Bits 8-15: Command Execution */
#define NVMCTRL_CTRLA_CMDEX_MASK (0xff << NVMCTRL_CTRLA_CMDEX_SHIFT)
# define NVMCTRL_CTRLA_CMDEX (0xa5 << NVMCTRL_CTRLA_CMDEX_SHIFT)
/* Control B register */
#define NVMCTRL_CTRLB_RWS_SHIFT (1) /* Bits 1-4: NVM Read Wait States */
#define NVMCTRL_CTRLB_RWS_MASK (15 << NVMCTRL_CTRLB_RWS_SHIFT)
# define NVMCTRL_CTRLB_RWS(n) ((uint32_t)(n) << NVMCTRL_CTRLB_RWS_SHIFT)
#define NVMCTRL_CTRLB_MANW (1 << 7) /* Bit 7: Manual Write */
#define NVMCTRL_CTRLB_SLEEPPRM_SHIFT (8) /* Bits 8-9: Power Reduction Mode during Sleep */
#define NVMCTRL_CTRLB_SLEEPPRM_MASK (3 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT)
# define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (0 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Exit low power on first access */
# define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (1 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Exit low power when exit sleep */
# define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (3 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Auto power reduction disabled */
#define NVMCTRL_CTRLB_READMODE_SHIFT (16) /* Bits 16-17: NVMCTRL Read Mode */
#define NVMCTRL_CTRLB_READMODE_MASK (3 << NVMCTRL_CTRLB_READMODE_SHIFT)
# define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (0 << NVMCTRL_CTRLB_READMODE_SHIFT) /* No extra wait states on miss */
# define NVMCTRL_CTRLB_READMODE_LOW_POWER (1 << NVMCTRL_CTRLB_READMODE_SHIFT) /* Insert wait/reduce power */
# define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (2 << NVMCTRL_CTRLB_READMODE_SHIFT) /* Same wait on all access */
#define NVMCTRL_CTRLB_CACHEDIS (1 << 18) /* Bit 18: Cache Disable */
/* NVM parameter register */
#define NVMCTRL_PARAM_NVMP_SHIFT (0) /* Bits 0-15: NVM Pages */
#define NVMCTRL_PARAM_NVMP_MASK (0xffff << NVMCTRL_PARAM_NVMP_SHIFT)
# define NVMCTRL_PARAM_NVMP(n) ((uint32_t)(n) << NVMCTRL_PARAM_NVMP_SHIFT)
#define NVMCTRL_PARAM_PSZ_SHIFT (16) /* Bits 16-18: Page Size */
#define NVMCTRL_PARAM_PSZ_MASK (7 << NVMCTRL_PARAM_PSZ_SHIFT)
# define NVMCTRL_PARAM_PSZ_8B (0 << NVMCTRL_PARAM_PSZ_SHIFT) /* 8 bytes */
# define NVMCTRL_PARAM_PSZ_16B (1 << NVMCTRL_PARAM_PSZ_SHIFT) /* 16 bytes */
# define NVMCTRL_PARAM_PSZ_32B (2 << NVMCTRL_PARAM_PSZ_SHIFT) /* 32 bytes */
# define NVMCTRL_PARAM_PSZ_64B (3 << NVMCTRL_PARAM_PSZ_SHIFT) /* 64 bytes */
# define NVMCTRL_PARAM_PSZ_128B (4 << NVMCTRL_PARAM_PSZ_SHIFT) /* 128 bytes */
# define NVMCTRL_PARAM_PSZ_256B (5 << NVMCTRL_PARAM_PSZ_SHIFT) /* 256 bytes */
# define NVMCTRL_PARAM_PSZ_512B (6 << NVMCTRL_PARAM_PSZ_SHIFT) /* 512 bytes */
# define NVMCTRL_PARAM_PSZ_1KB (7 << NVMCTRL_PARAM_PSZ_SHIFT) /* 1024 bytes */
#define NVMCTRL_PARAM_RWWEEP_SHIFT (20) /* Bits 20-31: Read while write EEPROM emulation area pages */
#define NVMCTRL_PARAM_RWWEEP_MASK (0xfff << NVMCTRL_PARAM_RWWEEP_SHIFT)
# define NVMCTRL_PARAM_RWWEEP(n) ((uint32_t)(n) << NVMCTRL_PARAM_RWWEEP_SHIFT)
/* Interrupt clear register */
/* Interrupt set register */
/* Interface flags status and clear register */
#define NVMCTRL_INT_READY (1 << 0) /* Bit 0: NVM Ready Interrupt */
#define NVMCTRL_INT_ERROR (1 << 1) /* Bit 1: Error Interrupt */
/* Status register */
#define NVMCTRL_STATUS_PRM (1 << 0) /* Bit 0: Power Reduction Mode */
#define NVMCTRL_STATUS_LOAD (1 << 1) /* Bit 1: NVM Page Buffer Active Loading */
#define NVMCTRL_STATUS_PROGE (1 << 2) /* Bit 2: Programming Error Status */
#define NVMCTRL_STATUS_LOCKE (1 << 3) /* Bit 3: Lock Error Status */
#define NVMCTRL_STATUS_NVME (1 << 4) /* Bit 4: NVM Error */
#define NVMCTRL_STATUS_SB (1 << 8) /* Bit 8: Security Bit Status */
/* Address register */
#define NVMCTRL_ADDR_MASK (0x001fffff) /* Bits 0-20: NVM Address */
/* Lock section register */
#define NVMCTRL_LOCK_REGION(n) (1 << (n)) /* Region n is locked */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAML21 */
#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_NVMCTRL_H */

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